ring vco schematics
diff --git a/xschem/ring_vco/bsim4v5.out b/xschem/ring_vco/bsim4v5.out
new file mode 100644
index 0000000..b5885f2
--- /dev/null
+++ b/xschem/ring_vco/bsim4v5.out
@@ -0,0 +1,5 @@
+BSIM4v5: Berkeley Short Channel IGFET Model-4
+Developed by Xuemei (Jane) Xi, Mohan Dunga, Prof. Ali Niknejad and Prof. Chenming Hu in 2003.
+
+++++++++++ BSIM4v5 PARAMETER CHECKING BELOW ++++++++++
+Model = x1.xm1:sky130_fd_pr__nfet_01v8__model.161
diff --git a/xschem/ring_vco/not.sch b/xschem/ring_vco/not.sch
new file mode 100644
index 0000000..ab0740c
--- /dev/null
+++ b/xschem/ring_vco/not.sch
@@ -0,0 +1,50 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 210 50 210 140 { lab=out}
+N 130 170 170 170 { lab=in}
+N 130 20 170 20 { lab=in}
+N 130 20 130 170 { lab=in}
+N 80 90 130 90 { lab=in}
+N 210 90 300 90 { lab=out}
+N 210 200 210 240 { lab=vss}
+N 210 170 280 170 { lab=vss}
+N 280 170 280 240 { lab=vss}
+N 210 240 280 240 { lab=vss}
+N 80 240 210 240 { lab=vss}
+N 210 -50 210 -10 { lab=vdd}
+N 80 -50 210 -50 { lab=vdd}
+N 210 -50 280 -50 { lab=vdd}
+N 280 -50 280 20 { lab=vdd}
+N 210 20 280 20 { lab=vdd}
+C {sky130_fd_pr/nfet_01v8.sym} 190 170 0 0 {name=M1
+L=0.15
+W=0.45
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 190 20 0 0 {name=M2
+L=0.15
+W=0.9
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {ipin.sym} 80 -50 0 0 {name=p1 lab=vdd}
+C {ipin.sym} 80 90 0 0 {name=p2 lab=in
+}
+C {ipin.sym} 80 240 0 0 {name=p3 lab=vss}
+C {opin.sym} 300 90 0 0 {name=p4 lab=out
+}
diff --git a/xschem/ring_vco/not.spice b/xschem/ring_vco/not.spice
new file mode 100644
index 0000000..8308a4a
--- /dev/null
+++ b/xschem/ring_vco/not.spice
@@ -0,0 +1,11 @@
+**.subckt not vdd in vss out
+*.ipin vdd
+*.ipin in
+*.ipin vss
+*.opin out
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+**.ends
+.end
diff --git a/xschem/ring_vco/not.sym b/xschem/ring_vco/not.sym
new file mode 100644
index 0000000..09e1378
--- /dev/null
+++ b/xschem/ring_vco/not.sym
@@ -0,0 +1,27 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 0 -30 0 -10 {}
+L 4 -40 0 -20 0 {}
+L 4 30 0 50 0 {}
+L 4 0 10 0 30 {}
+L 4 -20 20 20 0 {}
+L 4 -20 -20 20 0 {}
+L 4 -20 -20 -20 20 {}
+B 5 -2.5 -32.5 2.5 -27.5 {name=vdd dir=in name=p1 }
+B 5 -42.5 -2.5 -37.5 2.5 {name=in dir=in name=p2 }
+B 5 47.5 -2.5 52.5 2.5 {name=out dir=out name=p4 }
+B 5 -2.5 27.5 2.5 32.5 {name=vss dir=in name=p3 }
+A 4 25 -0.4000000000000057 5.015974481593782 355.4260787400991 360 {}
+T {@symname} 16 4 0 0 0.3 0.3 {}
+T {@name} 15 -22 0 0 0.2 0.2 {}
+T {vdd} -6 -35 1 0 0.2 0.2 {}
+T {in} -35 -14 0 0 0.2 0.2 {}
+T {out} 55 -14 0 1 0.2 0.2 {}
+T {vss} 14 15 1 0 0.2 0.2 {}
diff --git a/xschem/ring_vco/not_test.sch b/xschem/ring_vco/not_test.sch
new file mode 100644
index 0000000..7ce6b59
--- /dev/null
+++ b/xschem/ring_vco/not_test.sch
@@ -0,0 +1,80 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N -60 130 -60 160 { lab=GND}
+N 30 130 30 160 { lab=vss}
+N 30 40 30 70 { lab=vdd}
+N -60 40 -60 70 { lab=vss}
+N -20 -70 -20 -40 { lab=vss}
+N -20 -160 -20 -130 { lab=in}
+N 320 60 320 100 { lab=out}
+N 290 60 320 60 { lab=out}
+N 320 160 320 190 { lab=vss}
+N 170 60 200 60 { lab=in}
+N 240 90 240 120 { lab=vss}
+N 240 0 240 30 { lab=vdd}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 240 60 0 0 {name=x1}
+C {vsource.sym} -60 100 0 0 {name=V1 value=DC\{Vss\}}
+C {vsource.sym} 30 100 0 0 {name=V2 value=DC\{Vdd\}}
+C {gnd.sym} -60 160 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -60 40 1 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 30 160 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 30 40 1 0 {name=l9 sig_type=std_logic lab=vdd
+}
+C {netlist_not_shown.sym} 260 -140 0 0 {name=SIMULATION only_toplevel=false 
+
+value="
+
+
+* Circuit Parameters
+.param vdd  = 1.8
+.param vss  = 0.0
+.param vin  = 1.8
+.param iref = 200u
+.options TEMP = 65.0
+
+* Include Models
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib TT
+
+* OP Parameters & Singals to save
+.save all
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[id] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vth] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vdsat] @M.X1.XM1.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM1.msky130_fd_pr__nfet_01v8[gds]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[id] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gds]
+
+*Simulations
+.control
+  tran 0.1n 0.5u
+  setplot tran1
+  plot v(out) v(in)
+  *write ~/caravel_fulgor_opamp/xschem/sim_results/opamp_closeloop_tran1.raw
+  
+  reset
+  dc V3 0 1.8 0.01
+  setplot dc1
+  plot v(out) v(in)
+  
+  reset
+  op
+  print all
+  
+.endc
+
+.end
+"}
+C {vsource.sym} -20 -100 0 0 {name=V3 value="PULSE(0 \{Vin\} 1ps 1ps 1ps 50ns 100ns) DC\{Vin\}"}
+C {lab_pin.sym} -20 -40 3 0 {name=l22 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -20 -160 1 0 {name=l23 sig_type=std_logic lab=in}
+C {capa.sym} 320 130 0 0 {name=C1
+m=1
+value=1f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 320 190 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 240 120 3 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 240 0 1 0 {name=l6 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 170 60 0 0 {name=l7 sig_type=std_logic lab=in}
+C {lab_pin.sym} 320 60 2 0 {name=l8 sig_type=std_logic lab=out}
diff --git a/xschem/ring_vco/not_test.spice b/xschem/ring_vco/not_test.spice
new file mode 100644
index 0000000..a34117b
--- /dev/null
+++ b/xschem/ring_vco/not_test.spice
@@ -0,0 +1,67 @@
+**.subckt not_test
+x1 vdd in out vss not
+V1 vss GND DC{Vss} 
+V2 vdd vss DC{Vdd} 
+V3 in vss PULSE(0 {Vin} 1ps 1ps 1ps 50ns 100ns) DC{Vin} 
+C1 out vss 1f m=1
+**** begin user architecture code
+
+
+
+
+* Circuit Parameters
+.param vdd  = 1.8
+.param vss  = 0.0
+.param vin  = 1.8
+.param iref = 200u
+.options TEMP = 65.0
+
+* Include Models
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib TT
+
+* OP Parameters & Singals to save
+.save all  @M.X1.XM1.msky130_fd_pr__nfet_01v8[id] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vth]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vdsat]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM1.msky130_fd_pr__nfet_01v8[gds]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gds]
+
+*Simulations
+.control
+  tran 0.1n 0.5u
+  setplot tran1
+  plot v(out) v(in)
+  *write ~/caravel_fulgor_opamp/xschem/sim_results/opamp_closeloop_tran1.raw
+
+  reset
+  dc V3 0 1.8 0.01
+  setplot dc1
+  plot v(out) v(in)
+
+  reset
+  op
+  print all
+
+.endc
+
+.end
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  /home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym # of pins=4
+
+.subckt not  vdd in out vss
+*.ipin vdd
+*.ipin in
+*.ipin vss
+*.opin out
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+.ends
+
+.GLOBAL GND
+.end
diff --git a/xschem/ring_vco/ring_vco.sch b/xschem/ring_vco/ring_vco.sch
new file mode 100644
index 0000000..e2ab5e0
--- /dev/null
+++ b/xschem/ring_vco/ring_vco.sch
@@ -0,0 +1,261 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 480 -300 480 -270 { lab=GND}
+N 570 -300 570 -270 { lab=vss}
+N 570 -390 570 -360 { lab=vdd}
+N 480 -390 480 -360 { lab=vss}
+N 0 30 -0 60 { lab=9}
+N 0 -60 -0 -30 { lab=10}
+N -80 0 -40 -0 { lab=out_ring}
+N 0 -80 0 -60 { lab=10}
+N 50 -0 70 0 { lab=o1}
+N 160 -0 180 -0 { lab=o2}
+N 270 -0 290 0 { lab=o3}
+N 380 -0 400 -0 { lab=o4}
+N 490 -0 510 0 { lab=o5}
+N 110 30 110 60 { lab=9}
+N 220 30 220 60 { lab=9}
+N 330 30 330 60 { lab=9}
+N 440 30 440 60 { lab=9}
+N 550 30 550 60 { lab=9}
+N 110 -80 110 -30 { lab=10}
+N 220 -80 220 -30 { lab=10}
+N 330 -80 330 -30 { lab=10}
+N 440 -80 440 -30 { lab=10}
+N 550 -80 550 -30 { lab=10}
+N 920 0 1020 0 { lab=out}
+N -0 -80 550 -80 { lab=10}
+N 550 -80 640 -80 { lab=10}
+N 290 -200 290 -80 { lab=10}
+N -160 -230 250 -230 { lab=5}
+N -200 -200 -200 150 { lab=5}
+N -160 180 250 180 { lab=in}
+N -200 -310 -200 -260 { lab=vdd}
+N -200 -310 290 -310 { lab=vdd}
+N 290 -310 290 -260 { lab=vdd}
+N 290 -230 360 -230 { lab=vdd}
+N 360 -310 360 -230 { lab=vdd}
+N 290 -310 360 -310 { lab=vdd}
+N -270 -230 -200 -230 { lab=vdd}
+N -270 -310 -270 -230 { lab=vdd}
+N -270 -310 -200 -310 { lab=vdd}
+N -200 210 -200 250 { lab=vss}
+N -200 250 290 250 { lab=vss}
+N 290 210 290 250 { lab=vss}
+N 290 180 370 180 { lab=vss}
+N 370 180 370 250 { lab=vss}
+N 290 250 370 250 { lab=vss}
+N -280 180 -200 180 { lab=vss}
+N -280 180 -280 250 { lab=vss}
+N -280 250 -200 250 { lab=vss}
+N -200 -140 -120 -140 { lab=5}
+N -120 -230 -120 -140 { lab=5}
+N 760 -30 760 30 { lab=out_ring}
+N 760 0 820 0 { lab=out_ring}
+N 690 60 720 60 { lab=o6}
+N 690 -60 690 60 { lab=o6}
+N 690 -60 720 -60 { lab=o6}
+N 760 -120 760 -90 { lab=10}
+N 690 -120 760 -120 { lab=10}
+N 690 -120 690 -80 { lab=10}
+N 640 -80 690 -80 { lab=10}
+N 760 90 760 120 { lab=9}
+N 690 120 760 120 { lab=9}
+N 690 80 690 120 { lab=9}
+N 290 80 690 80 { lab=9}
+N 290 80 290 150 { lab=9}
+N 330 60 330 80 { lab=9}
+N 440 60 440 80 { lab=9}
+N 550 60 550 80 { lab=9}
+N -0 80 290 80 { lab=9}
+N -0 60 0 80 { lab=9}
+N 110 60 110 80 { lab=9}
+N 220 60 220 80 { lab=9}
+N 600 0 690 -0 { lab=o6}
+N 920 -30 920 30 { lab=out}
+N 920 90 920 120 { lab=vss}
+N 920 120 1010 120 { lab=vss}
+N 1010 60 1010 120 { lab=vss}
+N 920 60 1010 60 { lab=vss}
+N 850 60 880 60 { lab=out_ring}
+N 850 -60 850 60 { lab=out_ring}
+N 850 -60 880 -60 { lab=out_ring}
+N 820 -0 850 -0 { lab=out_ring}
+N 920 -120 920 -90 { lab=vdd}
+N 920 -120 1000 -120 { lab=vdd}
+N 1000 -120 1000 -60 { lab=vdd}
+N 920 -60 1000 -60 { lab=vdd}
+N 670 -300 670 -270 { lab=vss}
+N 670 -390 670 -360 { lab=in}
+N 760 -60 820 -60 { lab=10}
+N 820 -120 820 -60 { lab=10}
+N 760 -120 820 -120 { lab=10}
+N 760 60 840 60 { lab=9}
+N 840 60 840 120 { lab=9}
+N 760 120 840 120 { lab=9}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 0 0 0 0 {name=x1}
+C {vsource.sym} 480 -330 0 0 {name=V1 value=DC\{Vss\}}
+C {vsource.sym} 570 -330 0 0 {name=V2 value=DC\{Vdd\}}
+C {gnd.sym} 480 -270 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 480 -390 1 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 570 -270 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 570 -390 1 0 {name=l9 sig_type=std_logic lab=vdd
+}
+C {netlist_not_shown.sym} 790 -380 0 0 {name=SIMULATION only_toplevel=false 
+
+value="
+
+
+* Circuit Parameters
+.param vdd  = 1.8
+.param vss  = 0.0
+.param vin  = 0.6
+.param iref = 200u
+.options TEMP = 65.0
+
+* Include Models
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib TT
+
+* OP Parameters & Singals to save
+.save all
++ @M.X2.XM1.msky130_fd_pr__nfet_01v8[id] @M.X2.XM1.msky130_fd_pr__nfet_01v8[vth] @M.X2.XM1.msky130_fd_pr__nfet_01v8[vgs] @M.X2.XM1.msky130_fd_pr__nfet_01v8[vds] @M.X2.XM1.msky130_fd_pr__nfet_01v8[vdsat] @M.X2.XM1.msky130_fd_pr__nfet_01v8[gm] @M.X2.XM1.msky130_fd_pr__nfet_01v8[gds] @M.X2.XM1.msky130_fd_pr__nfet_01v8[cgs] @M.X2.XM1.msky130_fd_pr__nfet_01v8[cgd]
++ @M.X2.XM2.msky130_fd_pr__pfet_01v8[id] @M.X2.XM2.msky130_fd_pr__pfet_01v8[vth] @M.X2.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X2.XM2.msky130_fd_pr__pfet_01v8[vds] @M.X2.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X2.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X2.XM2.msky130_fd_pr__pfet_01v8[gds] @M.X2.XM1.msky130_fd_pr__nfet_01v8[cgs] @M.X2.XM1.msky130_fd_pr__nfet_01v8[cgd]
+
+*Simulations
+.control
+  *reset
+  tran 0.1n 0.5u
+  setplot tran1
+  plot v(out) v(in)
+  *write ~/caravel_fulgor_opamp/xschem/sim_results/opamp_closeloop_tran1.raw
+  
+  
+  *dc V3 0 1.8 0.01
+  *setplot dc1
+  *plot v(out1) v(out2) v(out3) v(in)
+  
+  reset
+  op
+  setplot op1
+  
+.endc
+
+.end
+"}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 110 0 0 0 {name=x2}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 220 0 0 0 {name=x3}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 330 0 0 0 {name=x4}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 440 0 0 0 {name=x5}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 550 0 0 0 {name=x6}
+C {lab_pin.sym} -80 0 0 0 {name=l5 sig_type=std_logic lab=out_ring}
+C {lab_wire.sym} 970 -120 0 0 {name=l11 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 970 120 0 0 {name=l14 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/nfet_01v8.sym} 740 60 0 0 {name=M1
+L=0.15
+W=1.2
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 740 -60 0 0 {name=M2
+L=0.15
+W=1.5
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=2
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 900 60 0 0 {name=M3
+L=0.15
+W=0.6
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 900 -60 0 0 {name=M4
+L=0.15
+W=1.05
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 820 0 0 0 {name=l4 sig_type=std_logic lab=out_ring}
+C {lab_pin.sym} 1020 0 2 0 {name=l6 sig_type=std_logic lab=out}
+C {sky130_fd_pr/pfet_01v8.sym} 270 -230 0 0 {name=M5
+L=0.15
+W=1.05
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 270 180 0 0 {name=M6
+L=0.15
+W=1.05
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} -180 -230 0 1 {name=M7
+L=0.15
+W=0.9
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} -180 180 0 1 {name=M8
+L=0.15
+W=0.9
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 60 -230 0 0 {name=l7 sig_type=std_logic lab=5}
+C {lab_wire.sym} 60 -310 0 0 {name=l8 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 40 250 0 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 40 180 0 0 {name=l12 sig_type=std_logic lab=in}
+C {lab_wire.sym} 290 -140 3 0 {name=l13 sig_type=std_logic lab=10}
+C {lab_wire.sym} 290 100 3 0 {name=l15 sig_type=std_logic lab=9}
+C {lab_wire.sym} 60 0 0 0 {name=l16 sig_type=std_logic lab=o1}
+C {lab_wire.sym} 170 0 0 0 {name=l17 sig_type=std_logic lab=o2}
+C {lab_wire.sym} 280 0 0 0 {name=l18 sig_type=std_logic lab=o3}
+C {lab_wire.sym} 390 0 0 0 {name=l19 sig_type=std_logic lab=o4}
+C {lab_wire.sym} 500 0 0 0 {name=l20 sig_type=std_logic lab=o5}
+C {lab_wire.sym} 630 0 0 0 {name=l21 sig_type=std_logic lab=o6}
+C {vsource.sym} 670 -330 0 0 {name=V3 value=DC\{Vin\}}
+C {lab_pin.sym} 670 -270 3 0 {name=l22 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 670 -390 1 0 {name=l23 sig_type=std_logic lab=in}
diff --git a/xschem/ring_vco/ring_vco.spice b/xschem/ring_vco/ring_vco.spice
new file mode 100644
index 0000000..c40e019
--- /dev/null
+++ b/xschem/ring_vco/ring_vco.spice
@@ -0,0 +1,91 @@
+**.subckt ring_vco
+x1 10 out_ring o1 9 not
+V1 vss GND DC{Vss} 
+V2 vdd vss DC{Vdd} 
+x2 10 o1 o2 9 not
+x3 10 o2 o3 9 not
+x4 10 o3 o4 9 not
+x5 10 o4 o5 9 not
+x6 10 o5 o6 9 not
+XM1 out_ring o6 9 9 sky130_fd_pr__nfet_01v8 W=1.2 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM2 out_ring o6 10 10 sky130_fd_pr__pfet_01v8 W=1.2 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=2 m=2 
+XM3 out out_ring vss vss sky130_fd_pr__nfet_01v8 W=0.6 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM4 out out_ring vdd vdd sky130_fd_pr__pfet_01v8 W=1.05 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM5 10 5 vdd vdd sky130_fd_pr__pfet_01v8 W=1.2 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=2 m=2 
+XM6 9 in vss vss sky130_fd_pr__nfet_01v8 W=1.2 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM7 5 5 vdd vdd sky130_fd_pr__pfet_01v8 W=1.2 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=2 m=2 
+XM8 5 in vss vss sky130_fd_pr__nfet_01v8 W=1.2 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+V3 in vss DC{Vin} 
+**** begin user architecture code
+
+
+
+
+* Circuit Parameters
+.param vdd  = 1.8
+.param vss  = 0.0
+.param vin  = 0.3
+.param iref = 200u
+.options TEMP = 65.0
+
+* Include Models
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib TT
+
+* OP Parameters & Singals to save
+.save all  @M.X1.XM1.msky130_fd_pr__nfet_01v8[id] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vth]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vdsat]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM1.msky130_fd_pr__nfet_01v8[gds]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gds]
+
+*Simulations
+.control
+  *reset
+  tran 0.1n 0.5u
+  stop when time = 0.1u
+  alterparam vin = 1.8
+  resume
+  setplot tran1
+  plot v(out)
+  *write ~/caravel_fulgor_opamp/xschem/sim_results/opamp_closeloop_tran1.raw
+
+
+  *dc V3 0 1.8 0.01
+  *setplot dc1
+  *plot v(out1) v(out2) v(out3) v(in)
+
+  reset
+  op
+  setplot op1
+
+.endc
+
+.end
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  /home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym # of pins=4
+
+.subckt not  vdd in out vss
+*.ipin vdd
+*.ipin in
+*.ipin vss
+*.opin out
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 W=0.42 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 W=0.42 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+.ends
+
+.GLOBAL GND
+.end