Moved the simple_por ngspice simulations into directory ngspice/simple_por/.
Added new directory ngspice/digital_pll/ containing simulation testbenches for
the digital PLL and trimmable ring oscillator.  Added qflow directories for
both;  this was done only to get a valid xspice file for the controller and
a valid SPICE netlist for the ring oscillator.
32 files changed
tree: f9593aad1d4d1dd91a6552d0168bf9d4738ebb9b
  1. .travisCI/
  2. def/
  3. doc/
  4. gds/
  5. lef/
  6. macros/
  7. mag/
  8. ngspice/
  9. openlane/
  10. qflow/
  11. scripts/
  12. spi/
  13. verilog/
  14. .travis.yml
  16. Makefile
  18. info.yaml

CIIC Harness

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware that can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC can be found here

Mega Project Area

This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.