blob: e0b057bd5a6d6c952afcd31b65d445a67a298ed9 [file] [log] [blame]
v { version=2.9.8 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 480 -300 480 -270 { lab=GND}
N 570 -300 570 -270 { lab=vss}
N 570 -390 570 -360 { lab=vdd}
N 480 -390 480 -360 { lab=vss}
N 0 30 -0 60 { lab=9}
N 0 -60 -0 -30 { lab=10}
N -80 0 -40 -0 { lab=out_ring}
N 0 -80 0 -60 { lab=10}
N 50 -0 70 0 { lab=o1}
N 160 -0 180 -0 { lab=o2}
N 270 -0 290 0 { lab=o3}
N 380 -0 400 -0 { lab=o4}
N 490 -0 510 0 { lab=o5}
N 110 30 110 60 { lab=9}
N 220 30 220 60 { lab=9}
N 330 30 330 60 { lab=9}
N 440 30 440 60 { lab=9}
N 550 30 550 60 { lab=9}
N 110 -80 110 -30 { lab=10}
N 220 -80 220 -30 { lab=10}
N 330 -80 330 -30 { lab=10}
N 440 -80 440 -30 { lab=10}
N 550 -80 550 -30 { lab=10}
N 2640 0 2740 0 { lab=out_vco}
N -0 -80 550 -80 { lab=10}
N 550 -80 640 -80 { lab=10}
N 290 -200 290 -80 { lab=10}
N -160 -230 250 -230 { lab=5}
N -200 -200 -200 150 { lab=5}
N -160 180 250 180 { lab=in}
N -200 -310 -200 -260 { lab=vdd}
N -200 -310 290 -310 { lab=vdd}
N 290 -310 290 -260 { lab=vdd}
N 290 -230 360 -230 { lab=vdd}
N 360 -310 360 -230 { lab=vdd}
N 290 -310 360 -310 { lab=vdd}
N -270 -230 -200 -230 { lab=vdd}
N -270 -310 -270 -230 { lab=vdd}
N -270 -310 -200 -310 { lab=vdd}
N -200 210 -200 250 { lab=vss}
N -200 250 290 250 { lab=vss}
N 290 210 290 250 { lab=vss}
N 290 180 370 180 { lab=vss}
N 370 180 370 250 { lab=vss}
N 290 250 370 250 { lab=vss}
N -280 180 -200 180 { lab=vss}
N -280 180 -280 250 { lab=vss}
N -280 250 -200 250 { lab=vss}
N -200 -140 -120 -140 { lab=5}
N -120 -230 -120 -140 { lab=5}
N 2480 -30 2480 30 { lab=out_ring}
N 2480 0 2540 0 { lab=out_ring}
N 2410 60 2440 60 { lab=#net1}
N 2410 -60 2410 60 { lab=#net1}
N 2410 -60 2440 -60 { lab=#net1}
N 2480 -120 2480 -90 { lab=10}
N 2410 -120 2480 -120 { lab=10}
N 2410 -120 2410 -80 { lab=10}
N 640 -80 690 -80 { lab=10}
N 2480 90 2480 120 { lab=9}
N 2410 120 2480 120 { lab=9}
N 2410 80 2410 120 { lab=9}
N 290 80 690 80 { lab=9}
N 290 80 290 150 { lab=9}
N 330 60 330 80 { lab=9}
N 440 60 440 80 { lab=9}
N 550 60 550 80 { lab=9}
N -0 80 290 80 { lab=9}
N -0 60 0 80 { lab=9}
N 110 60 110 80 { lab=9}
N 220 60 220 80 { lab=9}
N 2640 -30 2640 30 { lab=out_vco}
N 2640 90 2640 120 { lab=vss}
N 2640 120 2730 120 { lab=vss}
N 2730 60 2730 120 { lab=vss}
N 2640 60 2730 60 { lab=vss}
N 2570 60 2600 60 { lab=out_ring}
N 2570 -60 2570 60 { lab=out_ring}
N 2570 -60 2600 -60 { lab=out_ring}
N 2540 0 2570 0 { lab=out_ring}
N 2640 -120 2640 -90 { lab=vdd}
N 2640 -120 2720 -120 { lab=vdd}
N 2720 -120 2720 -60 { lab=vdd}
N 2640 -60 2720 -60 { lab=vdd}
N 670 -300 670 -270 { lab=vss}
N 670 -390 670 -360 { lab=in}
N 2480 -60 2540 -60 { lab=10}
N 2540 -120 2540 -60 { lab=10}
N 2480 -120 2540 -120 { lab=10}
N 2480 60 2560 60 { lab=vss}
N 2560 60 2560 120 { lab=vss}
N 600 -0 620 -0 { lab=o6}
N 710 -0 730 -0 { lab=o7}
N 690 80 910 80 { lab=9}
N 690 -80 910 -80 { lab=10}
N 660 -80 660 -30 { lab=10}
N 770 -80 770 -30 { lab=10}
N 770 30 770 80 { lab=9}
N 660 30 660 80 { lab=9}
N 910 80 1180 80 { lab=9}
N 910 -80 1180 -80 { lab=10}
N -60 10 -40 10 { lab=vss}
N -60 10 -60 50 { lab=vss}
N -60 50 720 50 { lab=vss}
N 720 10 730 10 { lab=vss}
N 720 10 720 50 { lab=vss}
N 610 10 620 10 { lab=vss}
N 610 10 610 50 { lab=vss}
N 500 10 510 10 { lab=vss}
N 500 10 500 50 { lab=vss}
N 390 10 400 10 { lab=vss}
N 390 10 390 50 { lab=vss}
N 60 10 70 10 { lab=vss}
N 60 10 60 50 { lab=vss}
N 280 10 290 10 { lab=vss}
N 280 10 280 50 { lab=vss}
N 170 10 180 10 { lab=vss}
N 170 10 170 50 { lab=vss}
N 820 -0 840 -0 { lab=o8}
N 930 -0 950 -0 { lab=#net2}
N 1040 -0 1060 0 { lab=#net3}
N 1150 -0 1180 -0 { lab=#net4}
N 720 50 1160 50 { lab=vss}
N 1160 10 1160 50 { lab=vss}
N 1160 10 1180 10 { lab=vss}
N 1050 10 1060 10 { lab=vss}
N 1050 10 1050 50 { lab=vss}
N 940 10 950 10 { lab=vss}
N 940 10 940 50 { lab=vss}
N 830 10 840 10 { lab=vss}
N 830 10 830 50 { lab=vss}
N 880 30 880 80 { lab=9}
N 880 -80 880 -30 { lab=10}
N 990 -80 990 -30 { lab=10}
N 990 30 990 80 { lab=9}
N 1100 30 1100 80 { lab=9}
N 1100 -80 1100 -30 { lab=10}
N 1220 30 1220 80 { lab=9}
N 1180 80 1220 80 { lab=9}
N 1220 -80 1220 -30 { lab=10}
N 1180 -80 1220 -80 { lab=10}
N 1220 80 1820 80 { lab=9}
N 1220 -80 1820 -80 { lab=10}
N 1340 30 1340 80 { lab=9}
N 1340 -80 1340 -30 { lab=10}
N 1460 30 1460 80 { lab=9}
N 1460 -80 1460 -30 { lab=10}
N 1580 -80 1580 -30 { lab=10}
N 1580 30 1580 80 { lab=9}
N 1160 50 1640 50 { lab=vss}
N 1640 10 1640 50 { lab=vss}
N 1640 10 1660 10 { lab=vss}
N 1520 10 1540 10 { lab=vss}
N 1520 10 1520 50 { lab=vss}
N 1400 10 1420 10 { lab=vss}
N 1400 10 1400 50 { lab=vss}
N 1280 10 1300 10 { lab=vss}
N 1280 10 1280 50 { lab=vss}
N 1700 30 1700 80 { lab=9}
N 1700 -80 1700 -30 { lab=10}
N 1630 0 1660 0 { lab=#net5}
N 1510 0 1540 0 { lab=#net6}
N 1390 -0 1420 0 { lab=#net7}
N 1270 0 1300 -0 { lab=#net8}
N 1820 80 2030 80 { lab=9}
N 1820 -80 2030 -80 { lab=10}
N 1750 0 1780 -0 { lab=#net9}
N 1640 50 1760 50 { lab=vss}
N 1760 10 1760 50 { lab=vss}
N 1760 10 1780 10 { lab=vss}
N 1760 50 1880 50 { lab=vss}
N 1880 10 1880 50 { lab=vss}
N 1880 10 1910 10 { lab=vss}
N 1820 30 1820 80 { lab=9}
N 1950 30 1950 80 { lab=9}
N 1950 -80 1950 -30 { lab=10}
N 1820 -80 1820 -30 { lab=10}
N 1870 -0 1910 -0 { lab=#net10}
N 2010 10 2010 50 { lab=vss}
N 2010 10 2030 10 { lab=vss}
N 2000 0 2030 -0 { lab=#net11}
N 1880 50 2010 50 { lab=vss}
N 2030 80 2200 80 { lab=9}
N 2030 -80 2200 -80 { lab=10}
N 2070 -80 2070 -30 { lab=10}
N 2070 30 2070 80 { lab=9}
N 2280 80 2370 80 { lab=9}
N 770 210 770 240 { lab=vdd}
N 770 380 770 400 { lab=vss}
N 670 310 700 310 { lab=out_vco}
N 770 400 770 420 { lab=vss}
N 640 310 670 310 { lab=out_vco}
N 970 210 970 240 { lab=vdd}
N 970 380 970 400 { lab=vss}
N 870 310 900 310 { lab=outx2}
N 970 400 970 420 { lab=vss}
N 840 310 870 310 { lab=outx2}
N 1170 210 1170 240 { lab=vdd}
N 1170 380 1170 400 { lab=vss}
N 1070 310 1100 310 { lab=outx4}
N 1170 400 1170 420 { lab=vss}
N 1040 310 1070 310 { lab=outx4}
N 1370 210 1370 240 { lab=vdd}
N 1370 380 1370 400 { lab=vss}
N 1270 310 1300 310 { lab=outx8}
N 1370 400 1370 420 { lab=vss}
N 1240 310 1270 310 { lab=outx8}
N 1570 210 1570 240 { lab=vdd}
N 1570 380 1570 400 { lab=vss}
N 1470 310 1500 310 { lab=outx16}
N 1570 400 1570 420 { lab=vss}
N 1440 310 1470 310 { lab=outx16}
N 1640 310 1690 310 { lab=outx32}
N 1920 310 1920 350 { lab=out}
N 1920 410 1920 440 { lab=vss}
N 1760 310 1860 310 { lab=out}
N 1760 280 1760 340 { lab=out}
N 1760 400 1760 430 { lab=vss}
N 1760 430 1850 430 { lab=vss}
N 1850 370 1850 430 { lab=vss}
N 1760 370 1850 370 { lab=vss}
N 1690 370 1720 370 { lab=outx32}
N 1690 250 1690 370 { lab=outx32}
N 1690 250 1720 250 { lab=outx32}
N 1760 190 1760 220 { lab=vdd}
N 1760 190 1840 190 { lab=vdd}
N 1840 190 1840 250 { lab=vdd}
N 1760 250 1840 250 { lab=vdd}
N 1860 310 1920 310 { lab=out}
N 770 -300 770 -270 { lab=vss}
N 770 -390 770 -360 { lab=en}
N 2370 80 2410 80 { lab=9}
N 2200 80 2280 80 { lab=9}
N 2200 -80 2290 -80 { lab=10}
N 2290 -80 2410 -80 { lab=10}
N 2350 0 2410 -0 { lab=#net1}
N 2120 -0 2140 0 { lab=#net12}
N 2140 -100 2140 0 { lab=#net12}
N 2030 -100 2140 -100 { lab=#net12}
N 2030 -190 2030 -100 { lab=#net12}
N 2030 -190 2100 -190 { lab=#net12}
N 2350 -110 2350 0 { lab=#net1}
N 2350 -110 2400 -110 { lab=#net1}
N 2400 -210 2400 -110 { lab=#net1}
N 2080 -130 2100 -130 { lab=vss}
N 2080 -150 2100 -150 { lab=9}
N 2080 -170 2100 -170 { lab=en}
N 2080 -210 2100 -210 { lab=10
}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 0 0 0 0 {name=x1}
C {vsource.sym} 480 -330 0 0 {name=V1 value=DC\{Vss\}}
C {vsource.sym} 570 -330 0 0 {name=V2 value=DC\{Vdd\}}
C {gnd.sym} 480 -270 0 0 {name=l1 lab=GND}
C {lab_pin.sym} 480 -390 1 0 {name=l3 sig_type=std_logic lab=vss}
C {lab_pin.sym} 570 -270 3 0 {name=l2 sig_type=std_logic lab=vss}
C {lab_pin.sym} 570 -390 1 0 {name=l9 sig_type=std_logic lab=vdd
}
C {netlist_not_shown.sym} 1060 -380 0 0 {name=SIMULATION only_toplevel=false
value="
* Circuit Parameters
.param vdd = 1.8
.param vss = 0.0
.param vin = 1
.param iref = 200u
.options TEMP = 65.0
* Include Models
.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib TT
* OP Parameters & Singals to save
.save all
+ @M.X2.XM1.msky130_fd_pr__nfet_01v8[id] @M.X2.XM1.msky130_fd_pr__nfet_01v8[vth] @M.X2.XM1.msky130_fd_pr__nfet_01v8[vgs] @M.X2.XM1.msky130_fd_pr__nfet_01v8[vds] @M.X2.XM1.msky130_fd_pr__nfet_01v8[vdsat] @M.X2.XM1.msky130_fd_pr__nfet_01v8[gm] @M.X2.XM1.msky130_fd_pr__nfet_01v8[gds] @M.X2.XM1.msky130_fd_pr__nfet_01v8[cgs] @M.X2.XM1.msky130_fd_pr__nfet_01v8[cgd]
+ @M.X2.XM2.msky130_fd_pr__pfet_01v8[id] @M.X2.XM2.msky130_fd_pr__pfet_01v8[vth] @M.X2.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X2.XM2.msky130_fd_pr__pfet_01v8[vds] @M.X2.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X2.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X2.XM2.msky130_fd_pr__pfet_01v8[gds] @M.X2.XM1.msky130_fd_pr__nfet_01v8[cgs] @M.X2.XM1.msky130_fd_pr__nfet_01v8[cgd]
+ @M.XM6.msky130_fd_pr__nfet_01v8[id] @M.XM6.msky130_fd_pr__nfet_01v8[vth] @M.XM6.msky130_fd_pr__nfet_01v8[vgs] @M.XM6.msky130_fd_pr__nfet_01v8[vds] @M.XM6.msky130_fd_pr__nfet_01v8[vdsat] @M.XM6.msky130_fd_pr__nfet_01v8[gm] @M.XM6.msky130_fd_pr__nfet_01v8[gds] @M.XM6.msky130_fd_pr__nfet_01v8[cgs] @M.XM6.msky130_fd_pr__nfet_01v8[cgd]
+ @M.XM5.msky130_fd_pr__pfet_01v8[id] @M.XM5.msky130_fd_pr__pfet_01v8[vth] @M.XM5.msky130_fd_pr__pfet_01v8[vgs] @M.XM5.msky130_fd_pr__pfet_01v8[vds] @M.XM5.msky130_fd_pr__pfet_01v8[vdsat] @M.XM5.msky130_fd_pr__pfet_01v8[gm] @M.XM5.msky130_fd_pr__pfet_01v8[gds] @M.XM5.msky130_fd_pr__nfet_01v8[cgs] @M.XM5.msky130_fd_pr__nfet_01v8[cgd]
*Simulations
.control
tran 0.05n 1u
setplot tran1
plot v(out) v(outx32)+2 v(outx16)+4 v(outx8)+6 v(outx4)+8 v(outx2)+10 v(out_vco)+12 v(en)+14
linearize
set specwindow="blackman"
fft v(out_vco)
spec 10 1000000 1000 v(out_vco)
plot mag(v(out_vco))
reset
tran 0.05n 1u
setplot tran2
linearize
fft v(out)
spec 10 1000000 1000 v(out)
plot mag(v(out))
write ~/caravel_fulgor_opamp/xschem/ring_vco/ring_vco_tran1.raw
.endc
.end
"}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 110 0 0 0 {name=x2}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 220 0 0 0 {name=x3}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 330 0 0 0 {name=x4}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 440 0 0 0 {name=x5}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 550 0 0 0 {name=x6}
C {lab_pin.sym} -80 0 0 0 {name=l5 sig_type=std_logic lab=out_ring}
C {lab_wire.sym} 2690 -120 0 0 {name=l11 sig_type=std_logic lab=vdd}
C {lab_wire.sym} 2690 120 0 0 {name=l14 sig_type=std_logic lab=vss}
C {sky130_fd_pr/nfet_01v8.sym} 2460 60 0 0 {name=M1
L=0.15
W=1.2
ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
as="'W * 0.29'" ps="'2 * (W + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
nf=1 mult=1
model=nfet_01v8
spiceprefix=X
}
C {sky130_fd_pr/pfet_01v8.sym} 2460 -60 0 0 {name=M2
L=0.15
W=1.5
ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
as="'W * 0.29'" ps="'2 * (W + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
nf=1 mult=2
model=pfet_01v8
spiceprefix=X
}
C {sky130_fd_pr/nfet_01v8.sym} 2620 60 0 0 {name=M3
L=0.15
W=0.6
ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
as="'W * 0.29'" ps="'2 * (W + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
nf=1 mult=1
model=nfet_01v8
spiceprefix=X
}
C {sky130_fd_pr/pfet_01v8.sym} 2620 -60 0 0 {name=M4
L=0.15
W=1.5
ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
as="'W * 0.29'" ps="'2 * (W + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
nf=1 mult=1
model=pfet_01v8
spiceprefix=X
}
C {lab_wire.sym} 2540 0 0 0 {name=l4 sig_type=std_logic lab=out_ring}
C {lab_pin.sym} 2740 0 2 0 {name=l6 sig_type=std_logic lab=out_vco}
C {sky130_fd_pr/pfet_01v8.sym} 270 -230 0 0 {name=M5
L=0.15
W=1.5
ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
as="'W * 0.29'" ps="'2 * (W + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
nf=1 mult=1
model=pfet_01v8
spiceprefix=X
}
C {sky130_fd_pr/nfet_01v8.sym} 270 180 0 0 {name=M6
L=0.15
W=1.5
ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
as="'W * 0.29'" ps="'2 * (W + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
nf=1 mult=1
model=nfet_01v8
spiceprefix=X
}
C {sky130_fd_pr/pfet_01v8.sym} -180 -230 0 1 {name=M7
L=0.15
W=0.9
ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
as="'W * 0.29'" ps="'2 * (W + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
nf=1 mult=1
model=pfet_01v8
spiceprefix=X
}
C {sky130_fd_pr/nfet_01v8.sym} -180 180 0 1 {name=M8
L=0.15
W=0.9
ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
as="'W * 0.29'" ps="'2 * (W + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
nf=1 mult=1
model=nfet_01v8
spiceprefix=X
}
C {lab_wire.sym} 60 -230 0 0 {name=l7 sig_type=std_logic lab=5}
C {lab_wire.sym} 60 -310 0 0 {name=l8 sig_type=std_logic lab=vdd}
C {lab_wire.sym} 40 250 0 0 {name=l10 sig_type=std_logic lab=vss}
C {lab_wire.sym} 40 180 0 0 {name=l12 sig_type=std_logic lab=in}
C {lab_wire.sym} 290 -140 3 0 {name=l13 sig_type=std_logic lab=10}
C {lab_wire.sym} 290 100 3 0 {name=l15 sig_type=std_logic lab=9}
C {lab_wire.sym} 60 0 0 0 {name=l16 sig_type=std_logic lab=o1}
C {lab_wire.sym} 170 0 0 0 {name=l17 sig_type=std_logic lab=o2}
C {lab_wire.sym} 280 0 0 0 {name=l18 sig_type=std_logic lab=o3}
C {lab_wire.sym} 390 0 0 0 {name=l19 sig_type=std_logic lab=o4}
C {lab_wire.sym} 500 0 0 0 {name=l20 sig_type=std_logic lab=o5}
C {lab_wire.sym} 610 0 0 0 {name=l21 sig_type=std_logic lab=o6}
C {vsource.sym} 670 -330 0 0 {name=V3 value=DC\{Vin\}}
C {lab_pin.sym} 670 -270 3 0 {name=l22 sig_type=std_logic lab=vss}
C {lab_pin.sym} 670 -390 1 0 {name=l23 sig_type=std_logic lab=in}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 660 0 0 0 {name=x7}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 770 0 0 0 {name=x8}
C {lab_wire.sym} 720 0 0 0 {name=l24 sig_type=std_logic lab=o7}
C {lab_wire.sym} 830 0 0 0 {name=l25 sig_type=std_logic lab=o8}
C {lab_wire.sym} -30 50 0 0 {name=l26 sig_type=std_logic lab=vss}
C {lab_pin.sym} 2560 120 3 0 {name=l27 sig_type=std_logic lab=vss}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 880 0 0 0 {name=x9}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 990 0 0 0 {name=x10}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1100 0 0 0 {name=x11}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1220 0 0 0 {name=x12}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1340 0 0 0 {name=x13}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1460 0 0 0 {name=x14}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1580 0 0 0 {name=x15}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1700 0 0 0 {name=x16}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1820 0 0 0 {name=x17}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1950 0 0 0 {name=x18}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 2070 0 0 0 {name=x19}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 770 310 0 0 {name=x21}
C {lab_pin.sym} 770 210 1 0 {name=l28 sig_type=std_logic lab=vdd
}
C {lab_pin.sym} 770 420 3 0 {name=l29 sig_type=std_logic lab=vss}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 970 310 0 0 {name=x22}
C {lab_pin.sym} 970 210 1 0 {name=l30 sig_type=std_logic lab=vdd
}
C {lab_pin.sym} 970 420 3 0 {name=l31 sig_type=std_logic lab=vss}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 1170 310 0 0 {name=x23}
C {lab_pin.sym} 1170 210 1 0 {name=l32 sig_type=std_logic lab=vdd
}
C {lab_pin.sym} 1170 420 3 0 {name=l33 sig_type=std_logic lab=vss}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 1370 310 0 0 {name=x24}
C {lab_pin.sym} 1370 210 1 0 {name=l34 sig_type=std_logic lab=vdd
}
C {lab_pin.sym} 1370 420 3 0 {name=l35 sig_type=std_logic lab=vss}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 1570 310 0 0 {name=x25}
C {lab_pin.sym} 1570 210 1 0 {name=l36 sig_type=std_logic lab=vdd
}
C {lab_pin.sym} 1570 420 3 0 {name=l37 sig_type=std_logic lab=vss}
C {lab_pin.sym} 640 310 0 0 {name=l38 sig_type=std_logic lab=out_vco}
C {lab_pin.sym} 1920 310 2 0 {name=l39 sig_type=std_logic lab=out}
C {lab_wire.sym} 1090 310 0 0 {name=l41 sig_type=std_logic lab=outx4}
C {lab_wire.sym} 890 310 0 0 {name=l40 sig_type=std_logic lab=outx2}
C {lab_wire.sym} 1290 310 0 0 {name=l42 sig_type=std_logic lab=outx8}
C {lab_wire.sym} 1490 310 0 0 {name=l43 sig_type=std_logic lab=outx16}
C {capa.sym} 1920 380 0 0 {name=C1
m=1
value=2p
footprint=1206
device="ceramic capacitor"}
C {lab_pin.sym} 1920 440 3 0 {name=l44 sig_type=std_logic lab=vss}
C {lab_wire.sym} 1810 190 0 0 {name=l45 sig_type=std_logic lab=vdd}
C {lab_wire.sym} 1810 430 0 0 {name=l46 sig_type=std_logic lab=vss}
C {sky130_fd_pr/nfet_01v8.sym} 1740 370 0 0 {name=M9
L=0.15
W=1.2
ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
as="'W * 0.29'" ps="'2 * (W + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
nf=1 mult=2
model=nfet_01v8
spiceprefix=X
}
C {sky130_fd_pr/pfet_01v8.sym} 1740 250 0 0 {name=M10
L=0.15
W=1.5
ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
as="'W * 0.29'" ps="'2 * (W + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
nf=1 mult=4
model=pfet_01v8
spiceprefix=X
}
C {lab_wire.sym} 1680 310 0 0 {name=l47 sig_type=std_logic lab=outx32}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/nand.sym} 2250 -170 0 0 {name=x26}
C {vsource.sym} 770 -330 0 0 {name=V4 value="PULSE(0 \{Vdd\} 100ns 1ps 1ps 0.25us 0.5us)"}
C {lab_pin.sym} 770 -270 3 0 {name=l49 sig_type=std_logic lab=vss}
C {lab_pin.sym} 770 -390 1 0 {name=l50 sig_type=std_logic lab=en}
C {lab_pin.sym} 2080 -210 0 0 {name=l48 sig_type=std_logic lab=10}
C {lab_pin.sym} 2080 -170 0 0 {name=l51 sig_type=std_logic lab=en}
C {lab_pin.sym} 2080 -150 0 0 {name=l52 sig_type=std_logic lab=9}
C {lab_pin.sym} 2080 -130 0 0 {name=l53 sig_type=std_logic lab=vss}