Created Trans Gate
diff --git a/mag/VCO/sky130_fd_pr__nfet_01v8_UVCFM7.mag b/mag/VCO/sky130_fd_pr__nfet_01v8_UVCFM7.mag
new file mode 100644
index 0000000..edb8d2e
--- /dev/null
+++ b/mag/VCO/sky130_fd_pr__nfet_01v8_UVCFM7.mag
@@ -0,0 +1,85 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1608323403
+<< error_p >>
+rect -29 -52 29 -46
+rect -29 -86 -17 -52
+rect -29 -92 29 -86
+<< pwell >>
+rect -211 -224 211 224
+<< nmos >>
+rect -15 -14 15 76
+<< ndiff >>
+rect -73 64 -15 76
+rect -73 -2 -61 64
+rect -27 -2 -15 64
+rect -73 -14 -15 -2
+rect 15 64 73 76
+rect 15 -2 27 64
+rect 61 -2 73 64
+rect 15 -14 73 -2
+<< ndiffc >>
+rect -61 -2 -27 64
+rect 27 -2 61 64
+<< psubdiff >>
+rect -175 154 -79 188
+rect 79 154 175 188
+rect -175 92 -141 154
+rect 141 92 175 154
+rect -175 -154 -141 -92
+rect 141 -154 175 -92
+rect -175 -188 -79 -154
+rect 79 -188 175 -154
+<< psubdiffcont >>
+rect -79 154 79 188
+rect -175 -92 -141 92
+rect 141 -92 175 92
+rect -79 -188 79 -154
+<< poly >>
+rect -15 76 15 102
+rect -15 -36 15 -14
+rect -33 -52 33 -36
+rect -33 -86 -17 -52
+rect 17 -86 33 -52
+rect -33 -102 33 -86
+<< polycont >>
+rect -17 -86 17 -52
+<< locali >>
+rect -175 154 -79 188
+rect 79 154 175 188
+rect -175 92 -141 154
+rect 141 92 175 154
+rect -61 64 -27 80
+rect -61 -18 -27 -2
+rect 27 64 61 80
+rect 27 -18 61 -2
+rect -33 -86 -17 -52
+rect 17 -86 33 -52
+rect -175 -154 -141 -92
+rect 141 -154 175 -92
+rect -175 -188 -79 -154
+rect 79 -188 175 -154
+<< viali >>
+rect -61 -2 -27 64
+rect 27 -2 61 64
+rect -17 -86 17 -52
+<< metal1 >>
+rect -67 64 -21 76
+rect -67 -2 -61 64
+rect -27 -2 -21 64
+rect -67 -14 -21 -2
+rect 21 64 67 76
+rect 21 -2 27 64
+rect 61 -2 67 64
+rect 21 -14 67 -2
+rect -29 -52 29 -46
+rect -29 -86 -17 -52
+rect 17 -86 29 -52
+rect -29 -92 29 -86
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -171 158 171
+string parameters w 0.45 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/VCO/sky130_fd_pr__pfet_01v8_H4M7SM.mag b/mag/VCO/sky130_fd_pr__pfet_01v8_H4M7SM.mag
new file mode 100644
index 0000000..0145651
--- /dev/null
+++ b/mag/VCO/sky130_fd_pr__pfet_01v8_H4M7SM.mag
@@ -0,0 +1,85 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1608323403
+<< error_p >>
+rect -29 135 29 141
+rect -29 101 -17 135
+rect -29 95 29 101
+<< nwell >>
+rect -211 -274 211 274
+<< pmos >>
+rect -15 -126 15 54
+<< pdiff >>
+rect -73 42 -15 54
+rect -73 -114 -61 42
+rect -27 -114 -15 42
+rect -73 -126 -15 -114
+rect 15 42 73 54
+rect 15 -114 27 42
+rect 61 -114 73 42
+rect 15 -126 73 -114
+<< pdiffc >>
+rect -61 -114 -27 42
+rect 27 -114 61 42
+<< nsubdiff >>
+rect -175 204 -79 238
+rect 79 204 175 238
+rect -175 141 -141 204
+rect 141 141 175 204
+rect -175 -204 -141 -141
+rect 141 -204 175 -141
+rect -175 -238 -79 -204
+rect 79 -238 175 -204
+<< nsubdiffcont >>
+rect -79 204 79 238
+rect -175 -141 -141 141
+rect 141 -141 175 141
+rect -79 -238 79 -204
+<< poly >>
+rect -33 135 33 151
+rect -33 101 -17 135
+rect 17 101 33 135
+rect -33 85 33 101
+rect -15 54 15 85
+rect -15 -152 15 -126
+<< polycont >>
+rect -17 101 17 135
+<< locali >>
+rect -175 204 -79 238
+rect 79 204 175 238
+rect -175 141 -141 204
+rect 141 141 175 204
+rect -33 101 -17 135
+rect 17 101 33 135
+rect -61 42 -27 58
+rect -61 -130 -27 -114
+rect 27 42 61 58
+rect 27 -130 61 -114
+rect -175 -204 -141 -141
+rect 141 -204 175 -141
+rect -175 -238 -79 -204
+rect 79 -238 175 -204
+<< viali >>
+rect -17 101 17 135
+rect -61 -114 -27 42
+rect 27 -114 61 42
+<< metal1 >>
+rect -29 135 29 141
+rect -29 101 -17 135
+rect 17 101 29 135
+rect -29 95 29 101
+rect -67 42 -21 54
+rect -67 -114 -61 42
+rect -27 -114 -21 42
+rect -67 -126 -21 -114
+rect 21 42 67 54
+rect 21 -114 27 42
+rect 61 -114 67 42
+rect 21 -126 67 -114
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -158 -221 158 221
+string parameters w 0.9 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl 0 viagr 0 viagt 0 viagb 0 viagate 100 viadrn 100 viasrc 100
+string library sky130
+<< end >>
diff --git a/mag/VCO/trans_gate.mag b/mag/VCO/trans_gate.mag
new file mode 100644
index 0000000..5713974
--- /dev/null
+++ b/mag/VCO/trans_gate.mag
@@ -0,0 +1,54 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1608323403
+<< nwell >>
+rect -155 -46 436 733
+<< pwell >>
+rect -119 -447 408 -79
+rect -119 -701 409 -447
+<< psubdiff >>
+rect -61 -529 344 -467
+rect -61 -622 -32 -529
+rect 317 -622 344 -529
+rect -61 -628 344 -622
+<< nsubdiff >>
+rect -92 446 390 681
+<< psubdiffcont >>
+rect -32 -622 317 -529
+<< viali >>
+rect -94 445 388 679
+rect -61 -529 344 -467
+rect -61 -622 -32 -529
+rect -32 -622 317 -529
+rect 317 -622 344 -529
+rect -61 -628 344 -622
+<< metal1 >>
+rect -106 679 400 685
+rect -106 445 -94 679
+rect 388 445 400 679
+rect -106 439 400 445
+rect -155 320 178 379
+rect 71 -317 122 287
+rect 166 -317 217 287
+rect -157 -404 176 -345
+rect -73 -467 356 -461
+rect -73 -628 -61 -467
+rect 344 -628 356 -467
+rect -73 -634 356 -628
+use sky130_fd_pr__nfet_01v8_UVCFM7  sky130_fd_pr__nfet_01v8_UVCFM7_0
+timestamp 1608323403
+transform 1 0 144 0 1 -303
+box -211 -224 211 224
+use sky130_fd_pr__pfet_01v8_H4M7SM  sky130_fd_pr__pfet_01v8_H4M7SM_0
+timestamp 1608323403
+transform 1 0 146 0 1 233
+box -211 -274 211 274
+<< labels >>
+rlabel pwell -61 -628 344 -467 1 vss
+rlabel metal1 -157 -404 176 -345 1 clk_n
+rlabel metal1 71 -317 122 287 1 in
+rlabel metal1 166 -317 217 287 1 out
+rlabel metal1 -155 320 178 379 1 clk_p
+rlabel viali -94 445 388 679 1 vdd
+<< end >>
diff --git a/xschem/ring_vco/nand.sch b/xschem/ring_vco/nand.sch
index b4a22fa..31fd0c1 100644
--- a/xschem/ring_vco/nand.sch
+++ b/xschem/ring_vco/nand.sch
@@ -24,10 +24,11 @@
 N 280 -40 280 0 { lab=OUT}
 N 280 0 300 -0 { lab=OUT}
 N 440 -40 440 -0 { lab=OUT}
-N 360 60 440 60 { lab=vss}
-N 440 60 440 200 { lab=vss}
-N 360 200 440 200 { lab=vss}
-N 360 150 440 150 { lab=vss}
+N 360 60 440 60 { lab=vbulk}
+N 440 60 440 200 { lab=vbulk}
+N 360 150 440 150 { lab=vbulk}
+N 280 230 440 230 { lab=vbulk}
+N 440 200 440 230 { lab=vbulk}
 C {sky130_fd_pr/nfet_01v8.sym} 340 150 0 0 {name=M1
 L=0.15
 W=0.45
@@ -52,7 +53,7 @@
 }
 C {sky130_fd_pr/pfet_01v8.sym} 260 -70 0 0 {name=M5
 L=0.15
-W=0.45
+W=0.9
 ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
 as="'W * 0.29'" ps="'2 * (W + 0.29)'"
 nrd="'0.29 / W'" nrs="'0.29 / W'"
@@ -63,7 +64,7 @@
 }
 C {sky130_fd_pr/pfet_01v8.sym} 460 -70 0 1 {name=M6
 L=0.15
-W=0.45
+W=0.9
 ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
 as="'W * 0.29'" ps="'2 * (W + 0.29)'"
 nrd="'0.29 / W'" nrs="'0.29 / W'"
@@ -79,3 +80,4 @@
 C {ipin.sym} 280 200 0 0 {name=p6 lab=vss}
 C {lab_pin.sym} 280 60 0 0 {name=l1 sig_type=std_logic lab=A}
 C {lab_pin.sym} 520 -70 2 0 {name=l2 sig_type=std_logic lab=B}
+C {ipin.sym} 280 230 0 0 {name=p4 lab=vbulk}
diff --git a/xschem/ring_vco/nand.sym b/xschem/ring_vco/nand.sym
index 06a655f..b62cefb 100644
--- a/xschem/ring_vco/nand.sym
+++ b/xschem/ring_vco/nand.sym
@@ -4,29 +4,28 @@
 format="@name @pinlist @symname"
 template="name=x1"
 }
-V {}
-S {}
-E {}
-L 4 -10 -60 -10 -40 {}
-L 4 -60 -20 -40 -20 {}
-L 4 50 0 70 0 {}
-L 4 -60 20 -40 20 {}
-L 4 -10 40 -10 60 {}
-L 4 -30 -40 0 -40 {}
-L 4 -40 -40 -40 40 {}
-L 4 -40 40 0 40 {}
-L 4 -40 -40 -30 -40 {}
-B 5 -12.5 -62.5 -7.5 -57.5 {name=vdd dir=in name=p2 }
-B 5 -62.5 -22.5 -57.5 -17.5 {name=A dir=in name=p3 }
-B 5 67.5 -2.5 72.5 2.5 {name=OUT dir=out name=p1 }
-B 5 -62.5 17.5 -57.5 22.5 {name=B dir=in name=p5 }
-B 5 -12.5 57.5 -7.5 62.5 {name=vss dir=in name=p6 }
-A 4 -5 -0 40.31128874149275 277.1250163489018 165.7499673021964 {}
-A 4 43 -0.5 7.017834423809099 355.9143832200251 360 {}
+
 T {@symname} -36 -6 0 0 0.3 0.3 {}
-T {@name} -25 -22 0 0 0.2 0.2 {}
-T {vdd} -16 -55 1 0 0.2 0.2 {}
-T {A} -55 -34 0 0 0.2 0.2 {}
-T {OUT} 75 -14 0 1 0.2 0.2 {}
-T {B} -55 6 0 0 0.2 0.2 {}
-T {vss} -24 65 3 0 0.2 0.2 {}
+T {@name} 135 -62 0 0 0.2 0.2 {}
+L 4 -130 -50 130 -50 {}
+L 4 -130 50 130 50 {}
+L 4 -130 -50 -130 50 {}
+L 4 130 -50 130 50 {}
+B 5 -152.5 -42.5 -147.5 -37.5 {name=vdd dir=in name=p2 }
+L 4 -150 -40 -130 -40 {}
+T {vdd} -125 -44 0 0 0.2 0.2 {}
+B 5 -152.5 -22.5 -147.5 -17.5 {name=A dir=in name=p3 }
+L 4 -150 -20 -130 -20 {}
+T {A} -125 -24 0 0 0.2 0.2 {}
+B 5 147.5 -42.5 152.5 -37.5 {name=OUT dir=out name=p1 }
+L 4 130 -40 150 -40 {}
+T {OUT} 125 -44 0 1 0.2 0.2 {}
+B 5 -152.5 -2.5 -147.5 2.5 {name=B dir=in name=p5 }
+L 4 -150 0 -130 0 {}
+T {B} -125 -4 0 0 0.2 0.2 {}
+B 5 -152.5 17.5 -147.5 22.5 {name=vss dir=in name=p6 }
+L 4 -150 20 -130 20 {}
+T {vss} -125 16 0 0 0.2 0.2 {}
+B 5 -152.5 37.5 -147.5 42.5 {name=vbulk dir=in name=p4 }
+L 4 -150 40 -130 40 {}
+T {vbulk} -125 36 0 0 0.2 0.2 {}
diff --git a/xschem/ring_vco/ring_vco.sch b/xschem/ring_vco/ring_vco.sch
index ddaa918..e0b057b 100644
--- a/xschem/ring_vco/ring_vco.sch
+++ b/xschem/ring_vco/ring_vco.sch
@@ -27,7 +27,7 @@
 N 330 -80 330 -30 { lab=10}
 N 440 -80 440 -30 { lab=10}
 N 550 -80 550 -30 { lab=10}
-N 2520 0 2620 0 { lab=out_vco}
+N 2640 0 2740 0 { lab=out_vco}
 N -0 -80 550 -80 { lab=10}
 N 550 -80 640 -80 { lab=10}
 N 290 -200 290 -80 { lab=10}
@@ -54,18 +54,18 @@
 N -280 250 -200 250 { lab=vss}
 N -200 -140 -120 -140 { lab=5}
 N -120 -230 -120 -140 { lab=5}
-N 2360 -30 2360 30 { lab=out_ring}
-N 2360 0 2420 0 { lab=out_ring}
-N 2290 60 2320 60 { lab=#net1}
-N 2290 -60 2290 60 { lab=#net1}
-N 2290 -60 2320 -60 { lab=#net1}
-N 2360 -120 2360 -90 { lab=10}
-N 2290 -120 2360 -120 { lab=10}
-N 2290 -120 2290 -80 { lab=10}
+N 2480 -30 2480 30 { lab=out_ring}
+N 2480 0 2540 0 { lab=out_ring}
+N 2410 60 2440 60 { lab=#net1}
+N 2410 -60 2410 60 { lab=#net1}
+N 2410 -60 2440 -60 { lab=#net1}
+N 2480 -120 2480 -90 { lab=10}
+N 2410 -120 2480 -120 { lab=10}
+N 2410 -120 2410 -80 { lab=10}
 N 640 -80 690 -80 { lab=10}
-N 2360 90 2360 120 { lab=9}
-N 2290 120 2360 120 { lab=9}
-N 2290 80 2290 120 { lab=9}
+N 2480 90 2480 120 { lab=9}
+N 2410 120 2480 120 { lab=9}
+N 2410 80 2410 120 { lab=9}
 N 290 80 690 80 { lab=9}
 N 290 80 290 150 { lab=9}
 N 330 60 330 80 { lab=9}
@@ -75,26 +75,26 @@
 N -0 60 0 80 { lab=9}
 N 110 60 110 80 { lab=9}
 N 220 60 220 80 { lab=9}
-N 2520 -30 2520 30 { lab=out_vco}
-N 2520 90 2520 120 { lab=vss}
-N 2520 120 2610 120 { lab=vss}
-N 2610 60 2610 120 { lab=vss}
-N 2520 60 2610 60 { lab=vss}
-N 2450 60 2480 60 { lab=out_ring}
-N 2450 -60 2450 60 { lab=out_ring}
-N 2450 -60 2480 -60 { lab=out_ring}
-N 2420 0 2450 0 { lab=out_ring}
-N 2520 -120 2520 -90 { lab=vdd}
-N 2520 -120 2600 -120 { lab=vdd}
-N 2600 -120 2600 -60 { lab=vdd}
-N 2520 -60 2600 -60 { lab=vdd}
+N 2640 -30 2640 30 { lab=out_vco}
+N 2640 90 2640 120 { lab=vss}
+N 2640 120 2730 120 { lab=vss}
+N 2730 60 2730 120 { lab=vss}
+N 2640 60 2730 60 { lab=vss}
+N 2570 60 2600 60 { lab=out_ring}
+N 2570 -60 2570 60 { lab=out_ring}
+N 2570 -60 2600 -60 { lab=out_ring}
+N 2540 0 2570 0 { lab=out_ring}
+N 2640 -120 2640 -90 { lab=vdd}
+N 2640 -120 2720 -120 { lab=vdd}
+N 2720 -120 2720 -60 { lab=vdd}
+N 2640 -60 2720 -60 { lab=vdd}
 N 670 -300 670 -270 { lab=vss}
 N 670 -390 670 -360 { lab=in}
-N 2360 -60 2420 -60 { lab=10}
-N 2420 -120 2420 -60 { lab=10}
-N 2360 -120 2420 -120 { lab=10}
-N 2360 60 2440 60 { lab=vss}
-N 2440 60 2440 120 { lab=vss}
+N 2480 -60 2540 -60 { lab=10}
+N 2540 -120 2540 -60 { lab=10}
+N 2480 -120 2540 -120 { lab=10}
+N 2480 60 2560 60 { lab=vss}
+N 2560 60 2560 120 { lab=vss}
 N 600 -0 620 -0 { lab=o6}
 N 710 -0 730 -0 { lab=o7}
 N 690 80 910 80 { lab=9}
@@ -179,27 +179,18 @@
 N 1880 10 1910 10 { lab=vss}
 N 1820 30 1820 80 { lab=9}
 N 1950 30 1950 80 { lab=9}
-N 2260 0 2290 0 { lab=#net1}
 N 1950 -80 1950 -30 { lab=10}
 N 1820 -80 1820 -30 { lab=10}
 N 1870 -0 1910 -0 { lab=#net10}
 N 2010 10 2010 50 { lab=vss}
 N 2010 10 2030 10 { lab=vss}
-N 2010 50 2130 50 { lab=vss}
-N 2130 10 2130 50 { lab=vss}
-N 2130 10 2160 10 { lab=vss}
-N 2120 0 2160 0 { lab=#net11}
-N 2000 0 2030 -0 { lab=#net12}
+N 2000 0 2030 -0 { lab=#net11}
 N 1880 50 2010 50 { lab=vss}
 N 2030 80 2200 80 { lab=9}
-N 2200 30 2200 80 { lab=9}
-N 2200 -80 2200 -30 { lab=10}
 N 2030 -80 2200 -80 { lab=10}
 N 2070 -80 2070 -30 { lab=10}
 N 2070 30 2070 80 { lab=9}
-N 2250 0 2260 -0 { lab=#net1}
-N 2200 80 2290 80 { lab=9}
-N 2200 -80 2290 -80 { lab=10}
+N 2280 80 2370 80 { lab=9}
 N 770 210 770 240 { lab=vdd}
 N 770 380 770 400 { lab=vss}
 N 670 310 700 310 { lab=out_vco}
@@ -225,9 +216,43 @@
 N 1470 310 1500 310 { lab=outx16}
 N 1570 400 1570 420 { lab=vss}
 N 1440 310 1470 310 { lab=outx16}
-N 1640 310 1690 310 { lab=out}
-N 1690 310 1690 350 { lab=out}
-N 1690 410 1690 440 { lab=vss}
+N 1640 310 1690 310 { lab=outx32}
+N 1920 310 1920 350 { lab=out}
+N 1920 410 1920 440 { lab=vss}
+N 1760 310 1860 310 { lab=out}
+N 1760 280 1760 340 { lab=out}
+N 1760 400 1760 430 { lab=vss}
+N 1760 430 1850 430 { lab=vss}
+N 1850 370 1850 430 { lab=vss}
+N 1760 370 1850 370 { lab=vss}
+N 1690 370 1720 370 { lab=outx32}
+N 1690 250 1690 370 { lab=outx32}
+N 1690 250 1720 250 { lab=outx32}
+N 1760 190 1760 220 { lab=vdd}
+N 1760 190 1840 190 { lab=vdd}
+N 1840 190 1840 250 { lab=vdd}
+N 1760 250 1840 250 { lab=vdd}
+N 1860 310 1920 310 { lab=out}
+N 770 -300 770 -270 { lab=vss}
+N 770 -390 770 -360 { lab=en}
+N 2370 80 2410 80 { lab=9}
+N 2200 80 2280 80 { lab=9}
+N 2200 -80 2290 -80 { lab=10}
+N 2290 -80 2410 -80 { lab=10}
+N 2350 0 2410 -0 { lab=#net1}
+N 2120 -0 2140 0 { lab=#net12}
+N 2140 -100 2140 0 { lab=#net12}
+N 2030 -100 2140 -100 { lab=#net12}
+N 2030 -190 2030 -100 { lab=#net12}
+N 2030 -190 2100 -190 { lab=#net12}
+N 2350 -110 2350 0 { lab=#net1}
+N 2350 -110 2400 -110 { lab=#net1}
+N 2400 -210 2400 -110 { lab=#net1}
+N 2080 -130 2100 -130 { lab=vss}
+N 2080 -150 2100 -150 { lab=9}
+N 2080 -170 2100 -170 { lab=en}
+N 2080 -210 2100 -210 { lab=10
+}
 C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 0 0 0 0 {name=x1}
 C {vsource.sym} 480 -330 0 0 {name=V1 value=DC\{Vss\}}
 C {vsource.sym} 570 -330 0 0 {name=V2 value=DC\{Vdd\}}
@@ -236,7 +261,7 @@
 C {lab_pin.sym} 570 -270 3 0 {name=l2 sig_type=std_logic lab=vss}
 C {lab_pin.sym} 570 -390 1 0 {name=l9 sig_type=std_logic lab=vdd
 }
-C {netlist_not_shown.sym} 790 -380 0 0 {name=SIMULATION only_toplevel=false 
+C {netlist_not_shown.sym} 1060 -380 0 0 {name=SIMULATION only_toplevel=false 
 
 value="
 
@@ -249,7 +274,7 @@
 .options TEMP = 65.0
 
 * Include Models
-.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib SS
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib TT
 
 * OP Parameters & Singals to save
 .save all
@@ -264,7 +289,8 @@
 .control
   tran 0.05n 1u
   setplot tran1
-  plot v(out) v(outx16)+2 v(outx8)+4 v(outx4)+6 v(outx2)+8 v(out_vco)+10
+  plot v(out) v(outx32)+2 v(outx16)+4 v(outx8)+6 v(outx4)+8 v(outx2)+10 v(out_vco)+12 v(en)+14
+  
   linearize
   set specwindow="blackman"
   fft v(out_vco)
@@ -278,7 +304,7 @@
   fft v(out)
   spec 10 1000000 1000 v(out)
   plot mag(v(out))
-  *write ~/caravel_fulgor_opamp/xschem/sim_results/opamp_closeloop_tran1.raw
+  write ~/caravel_fulgor_opamp/xschem/ring_vco/ring_vco_tran1.raw
   
   
 .endc
@@ -291,9 +317,9 @@
 C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 440 0 0 0 {name=x5}
 C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 550 0 0 0 {name=x6}
 C {lab_pin.sym} -80 0 0 0 {name=l5 sig_type=std_logic lab=out_ring}
-C {lab_wire.sym} 2570 -120 0 0 {name=l11 sig_type=std_logic lab=vdd}
-C {lab_wire.sym} 2570 120 0 0 {name=l14 sig_type=std_logic lab=vss}
-C {sky130_fd_pr/nfet_01v8.sym} 2340 60 0 0 {name=M1
+C {lab_wire.sym} 2690 -120 0 0 {name=l11 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 2690 120 0 0 {name=l14 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/nfet_01v8.sym} 2460 60 0 0 {name=M1
 L=0.15
 W=1.2
 ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
@@ -304,7 +330,7 @@
 model=nfet_01v8
 spiceprefix=X
 }
-C {sky130_fd_pr/pfet_01v8.sym} 2340 -60 0 0 {name=M2
+C {sky130_fd_pr/pfet_01v8.sym} 2460 -60 0 0 {name=M2
 L=0.15
 W=1.5
 ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
@@ -315,7 +341,7 @@
 model=pfet_01v8
 spiceprefix=X
 }
-C {sky130_fd_pr/nfet_01v8.sym} 2500 60 0 0 {name=M3
+C {sky130_fd_pr/nfet_01v8.sym} 2620 60 0 0 {name=M3
 L=0.15
 W=0.6
 ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
@@ -326,7 +352,7 @@
 model=nfet_01v8
 spiceprefix=X
 }
-C {sky130_fd_pr/pfet_01v8.sym} 2500 -60 0 0 {name=M4
+C {sky130_fd_pr/pfet_01v8.sym} 2620 -60 0 0 {name=M4
 L=0.15
 W=1.5
 ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
@@ -337,8 +363,8 @@
 model=pfet_01v8
 spiceprefix=X
 }
-C {lab_wire.sym} 2420 0 0 0 {name=l4 sig_type=std_logic lab=out_ring}
-C {lab_pin.sym} 2620 0 2 0 {name=l6 sig_type=std_logic lab=out_vco}
+C {lab_wire.sym} 2540 0 0 0 {name=l4 sig_type=std_logic lab=out_ring}
+C {lab_pin.sym} 2740 0 2 0 {name=l6 sig_type=std_logic lab=out_vco}
 C {sky130_fd_pr/pfet_01v8.sym} 270 -230 0 0 {name=M5
 L=0.15
 W=1.5
@@ -403,7 +429,7 @@
 C {lab_wire.sym} 720 0 0 0 {name=l24 sig_type=std_logic lab=o7}
 C {lab_wire.sym} 830 0 0 0 {name=l25 sig_type=std_logic lab=o8}
 C {lab_wire.sym} -30 50 0 0 {name=l26 sig_type=std_logic lab=vss}
-C {lab_pin.sym} 2440 120 3 0 {name=l27 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 2560 120 3 0 {name=l27 sig_type=std_logic lab=vss}
 C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 880 0 0 0 {name=x9}
 C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 990 0 0 0 {name=x10}
 C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1100 0 0 0 {name=x11}
@@ -415,7 +441,6 @@
 C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1820 0 0 0 {name=x17}
 C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 1950 0 0 0 {name=x18}
 C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 2070 0 0 0 {name=x19}
-C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym} 2200 0 0 0 {name=x20}
 C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym} 770 310 0 0 {name=x21}
 C {lab_pin.sym} 770 210 1 0 {name=l28 sig_type=std_logic lab=vdd
 }
@@ -437,14 +462,47 @@
 }
 C {lab_pin.sym} 1570 420 3 0 {name=l37 sig_type=std_logic lab=vss}
 C {lab_pin.sym} 640 310 0 0 {name=l38 sig_type=std_logic lab=out_vco}
-C {lab_pin.sym} 1690 310 2 0 {name=l39 sig_type=std_logic lab=out}
+C {lab_pin.sym} 1920 310 2 0 {name=l39 sig_type=std_logic lab=out}
 C {lab_wire.sym} 1090 310 0 0 {name=l41 sig_type=std_logic lab=outx4}
 C {lab_wire.sym} 890 310 0 0 {name=l40 sig_type=std_logic lab=outx2}
 C {lab_wire.sym} 1290 310 0 0 {name=l42 sig_type=std_logic lab=outx8}
 C {lab_wire.sym} 1490 310 0 0 {name=l43 sig_type=std_logic lab=outx16}
-C {capa.sym} 1690 380 0 0 {name=C1
+C {capa.sym} 1920 380 0 0 {name=C1
 m=1
-value=10f
+value=2p
 footprint=1206
 device="ceramic capacitor"}
-C {lab_pin.sym} 1690 440 3 0 {name=l44 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1920 440 3 0 {name=l44 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 1810 190 0 0 {name=l45 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 1810 430 0 0 {name=l46 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/nfet_01v8.sym} 1740 370 0 0 {name=M9
+L=0.15
+W=1.2
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=2
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1740 250 0 0 {name=M10
+L=0.15
+W=1.5
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=4
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 1680 310 0 0 {name=l47 sig_type=std_logic lab=outx32}
+C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/nand.sym} 2250 -170 0 0 {name=x26}
+C {vsource.sym} 770 -330 0 0 {name=V4 value="PULSE(0 \{Vdd\} 100ns 1ps 1ps 0.25us 0.5us)"}
+C {lab_pin.sym} 770 -270 3 0 {name=l49 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 770 -390 1 0 {name=l50 sig_type=std_logic lab=en}
+C {lab_pin.sym} 2080 -210 0 0 {name=l48 sig_type=std_logic lab=10}
+C {lab_pin.sym} 2080 -170 0 0 {name=l51 sig_type=std_logic lab=en}
+C {lab_pin.sym} 2080 -150 0 0 {name=l52 sig_type=std_logic lab=9}
+C {lab_pin.sym} 2080 -130 0 0 {name=l53 sig_type=std_logic lab=vss}
diff --git a/xschem/ring_vco/ring_vco.spice b/xschem/ring_vco/ring_vco.spice
index c40e019..36604d1 100644
--- a/xschem/ring_vco/ring_vco.spice
+++ b/xschem/ring_vco/ring_vco.spice
@@ -1,29 +1,54 @@
 **.subckt ring_vco
-x1 10 out_ring o1 9 not
+x1 10 out_ring o1 9 vss not
 V1 vss GND DC{Vss} 
 V2 vdd vss DC{Vdd} 
-x2 10 o1 o2 9 not
-x3 10 o2 o3 9 not
-x4 10 o3 o4 9 not
-x5 10 o4 o5 9 not
-x6 10 o5 o6 9 not
-XM1 out_ring o6 9 9 sky130_fd_pr__nfet_01v8 W=1.2 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
+x2 10 o1 o2 9 vss not
+x3 10 o2 o3 9 vss not
+x4 10 o3 o4 9 vss not
+x5 10 o4 o5 9 vss not
+x6 10 o5 o6 9 vss not
+XM1 out_ring net1 9 vss sky130_fd_pr__nfet_01v8 W=1.2 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
 + ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
-XM2 out_ring o6 10 10 sky130_fd_pr__pfet_01v8 W=1.2 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
+XM2 out_ring net1 10 10 sky130_fd_pr__pfet_01v8 W=1.5 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
 + ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=2 m=2 
-XM3 out out_ring vss vss sky130_fd_pr__nfet_01v8 W=0.6 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
+XM3 out_vco out_ring vss vss sky130_fd_pr__nfet_01v8 W=0.6 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
 + ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
-XM4 out out_ring vdd vdd sky130_fd_pr__pfet_01v8 W=1.05 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
+XM4 out_vco out_ring vdd vdd sky130_fd_pr__pfet_01v8 W=1.5 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
 + ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
-XM5 10 5 vdd vdd sky130_fd_pr__pfet_01v8 W=1.2 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
-+ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=2 m=2 
-XM6 9 in vss vss sky130_fd_pr__nfet_01v8 W=1.2 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
+XM5 10 5 vdd vdd sky130_fd_pr__pfet_01v8 W=1.5 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
 + ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
-XM7 5 5 vdd vdd sky130_fd_pr__pfet_01v8 W=1.2 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
-+ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=2 m=2 
-XM8 5 in vss vss sky130_fd_pr__nfet_01v8 W=1.2 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
+XM6 9 in vss vss sky130_fd_pr__nfet_01v8 W=1.5 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM7 5 5 vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM8 5 in vss vss sky130_fd_pr__nfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
 + ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
 V3 in vss DC{Vin} 
+x7 10 o6 o7 9 vss not
+x8 10 o7 o8 9 vss not
+x9 10 o8 net2 9 vss not
+x10 10 net2 net3 9 vss not
+x11 10 net3 net4 9 vss not
+x12 10 net4 net8 9 vss not
+x13 10 net8 net7 9 vss not
+x14 10 net7 net6 9 vss not
+x15 10 net6 net5 9 vss not
+x16 10 net5 net9 9 vss not
+x17 10 net9 net10 9 vss not
+x18 10 net10 net11 9 vss not
+x19 10 net11 net12 9 vss not
+x21 out_vco vss outx2 vdd FD_v2
+x22 outx2 vss outx4 vdd FD_v2
+x23 outx4 vss outx8 vdd FD_v2
+x24 outx8 vss outx16 vdd FD_v2
+x25 outx16 vss outx32 vdd FD_v2
+C1 out vss 2p m=1
+XM9 out outx32 vss vss sky130_fd_pr__nfet_01v8 W=1.2 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=2 m=2 
+XM10 out outx32 vdd vdd sky130_fd_pr__pfet_01v8 W=1.5 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=4 m=4 
+x26 10 net12 net1 en 9 vss nand
+V4 en vss PULSE(0 {Vdd} 100ns 1ps 1ps 0.25us 0.5us) 
 **** begin user architecture code
 
 
@@ -32,39 +57,51 @@
 * Circuit Parameters
 .param vdd  = 1.8
 .param vss  = 0.0
-.param vin  = 0.3
+.param vin  = 1
 .param iref = 200u
 .options TEMP = 65.0
 
 * Include Models
-.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib TT
+.lib ~/skywater_pdk/skywater-pdk/libraries/sky130_fd_pr/latest/models/corners/sky130.lib FF
 
 * OP Parameters & Singals to save
-.save all  @M.X1.XM1.msky130_fd_pr__nfet_01v8[id] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vth]
-+ @M.X1.XM1.msky130_fd_pr__nfet_01v8[vgs] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vds] @M.X1.XM1.msky130_fd_pr__nfet_01v8[vdsat]
-+ @M.X1.XM1.msky130_fd_pr__nfet_01v8[gm] @M.X1.XM1.msky130_fd_pr__nfet_01v8[gds]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[id]
-+ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vth] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds]
-+ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X1.XM2.msky130_fd_pr__pfet_01v8[gds]
+.save all  @M.X2.XM1.msky130_fd_pr__nfet_01v8[id] @M.X2.XM1.msky130_fd_pr__nfet_01v8[vth]
++ @M.X2.XM1.msky130_fd_pr__nfet_01v8[vgs] @M.X2.XM1.msky130_fd_pr__nfet_01v8[vds] @M.X2.XM1.msky130_fd_pr__nfet_01v8[vdsat]
++ @M.X2.XM1.msky130_fd_pr__nfet_01v8[gm] @M.X2.XM1.msky130_fd_pr__nfet_01v8[gds] @M.X2.XM1.msky130_fd_pr__nfet_01v8[cgs]
++ @M.X2.XM1.msky130_fd_pr__nfet_01v8[cgd]  @M.X2.XM2.msky130_fd_pr__pfet_01v8[id] @M.X2.XM2.msky130_fd_pr__pfet_01v8[vth]
++ @M.X2.XM2.msky130_fd_pr__pfet_01v8[vgs] @M.X2.XM2.msky130_fd_pr__pfet_01v8[vds] @M.X2.XM2.msky130_fd_pr__pfet_01v8[vdsat]
++ @M.X2.XM2.msky130_fd_pr__pfet_01v8[gm] @M.X2.XM2.msky130_fd_pr__pfet_01v8[gds] @M.X2.XM1.msky130_fd_pr__nfet_01v8[cgs]
++ @M.X2.XM1.msky130_fd_pr__nfet_01v8[cgd]  @M.XM6.msky130_fd_pr__nfet_01v8[id] @M.XM6.msky130_fd_pr__nfet_01v8[vth]
++ @M.XM6.msky130_fd_pr__nfet_01v8[vgs] @M.XM6.msky130_fd_pr__nfet_01v8[vds] @M.XM6.msky130_fd_pr__nfet_01v8[vdsat]
++ @M.XM6.msky130_fd_pr__nfet_01v8[gm] @M.XM6.msky130_fd_pr__nfet_01v8[gds] @M.XM6.msky130_fd_pr__nfet_01v8[cgs]
++ @M.XM6.msky130_fd_pr__nfet_01v8[cgd]  @M.XM5.msky130_fd_pr__pfet_01v8[id] @M.XM5.msky130_fd_pr__pfet_01v8[vth]
++ @M.XM5.msky130_fd_pr__pfet_01v8[vgs] @M.XM5.msky130_fd_pr__pfet_01v8[vds] @M.XM5.msky130_fd_pr__pfet_01v8[vdsat]
++ @M.XM5.msky130_fd_pr__pfet_01v8[gm] @M.XM5.msky130_fd_pr__pfet_01v8[gds] @M.XM5.msky130_fd_pr__nfet_01v8[cgs]
++ @M.XM5.msky130_fd_pr__nfet_01v8[cgd]
+
+
 
 *Simulations
 .control
-  *reset
-  tran 0.1n 0.5u
-  stop when time = 0.1u
-  alterparam vin = 1.8
-  resume
+  tran 0.05n 1u
   setplot tran1
-  plot v(out)
-  *write ~/caravel_fulgor_opamp/xschem/sim_results/opamp_closeloop_tran1.raw
+  plot v(out) v(outx32)+2 v(outx16)+4 v(outx8)+6 v(outx4)+8 v(outx2)+10 v(out_vco)+12 v(en)+14
 
-
-  *dc V3 0 1.8 0.01
-  *setplot dc1
-  *plot v(out1) v(out2) v(out3) v(in)
+  linearize
+  set specwindow=blackman
+  fft v(out_vco)
+  spec 10 1000000 1000 v(out_vco)
+  plot mag(v(out_vco))
 
   reset
-  op
-  setplot op1
+  tran 0.05n 1u
+  setplot tran2
+  linearize
+  fft v(out)
+  spec 10 1000000 1000 v(out)
+  plot mag(v(out))
+  write ~/caravel_fulgor_opamp/xschem/ring_vco/ring_vco_tran1.raw
+
 
 .endc
 
@@ -74,16 +111,71 @@
 **** end user architecture code
 **.ends
 
-* expanding   symbol:  /home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym # of pins=4
+* expanding   symbol:  /home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/not.sym # of pins=5
 
-.subckt not  vdd in out vss
+.subckt not  vdd in out vss vbulk
 *.ipin vdd
 *.ipin in
 *.ipin vss
 *.opin out
-XM1 out in vss vss sky130_fd_pr__nfet_01v8 W=0.42 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
+*.ipin vbulk
+XM1 out in vss vbulk sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
 + ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
-XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 W=0.42 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+.ends
+
+
+* expanding   symbol:  /home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/FD_v2.sym # of pins=4
+
+.subckt FD_v2  clk vss out vdd
+*.opin out
+*.ipin vdd
+*.ipin clk
+*.ipin vss
+XM1 1 4 vss vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM2 1 4 vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM3 1 clk 2 vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM4 1 clk_b 2 vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM5 3 2 vss vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM6 3 2 vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM7 3 clk_b out vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM8 3 clk out vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM9 4 out vss vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM10 4 out vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM11 clk_b clk vss vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM12 clk_b clk vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+.ends
+
+
+* expanding   symbol:  /home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/nand.sym # of pins=6
+
+.subckt nand  vdd A OUT B vss vbulk
+*.opin OUT
+*.ipin vdd
+*.ipin A
+*.ipin B
+*.ipin vss
+*.ipin vbulk
+XM1 net1 B vss vbulk sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM2 OUT A net1 vbulk sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM5 OUT A vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
+XM6 OUT B vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
 + ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1 
 .ends
 
diff --git a/xschem/ring_vco/ring_vco_tran1.raw b/xschem/ring_vco/ring_vco_tran1.raw
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