Update chip_io configs

- adds an obstruction on what will be gpio_control_block at the top
2 files changed
tree: dc5c2a950beb757f8cc9c5195fbdc3b3b15a5b8e
  1. .travis.yml
  2. .travisCI/
  3. LICENSE
  4. Makefile
  5. README.md
  6. def/
  7. doc/
  8. gds/
  9. info.yaml
  10. lef/
  11. macros/
  12. mag/
  13. ngspice/
  14. openlane/
  15. qflow/
  16. scripts/
  17. spi/
  18. verilog/
README.md

CIIC Harness

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Getting Started:

Start by cloning the repo and uncompressing the files.

git clone https://github.com/efabless/caravel.git
cd caravel
make uncompress

Install the required version of the PDK by running the following commands:

export PDK_ROOT=<The place where you want to install the pdk>
make pdk

Then, you can learn more about the caravel chip by watching these video:

Aboard Caravel:

Your area is the full user_project_wrapper, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the user_project_wrapper. For example, if your design is analog or you're using a different tool other than OpenLANE.

If you will use OpenLANE to harden your design, go through the instructions in this README.md.

Then, you will need to put your design aboard the Caravel chip. Make sure you have the following:

  • Magic installed on your machine. We may provide a Dockerized version later.
  • You have your user_project_wrapper.gds under ./gds/ in the Caravel directory.

Run the following command:

export PDK_ROOT=<The place where the installed pdk resides. The same PDK_ROOT used in the pdk installation step>
make

This should merge the GDSes using magic and you'll end up with your version of ./gds/caravel.gds. You should expect hundred of thousands of magic DRC violations with the current “development” state of caravel.

Managment SoC

The managment SoC runs firmware that can be used to:

  • Configure User Project I/O pads
  • Observe and control User Project signals (through on-chip logic analyzer probes)
  • Control the User Project power supply

The memory map of the management SoC can be found here

User Project Area

This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample user project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the User Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the User Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the User Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.