tree: 4726849fabcc91260bcae0f8f7e5a6565ce30eef [path history] [tgz]
  1. .travisCI/
  2. def/
  3. doc/
  4. gds/
  5. lef/
  6. macros/
  7. mag/
  8. maglef/
  9. ngspice/
  10. openlane/
  11. qflow/
  12. scripts/
  13. spi/
  14. utils/
  15. verilog/
  16. xschem/
  17. .travis.yml
  18. info.yaml
  21. Makefile

Prerequisites and Installation

In order to edit and simulate the schematics and the layout the following tools need to be installed:

  • xschem - A schematic capture tool that allows to run simulations using ngspice.
  • ngspice - A circuit simulator.
  • magic - A VLSI layout tool.

After cloning this repository and installing the previous mencioned tools, the PDK form SkyWater needs to be installed. In order to do that, run the install_pdk script in the repo. This script clones the following repositories:

General Purpose Open Source Operational Amplifier (OpAmp)

This project is a test chip, which contains several two stages operationals amplifiers with Miller compensation. This is an all analog desing implemented on the Google-Skywater 130nm Open Source PDK. It is an Open Source project under[Apache License 2.0] (LICENSE).

The OpAmp desing is located in an Open Source SoC Harness obtained from the efabless Caravel Project.

OpAmp Desing

General Specifications:

  • V_{dd}
  • I_{ref}
  • Power Consumption
  • DC Gain
  • Bandwidth
  • Chip Area

CIIC Harness

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware that can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC can be found here

Mega Project Area

This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.