|author||Tim Edwards <email@example.com>||Fri Nov 27 13:56:05 2020 -0500|
|committer||Tim Edwards <firstname.lastname@example.org>||Fri Nov 27 13:56:05 2020 -0500|
Corrected the simple_por layout to avoid overlapping the capacitor plate of the top capacitor with the vias on the bottom capacitor. This corresponds to an update in the magic techfile in open_pdks to enforce the contact overlap prohibition. Also updated the LVS run script to account for the change in directory path to the POR netlist. Corrected the POR netlist to correct the dummy resistor size (they were specified in series instead of in parallel). Re- extracted the POR and ran LVS.
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
Start by cloning the repo and uncompressing the files.
git clone https://github.com/efabless/caravel.git cd caravel make uncompress
Install the required version of the PDK by running the following commands:
export PDK_ROOT=<The place where you want to install the pdk> make pdk
Then, you can learn more about the caravel chip by watching these video:
Your area is the full user_project_wrapper, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the user_project_wrapper. For example, if your design is analog or you're using a different tool other than OpenLANE.
If you will use OpenLANE to harden your design, go through the instructions in this README.md.
Then, you will need to put your design aboard the Caravel chip. Make sure you have the following:
./gds/in the Caravel directory.
Run the following command:
export PDK_ROOT=<The place where the installed pdk resides. The same PDK_ROOT used in the pdk installation step> make
This should merge the GDSes using magic and you'll end up with your version of
./gds/caravel.gds. You should expect hundred of thousands of magic DRC violations with the current “development” state of caravel.
The managment SoC runs firmware that can be used to:
The memory map of the management SoC can be found here
This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample user project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: