|author||R. Timothy Edwards <firstname.lastname@example.org>||Wed Nov 04 12:10:35 2020 -0500|
|committer||GitHub <email@example.com>||Wed Nov 04 12:10:35 2020 -0500|
Merge pull request #30 from Manarabdelaty/wb_mprj_port Connect WB MI A port outputs to the wb bus
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
The managment SoC runs firmware that can be used to:
The memory map of the management SoC is given below
(NOTE: This needs updating; see the README file for an updated list.)
This is the user space. It has limited silicon area (TBD, about 2.8mm x 2.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: