|author||Tim Edwards <email@example.com>||Sun Nov 22 15:10:38 2020 -0500|
|committer||Tim Edwards <firstname.lastname@example.org>||Sun Nov 22 15:10:38 2020 -0500|
Finished implementation of the simple_por Power-on-reset circuit. Completed DRC and LVS, and testbench simulation in ngspice.
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
The managment SoC runs firmware that can be used to:
The memory map of the management SoC can be found here
This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: