blob: f8a651776b432a3a568b9236af45a61ff612a7e8 [file] [log] [blame]
v { version=2.9.8 file_version=1.2}
G {}
K {}
V {}
S {}
E {}
N 1860 50 1890 50 { lab=OUT}
N 1760 50 1860 50 { lab=OUT}
N 1190 -150 1260 -150 { lab=D}
N 1190 450 1300 450 { lab=CLK}
N 1540 50 1760 50 { lab=OUT}
N 1260 -150 1440 -150 { lab=D}
N 1370 -130 1440 -130 { lab=OUT}
N 1370 -130 1370 -70 { lab=OUT}
N 1370 -70 1640 -20 { lab=OUT}
N 1640 -20 1640 50 { lab=OUT}
N 1370 40 1440 40 { lab=#net1}
N 1370 -20 1370 40 { lab=#net1}
N 1370 -20 1640 -70 { lab=#net1}
N 1640 -140 1640 -70 { lab=#net1}
N 1540 -140 1640 -140 { lab=#net1}
N 1480 -10 1480 0 { lab=vdd}
N 1480 -10 1510 -10 { lab=vdd}
N 1480 -90 1480 -80 { lab=vss}
N 1480 -80 1510 -80 { lab=vss}
N 1480 -200 1480 -190 { lab=vdd}
N 1480 -200 1510 -200 { lab=vdd}
N 1480 100 1480 110 { lab=vss}
N 1480 110 1510 110 { lab=vss}
N 1370 260 1440 260 { lab=#net2}
N 1370 260 1370 320 { lab=#net2}
N 1370 320 1640 370 { lab=#net2}
N 1640 370 1640 440 { lab=#net2}
N 1370 430 1440 430 { lab=#net3}
N 1370 370 1370 430 { lab=#net3}
N 1370 370 1640 320 { lab=#net3}
N 1640 250 1640 320 { lab=#net3}
N 1540 250 1640 250 { lab=#net3}
N 1480 380 1480 390 { lab=vdd}
N 1480 380 1510 380 { lab=vdd}
N 1480 300 1480 310 { lab=vss}
N 1480 310 1510 310 { lab=vss}
N 1480 190 1480 200 { lab=vdd}
N 1480 190 1510 190 { lab=vdd}
N 1480 490 1480 500 { lab=#net4}
N 1480 500 1510 500 { lab=#net4}
N 1370 40 1370 240 { lab=#net1}
N 1370 240 1440 240 { lab=#net1}
N 1640 160 1640 250 { lab=#net3}
N 1400 160 1640 160 { lab=#net3}
N 1400 60 1400 160 { lab=#net3}
N 1400 60 1440 60 { lab=#net3}
N 1540 440 1640 440 { lab=#net2}
N 1300 450 1440 450 { lab=CLK}
C {ipin.sym} 1510 -200 2 0 {name=p2 lab=vdd}
C {ipin.sym} 1510 500 2 0 {name=p6 lab=vss}
C {opin.sym} 1890 50 0 0 {name=p3 lab=OUT}
C {ipin.sym} 1190 -150 0 0 {name=p4 lab=D}
C {ipin.sym} 1190 450 0 0 {name=p1 lab=CLK}
C {lab_pin.sym} 1510 -80 2 0 {name=l5 sig_type=std_logic lab=vss}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/nor.sym} 1480 -140 0 0 {name=x1}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/nor.sym} 1480 50 0 0 {name=x2}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/nor.sym} 1480 250 0 0 {name=x3}
C {/home/dhernando/caravel_fulgor_opamp/xschem/ring_vco/nor.sym} 1480 440 0 0 {name=x4}
C {lab_pin.sym} 1510 110 2 0 {name=l1 sig_type=std_logic lab=vss}
C {lab_pin.sym} 1510 310 2 0 {name=l3 sig_type=std_logic lab=vss}
C {lab_pin.sym} 1510 -10 2 0 {name=l7 sig_type=std_logic lab=vdd
}
C {lab_pin.sym} 1510 190 2 0 {name=l8 sig_type=std_logic lab=vdd
}
C {lab_pin.sym} 1510 380 2 0 {name=l9 sig_type=std_logic lab=vdd
}