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Branches

  1. 975b344 [Localrun03] Added chip art + drc clean by Ganesh Gore · 5 weeks ago master
  2. 77579f5 [Localrun03] All clean by Ganesh Gore · 5 weeks ago
  3. f260b1e [Check] Updated yaml to pass hierarchy check by Ganesh Gore · 5 weeks ago
  4. bcd3eee [BugFix] Wrong rsync file by Ganesh Gore · 5 weeks ago
  5. d0221f2 [Sync] Updated files from caravel repo by Ganesh Gore · 5 weeks ago

Caravel-SOFA-HD

Highlights

  • Opensource 12x12 FPGA designed using OpenFPGA prototyping tool
  • Designed with Skywater130nm PDK with HD standard cell library
  • Base K4 architecture from VPR with 40 vertical and horizontal channels
  • No adders (carry-chain) or flipflop reset pins
  • Designed using commercial PnR tool

Contribution

NOTE

  • This repository is created for The eFabless Open MPW shuttle program submission
  • The repository is auto-updated. For any commits issues and feature requests, please check Skywater-OpenFPGA

Caravel design and CIIC Harness

For caravel related updated refer efabless/caravel