Update to use openlane version of digital
diff --git a/gds/caravel.gds.gz b/gds/caravel.gds.gz
index 4c58210..e59c25c 100644
--- a/gds/caravel.gds.gz
+++ b/gds/caravel.gds.gz
Binary files differ
diff --git a/gds/caravel.mag b/gds/caravel.mag
index 234a598..bdd4799 100644
--- a/gds/caravel.mag
+++ b/gds/caravel.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1612384210
+timestamp 1612435203
 << checkpaint >>
 rect -1260 -1260 718860 1038860
 << metal1 >>
@@ -80750,187 +80750,187 @@
 rect 459478 40175 459520 40411
 rect 454976 40133 459520 40175
 use user_id_programming  user_id_value ../mag
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 656624 0 1 80926
 box 0 0 7109 7077
 use storage  storage ../mag
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 52032 0 1 53156
 box 0 0 88934 189234
 use mgmt_core  soc ../mag
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 210422 0 1 53602
 box 0 0 430000 180000
 use sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped  rstb_level ../mag
-timestamp 1612384210
+timestamp 1612435203
 transform -1 0 137896 0 -1 51956
 box -66 -83 5058 5000
 use simple_por  por ../mag
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 654176 0 -1 112880
 box 25 11 11344 8338
 use mgmt_protect  mgmt_buffers ../mag
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 212180 0 1 246848
 box -1586 -1605 201502 19557
 use gpio_control_block  gpio_control_bidir\[1\] ../mag
-timestamp 1612384210
+timestamp 1612435203
 transform -1 0 708537 0 1 166200
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_bidir\[0\]
-timestamp 1612384210
+timestamp 1612435203
 transform -1 0 708537 0 1 121000
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[36\]
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 8567 0 1 245800
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[37\]
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 8567 0 1 202600
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[2\]
-timestamp 1612384210
+timestamp 1612435203
 transform -1 0 708537 0 1 211200
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[3\]
-timestamp 1612384210
+timestamp 1612435203
 transform -1 0 708537 0 1 256400
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[33\]
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 8567 0 1 375400
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[34\]
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 8567 0 1 332200
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[35\]
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 8567 0 1 289000
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[4\]
-timestamp 1612384210
+timestamp 1612435203
 transform -1 0 708537 0 1 301400
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[5\]
-timestamp 1612384210
+timestamp 1612435203
 transform -1 0 708537 0 1 346400
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[7\]
-timestamp 1612384210
+timestamp 1612435203
 transform -1 0 708537 0 1 479800
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[6\]
-timestamp 1612384210
+timestamp 1612435203
 transform -1 0 708537 0 1 391600
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[32\]
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 8567 0 1 418600
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[31\]
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 8567 0 1 546200
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[30\]
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 8567 0 1 589400
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[29\]
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 8567 0 1 632600
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[9\]
-timestamp 1612384210
+timestamp 1612435203
 transform -1 0 708537 0 1 568800
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[8\]
-timestamp 1612384210
+timestamp 1612435203
 transform -1 0 708537 0 1 523800
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[10\]
-timestamp 1612384210
+timestamp 1612435203
 transform -1 0 708537 0 1 614000
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[28\]
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 8567 0 1 675800
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[27\]
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 8567 0 1 719000
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[26\]
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 8567 0 1 762200
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[13\]
-timestamp 1612384210
+timestamp 1612435203
 transform -1 0 708537 0 1 749200
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[12\]
-timestamp 1612384210
+timestamp 1612435203
 transform -1 0 708537 0 1 704200
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[11\]
-timestamp 1612384210
+timestamp 1612435203
 transform -1 0 708537 0 1 659000
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[25\]
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 8567 0 1 805400
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[24\]
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 8567 0 1 931224
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[23\]
-timestamp 1612384210
+timestamp 1612435203
 transform 0 1 97200 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[22\]
-timestamp 1612384210
+timestamp 1612435203
 transform 0 1 148600 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[21\]
-timestamp 1612384210
+timestamp 1612435203
 transform 0 1 200000 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[20\]
-timestamp 1612384210
+timestamp 1612435203
 transform 0 1 251400 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[19\]
-timestamp 1612384210
+timestamp 1612435203
 transform 0 1 303000 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[18\]
-timestamp 1612384210
+timestamp 1612435203
 transform 0 1 353400 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[17\]
-timestamp 1612384210
+timestamp 1612435203
 transform 0 1 420800 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[16\]
-timestamp 1612384210
+timestamp 1612435203
 transform 0 1 497800 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[15\]
-timestamp 1612384210
+timestamp 1612435203
 transform 0 1 549200 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[14\]
-timestamp 1612384210
+timestamp 1612435203
 transform -1 0 708537 0 1 927600
 box 0 0 33934 18344
 use user_project_wrapper  mprj ../mag
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 65308 0 1 278716
 box -8576 -7506 592500 711442
 use chip_io  padframe ../mag
-timestamp 1612384210
+timestamp 1612435203
 transform 1 0 0 0 1 0
 box 0 0 717600 1037600
 << properties >>
diff --git a/gds/caravel.old.gds.gz b/gds/caravel.old.gds.gz
index 24a4c79..4c58210 100644
--- a/gds/caravel.old.gds.gz
+++ b/gds/caravel.old.gds.gz
Binary files differ
diff --git a/gds/fractional_n_divider.GDS b/gds/fractional_n_divider.GDS
new file mode 100644
index 0000000..90afb37
--- /dev/null
+++ b/gds/fractional_n_divider.GDS
Binary files differ
diff --git a/gds/sky130_drc.txt b/gds/sky130_drc.txt
index b38ada5..2ef68e7 100644
--- a/gds/sky130_drc.txt
+++ b/gds/sky130_drc.txt
@@ -733,6 +733,1374 @@
    <categories>
    </categories>
   </category>
+  <category>
+   <name>licon.7</name>
+   <description>licon.7 : min. tap enclosure of licon by one of 2 opposite edges : 0.12um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.8</name>
+   <description>licon.8 : min. poly enclosure of licon : 0.05um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.8a</name>
+   <description>licon.8a : min. poly enclosure of licon by one of 2 opposite edges : 0.08um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.10</name>
+   <description>licon.10 : min. licon spacing to varac channel : 0.25um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.11</name>
+   <description>licon.11 : min. licon spacing to gate : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.11a</name>
+   <description>licon.11a : min. licon spacing to gate inside areaid.sc : 0.05um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.11c</name>
+   <description>licon.11c : min. licon spacing to gate for specific cells: 0.04um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.12</name>
+   <description>licon.12 : max. sd width without licon : 5.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13</name>
+   <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.14</name>
+   <description>licon.14 : min. poly licon spacing to difftap : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.15</name>
+   <description>licon.15 : min. npc enclosure of poly-licon : 0.1um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.16</name>
+   <description>licon.16 : tap must enclose one licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.17</name>
+   <description>licon.17 : tap must not straddle poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.18</name>
+   <description>licon.18 : npc mut enclosed one poly-licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.1</name>
+   <description>li.1 : min. li width : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.1a</name>
+   <description>li.1a : min. li width for the cells s8rf2_xcmvpp_hd5_* : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3</name>
+   <description>li.3 : min. li spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3a</name>
+   <description>li.3a : min. li spacing for the cells s8rf2_xcmvpp_hd5_* : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.5</name>
+   <description>li.5 : min. li enclosure of licon of 2 opposite edges : 0.08um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.6</name>
+   <description>li.6 : min. li area : 0.0561um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp.1</name>
+   <description>vpp.1 : min. vpp width : 1.43um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp.3</name>
+   <description>vpp.3 : vpp must not overlapp poly or diff or tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp.4</name>
+   <description>vpp.4 : vpp must not straddle nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp.4</name>
+   <description>vpp.4 : vpp must not straddle dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp.5</name>
+   <description>vpp.5 : min. vpp spacing to poly or li or m1 or m2 : 1.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp.5a</name>
+   <description>vpp.5a : max. m3 density in vpp : 0.25</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp.5b</name>
+   <description>vpp.5b : max. m4 density in vpp : 0.3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp.5c</name>
+   <description>vpp.5c : max. m5 density in vpp : 0.4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp.8</name>
+   <description>vpp.8 : nwell enclosure of vpp : 1.5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp.9</name>
+   <description>vpp.9 : vpp spacing to nwell : 1.5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.1</name>
+   <description>capm.1 : min. capm width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2a</name>
+   <description>capm.2a : min. capm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b</name>
+   <description>capm.2b : min. capm spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3</name>
+   <description>capm.3 : min. m2 enclosure of capm : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.4</name>
+   <description>capm.4 : min. capm enclosure of via2 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.5</name>
+   <description>capm.5 : min. capm spacing to via2 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.6</name>
+   <description>capm.6 : max. capm lenght/width : 20um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.7</name>
+   <description>capm.7 : capm not rectangle</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.8</name>
+   <description>capm.8 : min. capm spacing to via : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.10</name>
+   <description>capm.10 : capm must not straddle nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.10</name>
+   <description>capm.10 : capm must not straddle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.10</name>
+   <description>capm.10 : capm must not straddle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.10</name>
+   <description>capm.10 : capm must not straddle poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.10</name>
+   <description>capm.10 : capm must not straddle li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.10</name>
+   <description>capm.10 : capm must not straddle m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.11</name>
+   <description>capm.11 : min. capm spacing to m2 not overlapping capm : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1</name>
+   <description>ct.1 : minimum/maximum width of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.2</name>
+   <description>ct.2 : min. mcon spacing : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.4</name>
+   <description>ct.4 : mcon should covered by li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.1</name>
+   <description>m1.1 : min. m1 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.2</name>
+   <description>m1.2 : min. m1 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.3ab</name>
+   <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4</name>
+   <description>m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a</name>
+   <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.6</name>
+   <description>m1.6 : min. m1 area : 0.083um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.7</name>
+   <description>m1.7 : min. m1 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.5</name>
+   <description>m1.5 : min. m1 enclosure of mcon of 2 opposite edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4c.5c</name>
+   <description>via.4c.5c : m1 must enclose all via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a</name>
+   <description>via.1a : minimum/maximum width of via : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1b</name>
+   <description>via.1b : minimum/maximum width of via in areaid.mt: 0.15um or 0.23um or 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.2</name>
+   <description>via.2 : min. via spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a</name>
+   <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4b</name>
+   <description>via.4b : min. m1 enclosure of 0.23um via : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via1.5a</name>
+   <description>via1.5a : min. m1 enclosure of 0.15um via of 2 opposite edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via1.5b</name>
+   <description>via1.5b : min. m1 enclosure of 0.23um via of 2 opposite edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.1</name>
+   <description>m2.1 : min. m2 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.2</name>
+   <description>m2.2 : min. m2 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.3ab</name>
+   <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.6</name>
+   <description>m2.6 : min. m2 area : 0.0676um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.7</name>
+   <description>m2.7 : min. m2 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.via</name>
+   <description>m2.via : m2 must enclose via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4</name>
+   <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.5</name>
+   <description>m2.5 : min. m2 enclosure of via of 2 opposite edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2</name>
+   <description>via2 : m2 must enclose all via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a</name>
+   <description>via2.1a : minimum/maximum width of via2 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1b</name>
+   <description>via2.1b : minimum/maximum width of via2 in areaid.mt: 0.2um or 1.2um or 1.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.2</name>
+   <description>via2.2 : min. via2 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4</name>
+   <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4a</name>
+   <description>via2.4a : min. m2 enclosure of 1.5um via2 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.5</name>
+   <description>via2.5 : min. m2 enclosure of via2 of 2 opposite edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.1</name>
+   <description>m3.1 : min. m3 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.2</name>
+   <description>m3.2 : min. m3 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.3ab</name>
+   <description>m3.3ab : min. 3um.m3 spacing m3 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.6</name>
+   <description>m3.6 : min. m2 area : 0.24um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.via2</name>
+   <description>m3.via2 : m3 must enclose via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4</name>
+   <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3</name>
+   <description>via3 : m3 must enclose all via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1a</name>
+   <description>via3.1a : minimum/maximum width of via3 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1a</name>
+   <description>via3.1a : minimum/maximum width of via3 in areaid.mt: 0.2um or 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.2</name>
+   <description>via3.2 : min. via3 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4</name>
+   <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.5</name>
+   <description>via3.5 : min. m2 enclosure of via3 of 2 opposite edges : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.1</name>
+   <description>nsm.1 : min. nsm width : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.2</name>
+   <description>nsm.2 : min. nsm spacing : 4.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.4</name>
+   <description>nsm.4 : min. nsm enclosure of diff : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.4</name>
+   <description>nsm.4 : min. nsm enclosure of tap : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.4</name>
+   <description>nsm.4 : min. nsm enclosure of poly : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.4</name>
+   <description>nsm.4 : min. nsm enclosure of li : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.4</name>
+   <description>nsm.4 : min. nsm enclosure of m1 : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.4</name>
+   <description>nsm.4 : min. nsm enclosure of m2 : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.4</name>
+   <description>nsm.4 : min. nsm enclosure of m3 : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.4</name>
+   <description>nsm.4 : min. nsm enclosure of m4 : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.4</name>
+   <description>nsm.4 : min. nsm enclosure of m5 : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.4</name>
+   <description>nsm.4 : min. nsm enclosure of cfom : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.3</name>
+   <description>nsm.3 : min. nsm spacing to diff : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.3</name>
+   <description>nsm.3 : min. nsm spacing to tap : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.3</name>
+   <description>nsm.3 : min. nsm spacing to poly : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.3</name>
+   <description>nsm.3 : min. nsm spacing to li : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.3</name>
+   <description>nsm.3 : min. nsm spacing to m1 : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.3</name>
+   <description>nsm.3 : min. nsm spacing to m2 : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.3</name>
+   <description>nsm.3 : min. nsm spacing to m3 : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.3</name>
+   <description>nsm.3 : min. nsm spacing to m4 : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.3</name>
+   <description>nsm.3 : min. nsm spacing to m5 : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.3</name>
+   <description>nsm.3 : min. nsm spacing to cfom : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.1</name>
+   <description>m4.1 : min. m4 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.2</name>
+   <description>m4.2 : min. m4 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.4</name>
+   <description>m4.4 : min. m2 area : 0.24um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.5ab</name>
+   <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.via3</name>
+   <description>m4.via3 : m4 must enclose via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3</name>
+   <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1a</name>
+   <description>via4.1a : minimum/maximum width of via4 : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.2</name>
+   <description>via4.2 : min. via4 spacing : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4</name>
+   <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4</name>
+   <description>via4 : m4 must enclose all via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.1</name>
+   <description>m5.1 : min. m5 width : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.2</name>
+   <description>m5.2 : min. m5 spacing : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.via4</name>
+   <description>m5.via4 : m5 must enclose via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3</name>
+   <description>m4.3 : min. m5 enclosure of via4 : 0.31um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad.2</name>
+   <description>pad.2 : min. pad spacing : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf.1</name>
+   <description>mf.1 : minimum/maximum width of fuse : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf.2</name>
+   <description>mf.2 : minimum/maximum length of fuse : 7.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf.3</name>
+   <description>mf.3 : min. fuse center spacing : 2.76um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.1</name>
+   <description>hvi.1 : min. hvi width : 0.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.2</name>
+   <description>hvi.2 : min. hvi spacing, merge if less : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.4</name>
+   <description>hvi.4 : hvi must not overlapp tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvnwell.8</name>
+   <description>hvnwelli.8 : min. hvnwel spacing to nwell : 2.0</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvnwel.9</name>
+   <description>hvnwell.9 : hvi must overlapp hvnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvdifftap.14</name>
+   <description>hvdifftap.14 : min. diff inside hvi width : 0.29um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvdifftap.14a</name>
+   <description>hvdifftap.14a : min. p+diff resistor inside hvi width : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvdifftap.15a</name>
+   <description>hvdifftap.15a : min. diff inside hvi spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvdifftap.15b</name>
+   <description>hvdifftap.15b : min. n+diff inside hvi spacing to p+diff inside hvi except abutting: 0.37um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvdifftap.16</name>
+   <description>hvdifftap.16 : min. tap inside hvi abuttng diff : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvdifftap.17</name>
+   <description>hvdifftap.17 : min. hvnwell enclosure of p+diff : 0.33um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvdifftap.18</name>
+   <description>hvdifftap.18 : min. hvnwell spacing to n+diff : 0.43um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvdifftap.19</name>
+   <description>hvdifftap.19 : min. hvnwell enclosure of n+tap : 0.33um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvdifftap.20</name>
+   <description>hvdifftap.20 : min. hvnwell spacing to p+tap : 0.43um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvdifftap.21</name>
+   <description>hvdifftap.21 : diff must not straddle hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvdifftap.21</name>
+   <description>hvdifftap.21 : tap must not straddle hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvdifftap.22</name>
+   <description>hvdifftap.22 : min. hvi enclosure of diff or tap : 0.18um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvdifftap.23</name>
+   <description>hvdifftap.23 : min. hvi spacing to diff or tap : 0.18um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvdifftap.24</name>
+   <description>hvdifftap.24 : min. hv n+diff spacing to nwell : 0.43um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvdifftap.25</name>
+   <description>hvdifftap.25 : min. n+diff inside hvi spacing accros p+tap  : 1.07um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvpoly.13</name>
+   <description>hvpoly.13: min. hvi gate length : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvpoly.14</name>
+   <description>hvpoly.14 : poly must not straddle hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.1</name>
+   <description>hvntm.1 : min. hvntm width : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.2</name>
+   <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.3</name>
+   <description>hvntm.3 : min. hvntm enclosure of hv n+diff : 0.185um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.4</name>
+   <description>hvntm.4 : min. hvntm spacing to n+diff : 0.185um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.5</name>
+   <description>hvntm.5 : min. hvntm spacing to p+diff : 0.185um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.6a</name>
+   <description>hvntm.6a : min. hvntm spacing to p+tap : 0.185um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.9</name>
+   <description>hvntm.9 : hvntm must not overlapp areaid.ce</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>denmos.1</name>
+   <description>denmos.1 : min. de_nfet gate width : 1.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>denmos.2</name>
+   <description>denmos.2 : min. de_nfet source ouside poly width : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>denmos.3</name>
+   <description>denmos.3 : min. de_nfet source inside poly width : 0.925um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>denmos.4</name>
+   <description>denmos.4 : min. de_nfet drain width : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>denmos.5</name>
+   <description>denmos.5 : min. de_nfet source inside nwell width : 0.225m</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>denmos.6</name>
+   <description>denmos.6 : min. de_nfet source spacing to drain : 1.585um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>denmos.7</name>
+   <description>denmos.7 : min. de_nfet channel width : 5.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>denmos.8</name>
+   <description>denmos.8 : 90deg. not allowed for de_nfet drain</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>denmos.9a</name>
+   <description>denmos.9a : 90deg. not allowed for de_nfet nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>denmos.9a</name>
+   <description>denmos.9a : 45deg. bevels of de_nfet nwell should be 0.43um from corners</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>denmos.9a</name>
+   <description>denmos.9a : 45deg. bevels of de_nfet nwell should be 0.43um from corners</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>denmos.9b</name>
+   <description>denmos.9b : 45deg. bevels of de_nfet drain should be 0.05um from corners</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>denmos.9b</name>
+   <description>denmos.9b : 45deg. bevels of de_nfet drain should be 0.05um from corners</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>denmos.10</name>
+   <description>denmos.10 : min. nwell enclosure of de_nfet drain : 0.66um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>denmos.11</name>
+   <description>denmos.11 : min. de_nfet nwell spacing to tap : 0.86um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>denmos.12</name>
+   <description>denmos.12 : min. de_nfet nwell : 2.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>denmos.13</name>
+   <description>denmos.13 : min. nsdm enclosure of de_nfet source : 0.13um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>depmos.1</name>
+   <description>depmos.1 : min. de_pfet gate width : 1.05um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>depmos.2</name>
+   <description>depmos.2 : min. de_pfet source ouside poly width : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>depmos.3</name>
+   <description>depmos.3 : min. de_pfet source inside poly width : 0.92um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>depmos.4</name>
+   <description>depmos.4 : min. de_pfet drain width : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>depmos.5</name>
+   <description>depmos.5 : min. de_pfet source inside nwell width : 0.26m</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>depmos.6</name>
+   <description>depmos.6 : min. de_pfet source spacing to drain : 1.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>depmos.7</name>
+   <description>depmos.7 : min. de_pfet channel width : 5.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>depmos.8</name>
+   <description>depmos.8 : 90deg. not allowed for de_pfet drain</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>depmos.9a</name>
+   <description>depmos.9a : 90deg. not allowed for de_pfet pwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>depmos.9a</name>
+   <description>depmos.9a : 45deg. bevels of de_pfet pwell should be 0.43um from corners</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>depmos.9a</name>
+   <description>depmos.9a : 45deg. bevels of de_pfet pwell should be 0.43um from corners</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>depmos.9b</name>
+   <description>depmos.9b : 45deg. bevels of de_pfet drain should be 0.05um from corners</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>depmos.9b</name>
+   <description>depmos.9b : 45deg. bevels of de_pfet drain should be 0.05um from corners</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>depmos.10</name>
+   <description>depmos.10 : min. pwell enclosure of de_pfet drain : 0.86um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>depmos.11</name>
+   <description>depmos.11 : min. de_pfet pwell spacing to tap : 0.66um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>depmos.12</name>
+   <description>depmos.12 : min. psdm enclosure of de_pfet source : 0.13um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>extd.1</name>
+   <description>extd.1 : difftap must not straddle areaid.en</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>extd.2</name>
+   <description>extd.2 : poly must not overlapp entirely difftap in areaid.en</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi.1</name>
+   <description>vhvi.1 : min. vhvi width : 0.02um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi.2</name>
+   <description>vhvi.2 : vhvi must not overlap areaid.ce</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi.3</name>
+   <description>vhvi.3 : vhvi must not overlap hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi.5</name>
+   <description>vhvi.5 : vhvi must not straddle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi.5</name>
+   <description>vhvi.5 : vhvi must not straddle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi.7</name>
+   <description>vhvi.7 : vhvi must not straddle poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hv.nwell.1</name>
+   <description>hv.nwell.1 : min. vhvi nwell spacing to nwell : 2.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hv.diff.1</name>
+   <description>hv.diff.1 : min. vhvi diff spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hv.diff.2</name>
+   <description>hv.diff.2 : min. vhvi nwell spacing n+diff : 0.43um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hv.diff.3a</name>
+   <description>hv.diff.3a : min. vhvi n+diff spacing nwell : 0.55um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hv.poly.2</name>
+   <description>hv.poly.2 : min. vhvi poly spacing to diff : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hv.poly.3</name>
+   <description>hv.poly.3 : min. vhvi poly spacing to nwell : 0.55um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hv.poly.4</name>
+   <description>hv.poly.4 : min. nwell enclosure of vhvi poly : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi.1</name>
+   <description>uhvi.1 : diff must not straddle uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi.1</name>
+   <description>uhvi.1 : tap must not straddle uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi.2</name>
+   <description>uhvi.2 : poly must not straddle uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi.3</name>
+   <description>uhvi.3 : uhvi must not enclose pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi.4</name>
+   <description>uhvi.4 : dnwell must not straddle uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi.5</name>
+   <description>uhvi.5 : uhvi must not enclose areaid.en20</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi.7</name>
+   <description>uhvi.7 : uhvi must not enclose natfet</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwres.2</name>
+   <description>pwres.2 : min. pwell resistor width : 2.65um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwres.2</name>
+   <description>pwres.2 : max. pwell resistor width : 2.65um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwres.3</name>
+   <description>pwres.3 : min. pwell resistor length : 26.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwres.4</name>
+   <description>pwres.4 : max. pwell resistor length : 265um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwres.5</name>
+   <description>pwres.5 : min. pwell resistor tap spacing to nwell : 0.22um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwres.5</name>
+   <description>pwres.5 : max. pwell resistor tap spacing to nwell : 0.22um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwres.6</name>
+   <description>pwres.6 : min. width of tap inside pwell resistor : 0.53um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwres.6</name>
+   <description>pwres.6 : max. width of tap inside pwell resistor : 0.53um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwres.8</name>
+   <description>pwres.8 : diff not allowed inside pwell resistor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwres.8</name>
+   <description>pwres.8 : poly not allowed inside pwell resistor</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rfdiode.1</name>
+   <description>rfdiode.1 : non 90 degree angle areaid.re</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rfdiode.2</name>
+   <description>rfdiode.2 : areaid.re must coincide rf nwell diode</description>
+   <categories>
+   </categories>
+  </category>
  </categories>
  <cells>
   <cell>
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