blob: 45f65a4bfbd2dedcf40a343e9ecd028fad90366e [file] [log] [blame]
module mgmt_core #(
parameter MPRJ_IO_PADS = 32,
parameter MPRJ_PWR_PADS = 32
) (
`ifdef LVS
inout vdd1v8,
inout vss,
// GPIO (dedicated pad)
output gpio_out_pad, // Connect to out on gpio pad
input gpio_in_pad, // Connect to in on gpio pad
output gpio_mode0_pad, // Connect to dm[0] on gpio pad
output gpio_mode1_pad, // Connect to dm[2] on gpio pad
output gpio_outenb_pad, // Connect to oe_n on gpio pad
output gpio_inenb_pad, // Connect to inp_dis on gpio pad
// Flash memory control (SPI master)
output flash_csb,
output flash_clk,
output flash_csb_oeb,
output flash_clk_oeb,
output flash_io0_oeb,
output flash_io1_oeb,
output flash_csb_ieb,
output flash_clk_ieb,
output flash_io0_ieb, output flash_io1_ieb,
output flash_io0_do,
output flash_io1_do,
input flash_io0_di,
input flash_io1_di,
// Master reset
input resetb,
input porb,
// Clocking
input clock,
// LA signals
input [127:0] la_input, // From Mega-Project to cpu
output [127:0] la_output, // From CPU to Mega-Project
output [127:0] la_oen, // LA output enable
// Housekeeping SPI
output sdo_out,
output sdo_outenb,
output jtag_out,
output jtag_outenb,
// Mega-Project Control Signals
input [MPRJ_IO_PADS-1:0] mgmt_in_data,
output [MPRJ_IO_PADS-1:0] mgmt_out_data,
output mprj_io_loader_resetn,
output mprj_io_loader_clock,
output mprj_io_loader_data,
// WB MI A (Mega project)
input mprj_ack_i,
input [31:0] mprj_dat_i,
output mprj_cyc_o,
output mprj_stb_o,
output mprj_we_o,
output [3:0] mprj_sel_o,
output [31:0] mprj_adr_o,
output [31:0] mprj_dat_o,
// WB MI B Switch
input xbar_ack_i,
input [31:0] xbar_dat_i,
output xbar_cyc_o,
output xbar_stb_o,
output xbar_we_o,
output [3:0] xbar_sel_o,
output [31:0] xbar_adr_o,
output [31:0] xbar_dat_o,
output core_clk,
output user_clk,
output core_rstn,
// Metal programmed user ID / mask revision vector
input [31:0] mask_rev
wire ext_clk_sel;
wire pll_clk, pll_clk90;
wire ext_reset;
wire hk_connect;
caravel_clocking clocking(
`ifdef LVS
.ext_reset(ext_reset), // From housekeeping SPI
// The following functions are connected to specific user project
// area pins, when under control of the management area (during
// startup, and when not otherwise programmed for the user project).
// JTAG = jtag_out (inout)
// SDO = sdo_out (output) (shared with SPI master)
// SDI = mgmt_in_data[2] (input) (shared with SPI master)
// CSB = mgmt_in_data[3] (input) (shared with SPI master)
// SCK = mgmt_in_data[4] (input) (shared with SPI master)
// ser_rx = mgmt_in_data[5] (input)
// ser_tx = mgmt_out_data[6] (output)
// irq = mgmt_in_data[7] (input)
// flash_csb = mgmt_out_data[8] (output) (user area flash)
// flash_sck = mgmt_out_data[9] (output) (user area flash)
// flash_io0 = mgmt_in/out_data[10] (input) (user area flash)
// flash_io1 = mgmt_in/out_data[11] (output) (user area flash)
// OEB lines for [0] and [1] are the only ones connected directly to
// the pad. All others have OEB controlled by the configuration bit
// in the control block.
mgmt_soc #(
) soc (
`ifdef LVS
// Flash
// SPI pass-through to/from SPI flash controller
// SPI master->slave direct connection
// Logic Analyzer
// Mega-Project I/O Configuration
// I/O data
// Mega Project Slave ports (WB MI A)
// Crossbar Switch
.xbar_we_o (xbar_we_o),
digital_pll pll (
`ifdef LVS
.clockp({pll_clk, pll_clk90}),
// JTAG (to be implemented)
wire jtag_out = 1'b0;
wire jtag_outenb = 1'b1;
// Housekeeping SPI vectors
wire [4:0] spi_pll_div;
wire [2:0] spi_pll_sel;
wire [2:0] spi_pll90_sel;
wire [25:0] spi_pll_trim;
// Housekeeping SPI (SPI slave module)
housekeeping_spi housekeeping (
`ifdef LVS
.SCK((hk_connect) ? mgmt_out_data[4] : mgmt_in_data[4]),
.SDI((hk_connect) ? mgmt_out_data[2] : mgmt_in_data[2]),
.CSB((hk_connect) ? mgmt_out_data[3] : mgmt_in_data[3]),