Merge branch 'master' of https://github.com/efabless/caravel
diff --git a/README.md b/README.md
index 53d1508..6cc7c7a 100644
--- a/README.md
+++ b/README.md
@@ -1,104 +1,28 @@
-# CIIC Harness  
+# ابتدا(Ibtida) SoC
 
-A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
+ابتدا means the start of something. This is a minimal SoC built around a RISC-V based 5 stage pipelined core Buraq-Mini. Both the SoC and the core are made from scratch using CHISEL HDL. The CHISEL source code as well as the emitted verilog are provided in the relvant folders. It is still Work In Progress (WIP). The current SoC architecture is given below.
 
 <p align=”center”>
-<img src="/doc/ciic_harness.png" width="75%" height="75%"> 
+<img src="/doc/IbtidaSoC.png" > 
 </p>
 
-## Getting Started:
 
-Start by cloning the repo and uncompressing the files.
-```bash
-git clone https://github.com/efabless/caravel.git
-cd caravel
-make uncompress
-```
+## Contributors
+Main contributors are:
+1. Engr. Muhammad Hadir Khan (RTL design based on CHISEL)(Owner).
+2. Sajjad Ahmed              (RTL design based on CHISEL).
+3. Engr. Aireen Aamir Jalal  (APR flow with OpenLANE RTL-GDSII).
 
-Then you need to install the open_pdks prerequisite:
- - [Magic VLSI Layout Tool](http://opencircuitdesign.com/magic/index.html) is needed to run open_pdks -- version >= 8.3.60*
 
- > \* Note: You can avoid the need for the magic prerequisite by using the openlane docker to do the installation step in open_pdks. This [file](https://github.com/efabless/openlane/blob/develop/travisCI/travisBuild.sh) shows how.
-
-Install the required version of the PDK by running the following commands:
-
-```bash
-export PDK_ROOT=<The place where you want to install the pdk>
-make pdk
-```
-
-Then, you can learn more about the caravel chip by watching these video:
-- Caravel User Project Features -- https://youtu.be/zJhnmilXGPo
-- Aboard Caravel -- How to put your design on Caravel? -- https://youtu.be/9QV8SDelURk
-- Things to Clarify About Caravel -- What versions to use with Caravel? -- https://youtu.be/-LZ522mxXMw
-
-## Aboard Caravel:
-
-Your area is the full user_project_wrapper, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the user_project_wrapper. For example, if your design is analog or you're using a different tool other than OpenLANE.
-
-If you will use OpenLANE to harden your design, go through the instructions in this [README.md][0].
-
-Then, you will need to put your design aboard the Caravel chip. Make sure you have the following:
-
-- [Magic VLSI Layout Tool](http://opencircuitdesign.com/magic/index.html) installed on your machine. We may provide a Dockerized version later.\*
-- You have your user_project_wrapper.gds under `./gds/` in the Caravel directory.
-
- > \* **Note:** You can avoid the need for the magic prerequisite by using the openlane docker to run the make step. This [section](#running-make-using-openlane's-magic) shows how.
-
-Run the following command:
-
-```bash
-export PDK_ROOT=<The place where the installed pdk resides. The same PDK_ROOT used in the pdk installation step>
-make
-```
-
-This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect hundred of thousands of magic DRC violations with the current "development" state of caravel.
-
-## Running Make using OpenLANE's Magic
-
-To use the magic installed inside Openlane to complete the final GDS streaming out step, export the following:
-
-```bash
-export PDK_ROOT=<The location where the pdk is installed>
-export OPENLANE_ROOT=<the absolute path to the openlane directory cloned or to be cloned>
-export IMAGE_NAME=<the openlane image name installed on your machine. Preferably openlane:rc5>
-export CARAVEL_PATH=$(pwd)
-```
-
-Then, mount the docker:
-
-```bash
-docker run -it -v $CARAVEL_PATH:$CARAVEL_PATH -v $OPENLANE_ROOT:/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e CARAVEL_PATH=$CARAVEL_PATH -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME
-```
-
-Finally, once inside the docker run the following commands:
-```bash
-cd $CARAVEL_PATH
-make
-exit
-```
-
-This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect hundred of thousands of magic DRC violations with the current "development" state of caravel.
-
-## Managment SoC
-The managment SoC runs firmware that can be used to:
-- Configure User Project I/O pads
-- Observe and control User Project signals (through on-chip logic analyzer probes)
-- Control the User Project power supply
-
-The memory map of the management SoC can be found [here](verilog/rtl/README)
-
-## User Project Area
-This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10).  See [the Caravel  premliminary datasheet](doc/caravel_datasheet.pdf) for details.
-The repository contains a [sample user project](/verilog/rtl/user_proj_example.v) that contains a binary 32-bit up counter.  </br>
-
-<p align=”center”>
-<img src="/doc/counter_32.png" width="50%" height="50%">
-</p>
-
-The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:
-1. Configure the User Project I/O pads as o/p. Observe the counter value in the testbench: [IO_Ports Test](verilog/dv/caravel/user_proj_example/io_ports).
-2. Configure the User Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: [LA_Test1](verilog/dv/caravel/user_proj_example/la_test1).
-3. Configure the User Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles:  [LA_Test2](verilog/dv/caravel/user_proj_example/la_test2).
-
-[0]: openlane/README.md
+Other contributors:
+1. Dr. Ali Ahmed (Supervisor).
+2. Dr. Roomi Naqvi (Supervisor).
+3. Engr. Farhan Ahmed Karim (Supervisor).
+4. Engr. Asad Hussain Jaffri (Supervisor).
+5. Zain Rizwan Khan
+6. Hamza Shabbir
+7. Uzair Khan
+8. Wajeh
+9. Usman Zain
+10. Zeeshan
+11. Waleed
diff --git a/chisel/Buraq-mini/Pipeline.png b/chisel/Buraq-mini/Pipeline.png
new file mode 100644
index 0000000..1093ec6
--- /dev/null
+++ b/chisel/Buraq-mini/Pipeline.png
Binary files differ
diff --git a/chisel/Buraq-mini/README.md b/chisel/Buraq-mini/README.md
new file mode 100644
index 0000000..447f761
--- /dev/null
+++ b/chisel/Buraq-mini/README.md
@@ -0,0 +1,60 @@
+# RISC-V 5-stage Pipelined Core
+### Designed by Muhammad Hadir Khan
+\
+\
+![alt text](https://github.com/merledu/5-stage-Pipelined-CPU/blob/master/Pipeline.png)
+\
+\
+First of all get started by cloning this repository on your machine.  
+```ruby
+git clone https://github.com/merledu/5-stage-Pipelined-CPU.git
+```
+Create a .txt file and place the ***hexadecimal*** code of your instructions simulated on ***Venus*** (RISC-V Simulator)\
+Each instruction's hexadecimal code must be on seperate line as following. This program consists of 9 instructions.
+```
+00500113
+00500193
+014000EF
+00120293
+00502023
+00002303
+00628663
+00310233
+00008067
+```
+Then perform the following step
+```ruby
+cd 5-stage-Pipelined-CPU/RV32i/src/main/scala/datapath
+```
+Open **InstructionMem.scala** with this command. You can also manually go into the above path and open the file in your favorite text editor.
+```ruby
+open InstructionMem.scala
+```
+Find the following line
+``` python
+loadMemoryFromFile(mem, "/Users/mbp/Desktop/mem1.txt")
+```
+Change the .txt file path to match your file that you created above storing your own program instructions.\
+After setting up the InstructionMem.scala file, go inside the RV32i folder.
+```ruby
+cd 5-stage-Pipelined-CPU/RV32i
+```
+And enter
+```ruby
+sbt
+```
+When the terminal changes to this type
+```ruby
+sbt:RV32i>
+```
+Enter this command
+```ruby
+sbt:RV32i> test:runMain datapath.Launcher Top
+```
+After you get success
+```ruby
+sbt:RV32i> test:runMain datapath.Launcher Top --backend-name verilator
+```
+After success you will get a folder ***test_run_dir*** on root of your folder. Go into the examples folder inside.\
+There you will find the folder named Top. Enter in it and you can find the Top.vcd file which you visualise on **gtkwave** to\
+see your program running.
diff --git a/chisel/Buraq-mini/RV32i/.gitignore b/chisel/Buraq-mini/RV32i/.gitignore
new file mode 100644
index 0000000..ebc321f
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/.gitignore
@@ -0,0 +1,42 @@
+# These are generated when we run the build
+/emulator/
+/examples/target/
+/examples/project/target/
+/hello/project/target/
+/hello/target/
+/problems/project/target/
+/problems/target/
+/solutions/project/target/
+/solutions/target/
+/generated*/
+.idea
+*.h
+*.cpp
+*.o
+*.iml
+*.im24
+*.swp
+*.out
+/bin/
+target
+
+# sbt run folder
+/test_run_dir/
+
+# Eclipse files
+.cache-main
+.cache-tests
+.classpath
+.project
+.settings/
+
+# ignore files created when viewing doc/tutorial/*.tex
+doc/tutorial/*.aux
+doc/tutorial/*.log
+doc/tutorial/*.pdf
+doc/tutorial/*.synctex.gz
+doc/tutorial/*.sty
+doc/chisel-tutorial.pdf
+doc/*.aux
+doc/*.log
+
diff --git a/chisel/Buraq-mini/RV32i/build.sbt b/chisel/Buraq-mini/RV32i/build.sbt
new file mode 100644
index 0000000..6934b03
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/build.sbt
@@ -0,0 +1,65 @@
+def scalacOptionsVersion(scalaVersion: String): Seq[String] = {
+  Seq() ++ {
+    // If we're building with Scala > 2.11, enable the compile option
+    //  switch to support our anonymous Bundle definitions:
+    //  https://github.com/scala/bug/issues/10047
+    CrossVersion.partialVersion(scalaVersion) match {
+      case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq()
+      case _ => Seq("-Xsource:2.11")
+    }
+  }
+}
+
+def javacOptionsVersion(scalaVersion: String): Seq[String] = {
+  Seq() ++ {
+    // Scala 2.12 requires Java 8. We continue to generate
+    //  Java 7 compatible code for Scala 2.11
+    //  for compatibility with old clients.
+    CrossVersion.partialVersion(scalaVersion) match {
+      case Some((2, scalaMajor: Long)) if scalaMajor < 12 =>
+        Seq("-source", "1.7", "-target", "1.7")
+      case _ =>
+        Seq("-source", "1.8", "-target", "1.8")
+    }
+  }
+}
+
+organization := "merl"
+
+version := "3.1.0"
+
+name := "RV32i"
+
+scalaVersion := "2.11.12"
+
+crossScalaVersions := Seq("2.11.12", "2.12.4")
+
+scalacOptions ++= Seq("-deprecation", "-feature", "-unchecked", "-language:reflectiveCalls")
+
+// Provide a managed dependency on X if -DXVersion="" is supplied on the command line.
+// The following are the current "release" versions.
+val defaultVersions = Map(
+  "chisel3" -> "3.3.2",
+  "chisel-iotesters" -> "1.4.2"
+  )
+
+libraryDependencies ++= (Seq("chisel3","chisel-iotesters").map {
+  dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) })
+
+resolvers ++= Seq(
+  Resolver.sonatypeRepo("snapshots"),
+  Resolver.sonatypeRepo("releases")
+)
+
+// Recommendations from http://www.scalatest.org/user_guide/using_scalatest_with_sbt
+logBuffered in Test := false
+
+// Disable parallel execution when running tests.
+//  Running tests in parallel on Jenkins currently fails.
+parallelExecution in Test := false
+
+scalacOptions ++= scalacOptionsVersion(scalaVersion.value)
+
+javacOptions ++= javacOptionsVersion(scalaVersion.value)
+
+trapExit := false
diff --git a/chisel/Buraq-mini/RV32i/doc/Makefile b/chisel/Buraq-mini/RV32i/doc/Makefile
new file mode 100644
index 0000000..c058acf
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/doc/Makefile
@@ -0,0 +1,98 @@
+# Building the docs on osx will require to install Jinja2 and BeautifulSoup:
+#     $ pip install Jinja2 BeautifulSoup
+# and the different tools for text to pdf:
+#     $ port install texlive-latex-extra texlive-latex-recommended \
+#           texlive-htmlxml ImageMagick
+#
+# For building on Ubuntu 14.04 LTS, the following packages should be
+# installed with "apt-get install":
+#  python-bs4 imagemagick source-highlight tex4ht texlive-latex-base \
+#  texlive-latex-recommended texlive-latex-extra texlive-fonts-recommended \
+#  texlive-fonts-extra
+
+PDFLATEX  := pdflatex
+WWW_PAGES :=
+WWW_EXTRA :=
+
+# The following subdirectories build documentation correctly.
+PDF_DIRS	:= tutorial
+# Define a function to map PDF_DIRS to a PDF base name.
+# Basically, every directory is the base name of the pdf except for dac12-talk.
+pdf_base_name_from_dir = $(subst talks/dac12,dac12-talk,$(1))
+# Define a map function to apply a function to multiple arguments.
+map = $(foreach arg,$(2),$(call $(1),$(arg)))
+
+PDFS := $(addsuffix .pdf,$(addprefix chisel-,$(call map,pdf_base_name_from_dir,$(PDF_DIRS))))
+
+# Suffixes for tex temporary files we'll clean
+TEX_SUFFIXES := 4ct 4tc aux css dvi html idv lg log out tmp xref
+TEX_TEMP_FILES := $(foreach dir,$(PDF_DIRS),$(foreach suffix,$(TEX_SUFFIXES),$(dir)/$(call pdf_base_name_from_dir,$(dir)).$(suffix)))
+STY_TEMP_FILES := $(foreach dir,$(PDF_DIRS),$(dir)/$(call pdf_base_name_from_dir,$(dir))_date.sty)
+
+LATEX2MAN := latex2man
+MAN_PAGES := chisel.man
+
+srcDir    := .
+installTop:= ../www
+toolDir	?= ../../chisel-doc/bin
+
+vpath %.tex $(addprefix $(srcDir)/,$(PDF_DIRS))
+
+vpath %.mtt $(addprefix $(srcDir)/,$(PDF_DIRS))
+
+all: $(WWW_PAGES) $(WWW_EXTRA) $(PDFS)
+
+extra: $(WWW_EXTRA)
+
+html: $(WWW_PAGES)
+
+pdf: $(PDFS)
+
+install: all
+
+# NOTE: We follow the recommended practice of running the *latex tools twice
+# so references (citations and figures) are correctly handled.
+# NOTE: There are problems with running pdflatex after htlatex due to the
+# manual.aux file left over by the latter. We see:
+#  ./manual.tex:113: Undefined control sequence.
+#  <argument> ...tring :autoref\endcsname {\@captype 
+#                                                    }1
+#  l.113 Figure~\ref{fig:node-hierarchy}
+# This was reported at:
+# http://tex.stackexchange.com/questions/117802/running-pdflatex-after-htlatex-causes-hyperref-error-undefined-control-sequence
+# but apparently went away after upgrading to texlive 2013.
+# It fails on ubuntu 14.04 LTS and texlive-latex-recommended 2013.20140215-1
+# if we don't remove the manual.aux file
+chisel-%.pdf: %.tex %_date.sty
+	rm -f $(subst .tex,.aux,$<)
+	cd $(dir $<) && for c in 0 1; do pdflatex -file-line-error -interaction nonstopmode -output-directory $(PWD) $(notdir $<) ; done
+	mv $(subst .tex,.pdf,$(notdir $<)) $@
+
+%.html: %.tex %_date.sty
+	cd $(dir $<) && for c in 0 1; do htlatex $(notdir $<) $(PWD)/$(srcDir)/html.cfg "" -d/$(PWD)/ ; done
+	mv $(subst .tex,.html,$(notdir $<)) $@~
+	$(toolDir)/tex2html.py $@~ $@
+
+%.man: %.mtt
+	# cd into the directory containing the .tex file and massage it
+	cd $(dir $<) && \
+	sed -e "s/@VERSION@/$(RELEASE_TAG)/" -e "s/@DATE@/$(RELEASE_DATE)/" $(notdir $<) > $(basename $@).ttex ;\
+	latex2man $(basename $@).ttex $@
+
+%.html: $(srcDir)/templates/%.html $(srcDir)/templates/base.html
+	$(toolDir)/jinja2html.py $(notdir $<) $@
+
+clean:
+	-rm -f $(TEX_TEMP_FILES)
+	-rm -f $(STY_TEMP_FILES)
+	# Remove any .{png,graffle} files that are created from pdfs
+	-rm -f $(foreach gext,png graffle,$(subst .pdf,.$(gext),$(wildcard tutorial/figs/*.pdf)))
+	-rm -f $(WWW_PAGES) $(PDFS) $(WWW_EXTRA) $(addsuffix .1,$(WWW_EXTRA)) $(patsubst %.html,%.css,$(WWW_EXTRA))
+	-rm -f *~ *.aux *.log *.nav *.out *.snm *.toc *.vrb
+	-rm -f *.jpg *.png
+
+# Generate a date (optional) for the document based on the latest
+# git commit of any of its (obvious) constituent parts.
+%_date.sty:	%.tex
+	for f in $(wildcard $(dir $<)*.tex); do git log -n 1 --format="%at" -- $$f; done | sort -nr | head -1 | gawk '{print "\\date{",strftime("%B %e, %Y", $$1),"}"}' > $@
+	cmp $@ $(dir $<)$@ || cp $@ $(dir $<)
diff --git a/chisel/Buraq-mini/RV32i/doc/html.cfg b/chisel/Buraq-mini/RV32i/doc/html.cfg
new file mode 100644
index 0000000..6951fde
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/doc/html.cfg
@@ -0,0 +1,9 @@
+\Preamble{xhtml}
+  \Configure{graphics*}  
+         {pdf}  
+         {\Needs{"convert \csname Gin@base\endcsname.pdf  
+                               \csname Gin@base\endcsname.png"}%  
+          \Picture[pict]{\csname Gin@base\endcsname.png}%  
+         }  
+\begin{document}
+\EndPreamble
diff --git a/chisel/Buraq-mini/RV32i/doc/images/Buraq-mini SoC.png b/chisel/Buraq-mini/RV32i/doc/images/Buraq-mini SoC.png
new file mode 100644
index 0000000..da94600
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/doc/images/Buraq-mini SoC.png
Binary files differ
diff --git a/chisel/Buraq-mini/RV32i/doc/images/fig2.1.png b/chisel/Buraq-mini/RV32i/doc/images/fig2.1.png
new file mode 100644
index 0000000..01810a9
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/doc/images/fig2.1.png
Binary files differ
diff --git a/chisel/Buraq-mini/RV32i/doc/images/fig2.2.png b/chisel/Buraq-mini/RV32i/doc/images/fig2.2.png
new file mode 100644
index 0000000..1b221e7
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/doc/images/fig2.2.png
Binary files differ
diff --git a/chisel/Buraq-mini/RV32i/doc/images/fig2.3.png b/chisel/Buraq-mini/RV32i/doc/images/fig2.3.png
new file mode 100644
index 0000000..16057bd
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Binary files differ
diff --git a/chisel/Buraq-mini/RV32i/doc/images/fig2.4.png b/chisel/Buraq-mini/RV32i/doc/images/fig2.4.png
new file mode 100644
index 0000000..56df054
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+++ b/chisel/Buraq-mini/RV32i/doc/images/fig2.4.png
Binary files differ
diff --git a/chisel/Buraq-mini/RV32i/doc/images/fig2.5.png b/chisel/Buraq-mini/RV32i/doc/images/fig2.5.png
new file mode 100644
index 0000000..e5177e4
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/doc/images/fig2.5.png
Binary files differ
diff --git a/chisel/Buraq-mini/RV32i/doc/images/fig2.6.png b/chisel/Buraq-mini/RV32i/doc/images/fig2.6.png
new file mode 100644
index 0000000..e3ce836
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/doc/images/fig2.6.png
Binary files differ
diff --git a/chisel/Buraq-mini/RV32i/doc/style/scala.tex b/chisel/Buraq-mini/RV32i/doc/style/scala.tex
new file mode 100644
index 0000000..26299e9
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/doc/style/scala.tex
@@ -0,0 +1,64 @@
+% "define" Scala
+\usepackage[T1]{fontenc}  
+\usepackage[scaled=0.82]{beramono}  
+\usepackage{microtype} 
+
+\sbox0{\small\ttfamily A}
+\edef\mybasewidth{\the\wd0 }
+
+\lstdefinelanguage{scala}{
+  morekeywords={abstract,case,catch,class,def,%
+    do,else,extends,false,final,finally,%
+    for,if,implicit,import,match,mixin,%
+    new,null,object,override,package,%
+    private,protected,requires,return,sealed,%
+    super,this,throw,trait,true,try,%
+    type,val,var,while,with,yield},
+  sensitive=true,
+  morecomment=[l]{//},
+  morecomment=[n]{/*}{*/},
+  morestring=[b]",
+  morestring=[b]',
+  morestring=[b]"""
+}
+
+\usepackage{color}
+\definecolor{dkgreen}{rgb}{0,0.6,0}
+\definecolor{gray}{rgb}{0.5,0.5,0.5}
+\definecolor{mauve}{rgb}{0.58,0,0.82}
+
+% Default settings for code listings
+\lstset{frame=tb,
+  language=scala,
+  aboveskip=3mm,
+  belowskip=3mm,
+  showstringspaces=false,
+  columns=fixed, % basewidth=\mybasewidth,
+  basicstyle={\small\ttfamily},
+  numbers=none,
+  numberstyle=\footnotesize\color{gray},
+  % identifierstyle=\color{red},
+  keywordstyle=\color{blue},
+  commentstyle=\color{dkgreen},
+  stringstyle=\color{mauve},
+  frame=single,
+  breaklines=true,
+  breakatwhitespace=true,
+  procnamekeys={def, val, var, class, trait, object, extends},
+  procnamestyle=\ttfamily\color{red},
+  tabsize=2
+}
+
+\lstnewenvironment{scala}[1][]
+{\lstset{language=scala,#1}}
+{}
+\lstnewenvironment{cpp}[1][]
+{\lstset{language=C++,#1}}
+{}
+\lstnewenvironment{bash}[1][]
+{\lstset{language=bash,#1}}
+{}
+\lstnewenvironment{verilog}[1][]
+{\lstset{language=verilog,#1}}
+{}
+
diff --git a/chisel/Buraq-mini/RV32i/doc/style/talk.tex b/chisel/Buraq-mini/RV32i/doc/style/talk.tex
new file mode 100644
index 0000000..1958495
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/doc/style/talk.tex
@@ -0,0 +1,38 @@
+\lstset{basicstyle={\footnotesize\ttfamily}}
+
+\usetheme[height=8mm]{Rochester}
+\setbeamersize{text margin left=3mm} 
+\setbeamersize{text margin right=3mm} 
+\setbeamertemplate{navigation symbols}{}
+
+\definecolor{Cobalt}{rgb}{0.25,0.125,0.70}
+\definecolor{RedOrange}{rgb}{0.8,0.25,0.0}
+% \definecolor{RedOrange}{rgb}{0.8,0.775,0.25}
+\def\frametitledefaultcolor{Cobalt}
+\def\frametitleproblemcolor{RedOrange}
+
+\lstset{basicstyle={\footnotesize\ttfamily}}
+
+\setbeamertemplate{frametitle}
+{
+\vskip-7mm
+\textbf{\insertframetitle}\hfill\insertframenumber
+}
+\setbeamercolor{frametitle}{bg=\frametitledefaultcolor}
+
+\newenvironment{sample}{\VerbatimEnvironment\begin{footnotesize}\begin{semiverbatim}}{\end{semiverbatim}\end{footnotesize}}
+
+\newenvironment{FramedSemiVerb}%
+{\begin{Sbox}\begin{minipage}{.94\textwidth}\begin{semiverbatim}}%
+{\end{semiverbatim}\end{minipage}\end{Sbox}
+\setlength{\fboxsep}{8pt}\fbox{\TheSbox}}
+
+\newenvironment{FramedVerb}%
+{\VerbatimEnvironment
+\begin{Sbox}\begin{minipage}{.94\textwidth}\begin{Verbatim}}%
+{\end{Verbatim}\end{minipage}\end{Sbox}
+\setlength{\fboxsep}{8pt}\fbox{\TheSbox}}
+
+% \newenvironment{sample}{\VerbatimEnvironment\begin{footnotesize}\begin{Verbatim}}{\end{Verbatim}\end{footnotesize}}
+\newcommand{\code}[1]{\begin{footnotesize}{\tt #1}\end{footnotesize}}
+\newcommand{\comment}[1]{{\color{Green}\it\smaller #1}}
diff --git a/chisel/Buraq-mini/RV32i/doc/tutorial/figs/DUT.pdf b/chisel/Buraq-mini/RV32i/doc/tutorial/figs/DUT.pdf
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diff --git a/chisel/Buraq-mini/RV32i/doc/tutorial/retreat-talk.tex b/chisel/Buraq-mini/RV32i/doc/tutorial/retreat-talk.tex
new file mode 100644
index 0000000..3c59131
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/doc/tutorial/retreat-talk.tex
@@ -0,0 +1,1067 @@
+\documentclass[xcolor=pdflatex,dvipsnames,table]{beamer}
+\usepackage{epsfig,graphicx}
+\usepackage{palatino}
+\usepackage{fancybox}
+\usepackage{relsize}
+\usepackage[procnames]{listings}
+\usepackage{array}
+
+\input{../style/scala.tex}
+\input{../style/talk.tex}
+
+\title[Chisel]{Chisel: Constructing Hardware In a Scala Embedded Language}
+\author[Bachrach et al]{Jonathan Bachrach, Huy Vo, Brian Richards, \\
+Yunsup Lee, Andrew Waterman, Rimas Avizienis, Henry Cook, \\
+John Wawrzynek, Krste Asanovic}
+\date{\today}
+\institute[parlab]{EECS UC Berkeley}
+
+\begin{document}
+
+{
+\setbeamertemplate{footline}{} 
+\begin{frame}
+  \titlepage
+\end{frame}
+}
+\addtocounter{framenumber}{-1}
+
+\begin{frame}[fragile]
+\frametitle{21st Century Architecture Design}
+{\Large\textbf{Harder to get hardware / software efficiency gains}}
+\vskip5mm
+\begin{itemize}
+\item Need massive design-space exploration
+\begin{itemize}
+\item Hardware and software codesign and cotuning
+\end{itemize}
+\item Need meaningful results
+\begin{itemize}
+\item Cycle counts
+\item Cycle time, power and area
+\item Real chips
+\end{itemize}
+\item Traditional architectural simulators, hardware-description
+  languages, and tools are inadequate
+\begin{itemize}
+\item Slow
+\item Inaccurate
+\item Error prone
+\item Difficult to modify and parameterize
+\end{itemize}
+\end{itemize}
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Bottom Line -- Shorten Design Loop}
+{\LARGE\textbf{Make it}}
+\vskip2mm
+\begin{itemize}
+\item Easier to make design changes
+\begin{itemize}
+\item Fewer lines of design code ( \textbf{>> 3x} )
+\item More reusable code
+\item Parameterize designs
+\end{itemize}
+\item Faster to test results ( \textbf{>> 8x} )
+\begin{itemize}
+\item Fast compilation
+\item Fast simulation
+\item Easy testing
+\item Easy verification
+\end{itemize}
+\end{itemize}
+\vskip0.8cm
+{\LARGE\textbf{Result}}
+\begin{itemize}
+\item Explore more design space
+\end{itemize}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Chisel is ...}
+
+\begin{columns}[c]
+
+\column{0.55\textwidth}
+
+\begin{itemize}
+\item Best of hardware and software design ideas
+\item Embedded within Scala language to leverage mindshare and language design
+\item Algebraic construction and wiring
+\item Hierarchical, object oriented, and functional construction
+\item Abstract data types and interfaces
+\item Bulk connections
+\item Multiple targets
+\begin{itemize}
+\item Simulation and synthesis
+\item Memory IP is target-specific
+\end{itemize}
+\end{itemize}
+
+\column{0.40\textwidth}
+
+\begin{center}
+single source \\
+\includegraphics[width=0.99\textwidth]{../manual/figs/targets.pdf} \\
+multiple targets \\
+\end{center}
+
+\end{columns}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{The Scala Programming Language}
+
+\begin{columns}[c]
+
+\column{0.75\textwidth}
+
+\begin{itemize}
+\item Compiled to JVM
+\begin{itemize}
+\item Good performance
+\item Great Java interoperability
+\item Mature debugging, execution environments
+\end{itemize}
+\item Object Oriented
+\begin{itemize}
+\item Factory Objects, Classes
+\item Traits, overloading etc
+\end{itemize}
+\item Functional
+\begin{itemize}
+\item Higher order functions
+\item Anonymous functions
+\item Currying etc
+\end{itemize}
+\item Extensible
+\begin{itemize}
+\item Domain Specific Languages (DSLs)
+\end{itemize}
+\end{itemize}
+
+\column{0.25\textwidth}
+
+\begin{center}
+\includegraphics[height=0.4\textheight]{figs/programming-scala.pdf} \\
+\includegraphics[height=0.4\textheight]{figs/programming-in-scala.pdf}
+\end{center}
+
+\end{columns}
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Algebraic Graph Construction}
+
+\begin{columns}
+\column{0.35\textwidth}
+{\lstset{basicstyle={\Large\ttfamily}}
+\begin{scala}
+Mux(x > y, x, y)
+\end{scala}
+}
+
+\column{0.6\textwidth}
+
+\begin{center}
+\includegraphics[width=0.9\textwidth]{figs/max2.pdf} 
+\end{center}
+\end{columns}
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Creating Component}
+
+\begin{columns}
+\column{0.45\textwidth}
+
+{\lstset{basicstyle={\scriptsize\ttfamily}}
+\begin{scala}
+class Max2 extends Component {
+  val io = new Bundle {
+    val x = UFix(width = 8).asInput
+    val y = UFix(width = 8).asInput
+    val z = UFix(width = 8).asOutput }
+  io.z := Mux(io.x > io.y, io.x, io.y)
+}
+\end{scala}
+}
+
+\column{0.45\textwidth}
+\begin{center}
+\includegraphics[width=0.95\textwidth]{figs/Max2c.pdf} \\
+\end{center}
+\end{columns}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Connecting Components}
+
+\begin{columns}
+\column{0.25\textwidth}
+\begin{scala}
+val m1 = new Max2()
+m1.io.x := a
+m1.io.y := b
+val m2 = new Max2()
+m2.io.x := c
+m2.io.y := d
+val m3 = new Max2()
+m3.io.x := m1.io.z
+m3.io.y := m2.io.z
+\end{scala}
+
+\column{0.7\textwidth}
+
+\begin{center}
+\includegraphics[width=0.99\textwidth]{figs/Max4.pdf} \\
+\end{center}
+\end{columns}
+
+\end{frame}
+
+
+\begin{frame}[fragile]
+\frametitle{Defining Construction Functions}
+
+\begin{columns}
+
+\column{0.45\textwidth}
+
+\begin{scala}
+def Max2 = Mux(x > y, x, y)
+\end{scala}
+\begin{scala}
+Max2(x, y)
+\end{scala}
+
+\column{0.5\textwidth}
+
+\begin{center}
+\includegraphics[width=0.95\textwidth]{figs/Max2.pdf} \\[1cm]
+\end{center}
+
+\end{columns}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Functional Construction}
+
+\begin{columns}
+
+\column{0.45\textwidth}
+
+\begin{scala}
+Reduce(Array(a, b, c, d), Max2)
+\end{scala}
+
+\column{0.5\textwidth}
+
+\begin{center}
+\includegraphics[width=0.99\textwidth]{figs/reduceMax.pdf} \\
+\end{center}
+
+\end{columns}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Example}
+\begin{columns}
+
+\column{0.45\textwidth}
+
+\begin{footnotesize}
+\begin{scala}
+class GCD extends Component {
+  val io = new Bundle {
+    val a     = UFix(INPUT, 16)
+    val b     = UFix(INPUT, 16)
+    val z     = UFix(OUTPUT, 16)
+    val valid = Bool(OUTPUT) }
+  val x = Reg(resetVal = io.a)
+  val y = Reg(resetVal = io.b)
+  when (x > y) {
+    x := x - y
+  } .otherwise {
+    y := y - x
+  }
+  io.z     := x
+  io.valid := y === UFix(0)
+}
+\end{scala}
+\end{footnotesize}
+
+\column{0.45\textwidth}
+
+\begin{center}
+\includegraphics[width=0.9\textwidth]{figs/gcd.pdf} 
+\end{center}
+
+\end{columns}
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Primitive Datatypes}
+\begin{itemize}
+\item{Chisel has 4 primitive datatypes}
+\begin{description}
+\item[Bits]  -- raw collection of bits
+\item[Fix]   -- signed fixed-point number
+\item[UFix] -- unsigned fixed-point number
+\item[Bool] -- Boolean value
+\end{description}
+\item Can do arithmetic and logic with these datatypes
+\end{itemize}
+
+\textbf{Example Literal Constructions}
+\begin{scala}
+val sel = Bool(false)
+val a   = UFix(25)
+val b   = Fix(-35)
+\end{scala}
+where \verb+val+ is a Scala keyword used to declare variables whose values won't change
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Aggregate Data Types}
+
+\textbf{Bundle}
+
+\begin{itemize}
+\item User-extensible collection of values with named fields
+\item Similar to structs
+\end{itemize}
+
+\begin{footnotesize}
+% \textbf{Bundle Example}
+\begin{scala}
+class MyFloat extends Bundle{
+  val sign        = Bool()
+  val exponent    = UFix(width=8)
+  val significand = UFix(width=23)
+}
+\end{scala}
+\end{footnotesize}
+
+\textbf{Vec}
+
+\begin{itemize}
+\item Create indexable collection of values
+\item Similar to arrays
+\end{itemize}
+
+\begin{footnotesize}
+% \textbf{Vec Example}
+\begin{scala}
+val myVec = Vec(5){ Fix(width=23) }
+\end{scala}
+\end{footnotesize}
+
+\end{frame}
+
+
+\begin{frame}[fragile]
+\frametitle{Abstract Data Types}
+\begin{itemize}
+\item The user can construct new data types
+\begin{itemize}
+\item Allows for compact, readable code
+\end{itemize}
+\item Example: Complex numbers
+\begin{itemize}
+\item Useful for FFT, Correlator, other DSP
+\item Define arithmetic on complex numbers
+\end{itemize}
+\end{itemize}
+
+\begin{footnotesize}
+\begin{scala}
+class Complex(val real: Fix, val imag: Fix) 
+    extends Bundle {
+  def + (b: Complex): Complex = 
+    new Complex(real + b.real, imag + b.imag)
+  ...
+}
+val a = new Complex(Fix(32), Fix(-16))
+val b = new Complex(Fix(-15), Fix(21))
+val c = a + b
+\end{scala}
+\end{footnotesize}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Polymorphism and Parameterization}
+\begin{itemize}
+\item Chisel users can define their own parameterized functions
+\begin{itemize}
+\item Parameterization encourages reusability
+\item Data types can be inferred and propagated
+\end{itemize}
+\end{itemize}
+
+\textbf{Example Shift Register:}
+\begin{scala}
+def delay[T <: Data](x: T, n: Int): T = 
+  if(n == 0) x else Reg(delay(x, n - 1))
+\end{scala}
+where
+\begin{itemize}
+\item The input \verb+x+ is delayed n cycles
+\item \verb+x+ can by of any type that extends from \verb+Data+
+\end{itemize}
+
+\end{frame}
+
+\begin{frame}[fragile, shrink]
+\frametitle{Functional Composition}
+
+% \begin{itemize}
+% \item natural
+% \item reusable
+% \item composable
+% \end{itemize}
+% \vskip1cm
+
+\begin{Large}
+\begin{columns}
+
+\column{0.45\textwidth}
+\verb+Map(ins, x => x * y)+ \\
+\begin{center}
+\includegraphics[height=0.6\textheight]{figs/map.pdf} \\[2cm]
+\end{center}
+
+\column{0.45\textwidth}
+\verb+Chain(n, in, x => f(x))+ \\
+\begin{center}
+\includegraphics[width=0.9\textwidth]{figs/chain.pdf} \\
+\end{center}
+
+\verb+Reduce(data, Max)+ \\
+\begin{center}
+\includegraphics[width=0.9\textwidth]{figs/reduce.pdf} \\
+\end{center}
+
+
+\end{columns}
+
+\end{Large}
+
+\end{frame}
+
+% \begin{frame}[fragile, shrink]
+% \frametitle{Chain}
+% 
+% \begin{columns}
+% 
+% \column{0.6\textwidth}
+% 
+% \begin{scala}
+% def Chain[T <: Data]
+%       (n: Int, in: T, f: T => T): T = {
+%   if (n == 1)
+%     in
+%   else 
+%    chain(n-1, f(in), f)
+% }
+% \end{scala}
+% usage:
+% \begin{scala}
+% Chain(n, in, x => x + x)
+% \end{scala}
+% 
+% \column{0.3\textwidth}
+% 
+% \begin{center}
+% \includegraphics[width=0.9\textwidth]{figs/chain.pdf} \\
+% \end{center}
+% 
+% \end{columns}
+% \end{frame}
+% 
+% \begin{frame}[fragile, shrink]
+% \frametitle{Map}
+% 
+% \begin{columns}
+% 
+% \column{0.6\textwidth}
+% 
+% \begin{scala}
+% def Map[S <: Data, T <: Data]
+%       (ins: Seq[T], f: S => T): T
+% \end{scala}
+% usage:
+% \begin{scala}
+% Map(ins, h => Reg(h * Reg(x)))
+% \end{scala}
+%  
+% \column{0.3\textwidth}
+% 
+% \begin{center}
+% \includegraphics[height=0.7\textheight]{figs/map.pdf} \\
+% \end{center}
+% 
+% \end{columns}
+% \end{frame}
+%  
+% \begin{frame}[fragile, shrink]{Reduce}
+% 
+% \begin{columns}
+% 
+% \column{0.6\textwidth}
+% 
+% \begin{scala}
+% def Reduce[T <: Data]
+%       (ins: Seq[T], f: (T, T) => T): T = {
+%   val len = ins.length
+%   if (len == 1)
+%     ins(0)
+%   else 
+%     f(Reduce(in.slice(0, len/2),   f), 
+%       Reduce(in.slice(len/2, len), f))
+% }
+% \end{scala}
+% usage:
+% \begin{scala}
+% def Max[T <: Num](x: T, y: T) = 
+%   Mux(x > y, x, y)
+% Reduce(data, Max)
+% \end{scala}
+% 
+% \column{0.3\textwidth}
+% 
+% \begin{center}
+% \includegraphics[width=0.9\textwidth]{figs/Reduce.pdf} \\
+% \end{center}
+% 
+% \end{columns}
+% 
+% \end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Generator}
+\begin{footnotesize}
+\begin{scala}
+class Cache(cache_type:    Int = DIR_MAPPED,
+            associativity: Int = 1,
+            line_size:     Int = 128,
+            cache_depth:   Int = 16,
+            write_policy:  Int = WRITE_THRU
+           ) extends Component {
+  val io = new Bundle() {
+    val cpu = new IoCacheToCPU()
+    val mem = new IoCacheToMem().flip()
+  }
+  val addr_idx_width = log2(cache_depth).toInt
+  val addr_off_width = log2(line_size/32).toInt
+  val addr_tag_width = 32 - addr_idx_width - addr_off_width - 2
+  val log2_assoc     = log2(associativity).toInt
+  ...
+  if (cache_type == DIR_MAPPED)
+    ...
+\end{scala}
+\end{footnotesize}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{State Elements}
+
+Simplest element is positive edge triggered register:
+\begin{scala}
+val prev_in = Reg(in)
+\end{scala}
+Can assign data input later using wiring
+\begin{scala}
+val pc = Reg(){ UFix(width = 16) }
+pc := pc + UFix(1, 16)
+\end{scala}
+Can quickly define more useful circuits
+\begin{scala}
+def risingEdge(x: Bool) = x && !Reg(x)
+\end{scala}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Conditional Updates}
+
+\begin{columns}
+
+\column{0.45\textwidth}
+
+Convenient to specify updates spread across several statements
+\begin{scala}
+val r = Reg() { UFix(width = 16) } 
+when (c === UFix(0)) {
+  r := r + UFix(1)
+}
+\end{scala}
+or
+{\lstset{frame=shadowbox}
+\begin{scala}
+when (c1) { r := e1 } 
+when (c2) { r := e2 }
+\end{scala}
+}
+
+\column{0.45\textwidth}
+
+\shadowbox{
+\includegraphics[width=0.95\textwidth]{figs/condupdates.pdf} }
+
+\end{columns}
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Composition of Conditional Updates}
+
+Nesting
+\begin{scala}
+when (a) { when (b) { body } }
+\end{scala}
+Chaining
+\begin{scala}
+when (c1) { u1 }
+.elsewhen (c2) { u2 }
+.otherwise { ud }
+\end{scala}
+Dynamic Scoping
+\begin{scala}
+def condUpdateR (c: Bool, d: Data) = when (c) { r := d }
+\end{scala}
+\begin{scala}
+when (a) { condUpdateR(b, x) }
+\end{scala}
+\begin{scala}
+when (a) { when (b) { r := x } }
+\end{scala}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Symmetry of Conditional Updates}
+
+Regs and Wires
+\begin{scala}
+x := init
+when (isEnable) {
+  x := data
+}
+\end{scala}
+ 
+Vecs and Mems
+\begin{scala}
+when (isEnable) {
+  m(addr) := data
+}
+\end{scala}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Object Oriented Conditional Updates}
+
+% \begin{scala}
+% class DecoupledIO[T <: Data]()(gen: => T) extends Bundle {
+%   val valid = Bool(dir = OUTPUT)
+%   val ready = Bool(dir = INPUT)
+%   val data  = gen.asOutput
+% }
+% 
+% class EnqIO[T <: Data]()(gen: => T) extends DecoupledIO[T]()(gen) {
+%   def enq(dat: T): T = { valid := Bool(true); data := dat; dat }
+%   valid := Bool(false)
+% }
+% 
+% class Packet extends Bundle {
+%   val header = UFix(width = 8)
+%   val body   = Bits(width = 64)
+% }
+% \end{scala}
+% 
+% example:
+
+\begin{columns}
+\column{0.57\textwidth}
+
+{\lstset{basicstyle={\scriptsize\ttfamily}}
+\begin{scala}
+val in  = (new DeqIo()){ new Packet() }
+val out = (new EnqIo()){ new Packet() }
+when (in.valid && out.ready) {
+  out.enq(filter(in.deq()))
+}
+\end{scala}
+
+\vskip5mm
+
+\begin{scala}
+val in   = (new DeqIo()){ new Packet() }
+val outs = Vec(4){ new EnqIo()){ new Packet() } }
+val tbl  = Mem(4){ UFix(width = 2) }
+when (in.valid) {
+  val k = tbl(in.data.header)
+  when (outs(k).ready) {
+    outs(k).enq(in.deq())
+  }
+}
+\end{scala}
+}
+
+\column{0.38\textwidth}
+
+\includegraphics[width=0.99\textwidth]{figs/filter.pdf} \\[20mm]
+\includegraphics[width=0.99\textwidth]{figs/router.pdf} 
+
+\end{columns}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Component Testing}
+
+% \begin{itemize}
+% \item write tests in Scala
+% \item bind values using dot notation
+% \end{itemize}
+
+\begin{columns}
+\column{0.45\textwidth}
+
+{\lstset{basicstyle={\scriptsize\ttfamily}}
+\begin{scala}
+class Mux2IO extends Bundle {
+  val sel = Bits(width = 1).asInput
+  val in0 = Bits(width = 1).asInput
+  val in1 = Bits(width = 1).asInput
+  val out = Bits(width = 1).asOutput
+}
+\end{scala}
+}
+\begin{center}
+\includegraphics[width=0.9\textwidth]{figs/mux2.pdf} 
+\end{center}
+
+\column{0.5\textwidth}
+{\lstset{basicstyle={\scriptsize\ttfamily}}
+\begin{scala}
+class Mux2Tests extends Iterator[Mux2IO] { 
+  var i = 0
+  val n = pow(2, 3)
+  def hasNext = i < n
+  def next = { 
+    val io  = new Mux2IO
+    val k   = Bits(i, width = log2up(n))
+    io.sel := k(0)
+    io.in0 := k(1)
+    io.in1 := k(2)
+    io.out := Mux(k(0), k(1), k(2))
+    i      += 1
+    io
+  }
+}
+\end{scala}
+}
+
+\end{columns}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Chisel Line Count Breakdown}
+
+\begin{columns}
+
+\column{0.3\textwidth}
+
+\begin{itemize}
+\item \verb+~+5200 lines total
+\item Embeds into Scala well
+\end{itemize}
+
+\column{0.7\textwidth}
+
+\begin{center}
+\includegraphics[width=0.9\textwidth]{figs/linecount.png}
+\end{center}
+
+\end{columns}
+
+\end{frame}
+
+\begin{frame}
+\frametitle {Chisel versus Hand-Coded Verilog}
+
+\begin{itemize}
+\item 3-stage RISCV CPU hand-coded in Verilog
+\item Translated to Chisel
+\item Resulted in 3x reduction in lines of code
+\item Most savings in wiring
+\item Lots more savings to go ...
+% \item Chisel-generated Verilog gives comparable synthesis quality of results
+\end{itemize}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Process Language}
+
+\begin{columns}
+
+\column{0.5\textwidth}
+
+Composeable State Machines
+\begin{scala}
+Do{ ... }
+Exec(c){ a } / Exec{ a }
+Stop
+Skip / Wait(n)
+Seq(a, ...)
+Par(a, ...)
+Alt(c, a1, a2)
+While(c){ a } / Loop{ a }
+\end{scala}
+
+Each process block uses a \verb+when+
+\begin{scala}
+when (io.start) { ... }
+\end{scala}
+to ensure that state updates are updated only when process execute.
+
+\column{0.45\textwidth}
+
+\begin{center}
+\includegraphics[width=0.9\textwidth]{figs/process.pdf} \\
+\end{center}
+
+\end{columns}
+
+\end{frame}
+
+\begin{frame}[fragile, shrink]
+\frametitle{Process Language Example}
+
+\begin{scala}
+class Multiply extends Component {
+  val io = new Bundle{ 
+    val start  = Bool(INPUT);
+    val x      = UFix(dir = INPUT, width = 32)
+    val y      = UFix(dir = INPUT, width = 32)
+    val z      = UFix(dir = OUTPUT, width = 32)
+    val finish = Bool(OUTPUT) }
+  val a   = Reg(){ UFix(0, 32) }
+  val b   = Reg(){ UFix(0, 32) }
+  val acc = Reg(){ UFix(0, 32) }
+  val finish =
+    Exec(io.start) {
+      Seq(Do{ a := io.x; b := io.y; acc := UFix(0, 32) },
+          While(b != UFix(0, 32)) {
+            Do{ a   := (a << UFix(1)) 
+                b   := (b >> UFix(1))
+                acc := Mux(b(0) === Bits(1), acc+a, acc) } })
+    }
+  io.finish  := finish
+  io.z       := acc
+}
+\end{scala}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Transactors and Beyond}
+\begin{columns}
+\column{0.53\textwidth}
+{\lstset{basicstyle={\scriptsize\ttfamily}}
+\begin{scala}
+class Router extends Transactor {
+  val n   = 2
+  val io  = new RouterIO(n)
+  val tbl = Mem(32){ UFix(width = sizeof(n)) }
+  defRule("rd") { 
+    val cmd = io.reads.deq()  
+    io.replies.enq(tbl.read(cmd.addr)) 
+  }
+  defRule("wr") { 
+    val cmd = io.writes.deq()
+    tbl.write(cmd.addr, cmd.data) 
+  }
+  defRule("rt") { 
+    val pkt = io.in.deq()
+    io.outs(tbl.read(pkt.header)).enq(pkt) 
+  }
+}
+\end{scala}
+}
+\column{0.42\textwidth}
+\includegraphics[width=0.99\textwidth]{figs/trouter.pdf} 
+\end{columns}
+
+\end{frame}
+
+% \begin{frame}{Related Work}
+% 
+% \begin{itemize}
+% \item SystemVerilog
+% \begin{itemize}
+% \item Lacks general purpose programming and extensibility
+% \end{itemize}
+% \item Lava
+% \begin{itemize}
+% \item Elegant but focus on spatial layout
+% \end{itemize}
+% \item Domain specific (bluespec + esterel + autoesl)
+% \begin{itemize}
+% \item Powerful but needs to match task at hand	
+% \end{itemize}
+% \item Generator language (Genesis2 + spiralFFT)
+% \begin{itemize}
+% \item Either inherit poor abstraction qualities of underlying HDL or
+% \item Do not provide complete solution
+% \end{itemize}
+% \end{itemize}
+% 
+% \end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Rocket Microarchitecture}
+\begin{itemize}
+\item 6-stage RISC decoupled integer datapath + 5-stage IEEE FPU + MMU
+  and non-blocking caches
+\item Completely written in Chisel
+\end{itemize}
+\includegraphics[width=\textwidth]{figs/rocket-microarchitecture.pdf}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Single Source / Multiple Targets}
+
+\begin{center}
+single source \\
+\includegraphics[width=0.95\textwidth]{../manual/figs/targets.pdf} \\
+multiple targets \
+\end{center}
+
+\end{frame}
+
+
+\begin{frame}[fragile]
+\frametitle{Fast Cycle-Accurate Simulation in C++}
+
+\begin{itemize}
+\item Compiles to single class 
+\begin{itemize}
+\item Keep state and top level io in class fields
+\item \verb+clock_lo+ and \verb+clock_hi+ methods
+\end{itemize}
+\item Generates calls to fast multiword library using C++ templates 
+\begin{itemize}
+\item specializing for small word cases
+\item remove branching as much as possible to utilize maximum ILP in processor
+\end{itemize}
+\end{itemize}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Simulator Comparison}
+
+\textbf{Comparison of simulation time when booting Tessellation OS}
+\vskip0.5cm
+
+\begin{footnotesize}
+\begin{tabular}{lrrrrrr}
+\textbf{Simulator} & \textbf{Compile}  & \textbf{Compile} & \textbf{Run}  & \textbf{Run} & \textbf{Total} & \textbf{Total} \\
+& \textbf{Time (s)}  & \textbf{Speedup} & \textbf{Time (s)}  & \textbf{Speedup} & \textbf{Time (s)} & \textbf{Speedup} \\
+\hline
+VCS             &   22 & 1.000 & 5368 & 1.00 & 5390 & 1.00 \\ 
+Chisel C++  & 119 & 0.184 & 575 & 9.33 & 694 & 7.77\\
+Virtex-6 & 3660 & 0.006 & 76 & 70.60 & 3736 & 1.44\\
+\end{tabular}
+\end{footnotesize}
+
+
+\end{frame}
+
+\begin{frame}
+\frametitle{Simulation Crossover Points}
+
+% \begin{columns}
+% \begin{tabular}{ll}
+% \textbf{Simulation} & \textbf{Worth it if ...} \\
+% \hline
+% Chisel C++ & millions of cycles \\
+% FPGA & billions of cycles \\
+% \end{tabular}
+% 
+% \column{0.55\textwidth}
+
+\begin{center}
+\includegraphics[height=0.8\textheight]{figs/perf.pdf}
+\end{center}
+
+% \end{columns}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Data Parallel Processor Tape Out Results}
+
+\begin{center}
+Completely written in Chisel
+\includegraphics[height=0.7\textheight]{figs/ibm45.png}
+
+\begin{footnotesize}
+The data-parallel processor layout results using IBM 45nm SOI 10-metal layer process using memory compiler generated 6T and 8T SRAM blocks.
+\end{footnotesize}
+\end{center}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Products}
+
+\begin{itemize}
+\item Open source with BSD license
+\begin{itemize}
+\item \verb+chisel.eecs.berkeley.edu+
+\item complete set of documentation
+\item bootcamp / release june 8, 2012
+\end{itemize}
+\item Library of components
+\begin{itemize}
+\item queues, decoders, encoders, popcount, scoreboards, integer ALUs, LFSR, Booth multiplier, iterative divider, ROMs, RAMs, CAMs, TLB, caches, prefetcher, fixed-priority arbiters, round-robin arbiters, IEEE-754/2008 floating-point units
+\end{itemize}
+\item Set of educational processors including:
+\begin{itemize}
+\item microcoded processor, one-stage, two-stage, and five-stage pipelines, and an out-of-order processor, all with accompanying visualizations.
+\end{itemize}
+\end{itemize}
+
+\end{frame}
+
+\begin{frame}[fragile]
+\frametitle{Future}
+
+\begin{itemize}
+\item Automated design space exploration
+\item Insertion of activity counters for power monitors
+\item Automatic fault insertion
+\item Faster and more scalable simulation
+\item More generators
+\item More little languages
+\item Compilation to UCLID
+\end{itemize}
+
+\end{frame}
+
+
+\end{document}
diff --git a/chisel/Buraq-mini/RV32i/doc/tutorial/tutorial-2.tex b/chisel/Buraq-mini/RV32i/doc/tutorial/tutorial-2.tex
new file mode 100644
index 0000000..7e0200e
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/doc/tutorial/tutorial-2.tex
@@ -0,0 +1,2097 @@
+\documentclass[twocolumn,10pt]{article}
+\setlength\textwidth{6.875in}
+\setlength\textheight{8.875in}
+% set both margins to 2.5 pc
+\setlength{\oddsidemargin}{-0.1875in}% 1 - (8.5 - 6.875)/2
+\setlength{\evensidemargin}{-0.1875in}
+\setlength{\marginparwidth}{0pc}
+\setlength{\marginparsep}{0pc}%
+\setlength{\topmargin}{0in} \setlength{\headheight}{0pt}
+\setlength{\headsep}{0pt}
+\setlength{\footskip}{37pt}%
+%\setlength{\columnsep}{0.3125in}
+%\setlength{\columnwidth}{3.28125in}% (6.875 - 0.3125)/2 = 3.28125in
+\setlength{\parindent}{1pc}
+\newcommand{\myMargin}{1.00in}
+\usepackage[top=\myMargin, left=\myMargin, right=\myMargin, bottom=\myMargin, nohead]{geometry}
+\usepackage{epsfig,graphicx}
+\usepackage{palatino}
+\usepackage{fancybox}
+\usepackage{url}
+\usepackage[procnames]{listings}
+
+\input{../style/scala.tex}
+
+\lstset{frame=, basicstyle={\footnotesize\ttfamily}}
+
+\newcommand{\todo}[1]{\emph{TODO: #1}}
+\newcommand{\comment}[1]{\emph{Comment: #1}}
+
+% uncomment following for final submission
+\renewcommand{\todo}[1]{}
+\renewcommand{\comment}[1]{}
+
+\newenvironment{commentary}
+{ \vspace{-0.1in}
+  \begin{quotation}
+  \noindent
+  \small \em
+  \rule{\linewidth}{1pt}\\
+}
+{
+  \end{quotation}
+}
+
+% \newenvironment{kode}%
+% {\footnotesize
+%  %\setlength{\parskip}{0pt}
+%   %\setlength{\topsep}{0pt}
+%   %\setlength{\partopsep}{0pt}
+%  \verbatim}
+% {\endverbatim 
+% %\vspace*{-0.1in}
+%  }
+
+% \newenvironment{kode}%
+% {\VerbatimEnvironment
+% \footnotesize\begin{Sbox}\begin{minipage}{6in}\begin{Verbatim}}%
+% {\end{Verbatim}\end{minipage}\end{Sbox}
+% \setlength{\fboxsep}{8pt}\fbox{\TheSbox}}
+
+% \newenvironment{kode}
+% {\begin{Sbox}
+% \footnotesize
+% \begin{minipage}{6in}
+%   %\setlength{\parskip}{0pt}
+%   %\setlength{\topsep}{0pt}
+%   %\setlength{\partopsep}{0pt}
+%   \verbatim}
+% {\endverbatim 
+% \end{minipage}
+% \end{Sbox} 
+% \fbox{\TheSbox}
+%  %\vspace*{-0.1in}
+%  }
+
+\title{Chisel 2.2 Tutorial}
+\author{Jonathan Bachrach, Krste Asanovi\'{c}, John Wawrzynek \\
+EECS Department, UC Berkeley\\
+{\tt  \{jrb|krste|johnw\}@eecs.berkeley.edu}
+}
+\date{\today}
+
+\newenvironment{example}{\VerbatimEnvironment\begin{footnotesize}\begin{Verbatim}}{\end{Verbatim}\end{footnotesize}}
+\newcommand{\kode}[1]{\begin{footnotesize}{\tt #1}\end{footnotesize}}
+
+\def\code#1{{\tt #1}}
+
+\def\note#1{\noindent{\bf [Note: #1]}}
+%\def\note#1{}
+
+\begin{document}
+\maketitle{}
+
+% TODO: default
+% TODO: enum yields Bits
+% TODO: why hardware construction languages
+
+\section{Introduction}
+
+This document is a tutorial introduction to {\em Chisel} (Constructing
+Hardware In a Scala Embedded Language).  Chisel is a hardware
+construction language embedded in the high-level programming language
+Scala.  At some point we will provide a proper reference manual, in
+addition to more tutorial examples.  In the meantime, this document
+along with a lot of trial and error should set you on your way to
+using Chisel.  Chisel is really only a set of special class
+definitions, predefined objects, and usage conventions within Scala,
+so when you write a Chisel program you are actually writing a Scala
+program.  However, for the tutorial we don't presume that you
+understand how to program in Scala.  We will point out necessary Scala
+features through the Chisel examples we give, and significant hardware
+designs can be completed using only the material contained herein.
+But as you gain experience and want to make your code simpler or more
+reusable, you will find it important to leverage the underlying power
+of the Scala language. We recommend you consult one of the excellent
+Scala books to become more expert in Scala programming.
+
+% MS: maybe infancy can now be dropped. Chisel has proven
+% to be mature enough for serious designs.
+Chisel is still in its infancy and you are likely to encounter some
+implementation bugs, and perhaps even a few conceptual design
+problems.  However, we are actively fixing and improving the language,
+and are open to bug reports and suggestions.  Even in its early state,
+we hope Chisel will help designers be more productive in building
+designs that are easy to reuse and maintain.
+
+\begin{commentary}
+Through the tutorial, we format commentary on our design choices as in
+this paragraph.  You should be able to skip the commentary sections
+and still fully understand how to use Chisel, but we hope you'll find
+them interesting.
+
+We were motivated to develop a new hardware language by years of
+struggle with existing hardware description languages in our research
+projects and hardware design courses.  Verilog and VHDL were developed
+as hardware {\em simulation} languages, and only later did they become
+a basis for hardware {\em synthesis}.  Much of the semantics of these
+languages are not appropriate for hardware synthesis and, in fact,
+many constructs are simply not synthesizable.  Other constructs are
+non-intuitive in how they map to hardware implementations, or their
+use can accidently lead to highly inefficient hardware structures.
+While it is possible to use a subset of these languages and yield
+acceptable results, they nonetheless present a cluttered and confusing
+specification model, particularly in an instructional setting.
+
+However, our strongest motivation for developing a new hardware
+language is our desire to change the way that electronic system design
+takes place.  We believe that it is important to not only teach
+students how to design circuits, but also to teach them how to design
+{\em circuit generators}---programs that automatically generate
+designs from a high-level set of design parameters and constraints.
+Through circuit generators, we hope to leverage the hard work of
+design experts and raise the level of design abstraction for everyone.
+To express flexible and scalable circuit construction, circuit
+generators must employ sophisticated programming techniques to make
+decisions concerning how to best customize their output circuits
+according to high-level parameter values and constraints.  While
+Verilog and VHDL include some primitive constructs for programmatic
+circuit generation, they lack the powerful facilities present in
+modern programming languages, such as object-oriented programming,
+type inference, support for functional programming, and reflection.
+
+Instead of building a new hardware design language from scratch, we
+chose to embed hardware construction primitives within an existing
+language.  We picked Scala not only because it includes the
+programming features we feel are important for building circuit
+generators, but because it was specifically developed as a base for
+domain-specific languages.
+\end{commentary}
+
+\section{Hardware expressible in Chisel}
+
+% The initial version of Chisel only supports the expression of
+% synchronous RTL (Register-Transfer Level) designs, with a single
+% common clock.  Synchronous RTL circuits can be expressed as a
+% hierarchical composition of modules containing combinational logic and
+% clocked state elements.  Although Chisel assumes a single global
+% clock, local clock gating logic is automatically generated for every
+% state element in the design to save power.
+% \begin{commentary}
+% Modern hardware designs often include multiple islands of logic, where
+% each island uses a different clock and where islands must correctly
+% communicate across clock island boundaries.  Although clock-crossing
+% synchronization circuits are notoriously difficult to design, there
+% are known good solutions for most scenarios, which can be packaged as
+% library elements for use by designers.  As a result, most effort in
+% new designs is spent in developing and verifying the functionality
+% within each synchronous island rather than on passing values between
+% islands.
+% 
+% In its current form, Chisel can be used to describe each of the
+% synchronous islands individually. Existing tool frameworks can tie
+% together these islands into a complete design.  For example, a
+% separate outer simulation framework can be used to model the assembly
+% of islands running together.  It should be noted that exhaustive
+% dynamic verification of asynchronous communications is usually
+% impossible and that more formal static approaches are usually
+% necessary.
+% \end{commentary}
+
+This version of Chisel only supports binary logic, and does not
+support tri-state signals.
+\begin{commentary}
+We focus on binary logic designs as they constitute the vast majority
+of designs in practice.  We omit support for tri-state logic in the
+current Chisel language as this is in any case poorly supported by
+industry flows, and difficult to use reliably outside of controlled
+hard macros.
+\end{commentary}
+
+\section{Datatypes in Chisel}
+
+Chisel datatypes are used to specify the type of values held in state
+elements or flowing on wires.  While hardware designs ultimately
+operate on vectors of binary digits, other more abstract
+representations for values allow clearer specifications and help the
+tools generate more optimal circuits.  In Chisel, a raw collection of
+bits is represented by the \code{Bits} type.  Signed and unsigned integers
+are considered subsets of fixed-point numbers and are represented by
+types \code{SInt} and \code{UInt} respectively. Signed fixed-point
+numbers, including integers, are represented using two's-complement
+format.  Boolean values are represented as type \code{Bool}.  Note
+that these types are distinct from Scala's builtin types such as
+\code{Int} or \code{Boolean}.  Additionally, Chisel defines {\em Bundles} for making
+collections of values with named fields (similar to {\em structs} in
+other languages), and {\em Vecs} for indexable collections of
+values.  Bundles and Vecs will be covered later.
+
+Constant or literal values are expressed using Scala integers or
+strings passed to constructors for the types:
+\begin{scala}
+UInt(1)       // decimal 1-bit lit from Scala Int.
+UInt("ha")    // hexadecimal 4-bit lit from string.
+UInt("o12")   // octal 4-bit lit from string.
+UInt("b1010") // binary 4-bit lit from string.
+
+SInt(5)    // signed decimal 4-bit lit from Scala Int.
+SInt(-8)   // negative decimal 4-bit lit from Scala Int.
+UInt(5)    // unsigned decimal 3-bit lit from Scala Int.
+
+Bool(true) // Bool lits from Scala lits.
+Bool(false)
+\end{scala}
+
+Underscores can be used as separators in long string literals to aid
+readability, but are ignored when creating the value, e.g.:
+\begin{scala}
+UInt("h_dead_beef")   // 32-bit lit of type UInt
+\end{scala}
+
+By default, the Chisel compiler will size each constant to the minimum
+number of bits required to hold the constant, including a sign bit for
+signed types.  Bit widths can also be specified explicitly on
+literals, as shown below:
+\begin{scala}
+UInt("ha", 8)     // hexadecimal 8-bit lit of type UInt
+UInt("o12", 6)    // octal 6-bit lit of type UInt
+UInt("b1010", 12) // binary 12-bit lit of type UInt
+
+SInt(5, 7) // signed decimal 7-bit lit of type SInt
+UInt(5, 8) // unsigned decimal 8-bit lit of type UInt
+\end{scala}
+
+\noindent
+For literals of type \code{UInt}, the value is
+zero-extended to the desired bit width.  For literals of type
+\code{SInt}, the value is sign-extended to fill the desired bit width.
+If the given bit width is too small to hold the argument value, then a
+Chisel error is generated.
+
+\begin{commentary}
+We are working on a more concise literal syntax for Chisel using
+symbolic prefix operators, but are stymied by the limitations of Scala
+operator overloading and have not yet settled on a syntax that is
+actually more readable than constructors taking strings.
+
+We have also considered allowing Scala literals to be automatically
+converted to Chisel types, but this can cause type ambiguity and
+requires an additional import.
+
+The SInt and UInt types will also later support an optional exponent
+field to allow Chisel to automatically produce optimized fixed-point
+arithmetic circuits.
+\end{commentary}
+
+\section{Combinational Circuits}
+
+A circuit is represented as a graph of nodes in Chisel.  Each node is
+a hardware operator that has zero or more inputs and that drives one
+output.  A literal, introduced above, is a degenerate kind of node
+that has no inputs and drives a constant value on its output.  One way
+to create and wire together nodes is using textual expressions.  For
+example, we can express a simple combinational logic circuit
+using the following expression:
+
+\begin{scala}
+(a & b) | (~c & d)
+\end{scala}
+
+The syntax should look familiar, with \code{\&} and \code{|}
+representing bitwise-AND and -OR respectively, and \code{\~{}}
+representing bitwise-NOT.  The names \code{a} through \code{d}
+represent named wires of some (unspecified) width.
+
+Any simple expression can be converted directly into a circuit tree,
+with named wires at the leaves and operators forming the internal
+nodes.  The final circuit output of the expression is taken from the
+operator at the root of the tree, in this example, the bitwise-OR.
+
+Simple expressions can build circuits in the shape of trees, but to
+construct circuits in the shape of arbitrary directed acyclic graphs
+(DAGs), we need to describe fan-out.  In Chisel, we do this by naming
+a wire that holds a subexpression that we can then reference multiple
+times in subsequent expressions.  We name a wire in Chisel by
+declaring a variable.  For example, consider the select expression,
+which is used twice in the following multiplexer description:
+\begin{scala}
+val sel = a | b
+val out = (sel & in1) | (~sel & in0)
+\end{scala}
+
+\noindent
+The keyword \code{val} is part of Scala, and is used to name variables
+that have values that won't change.  It is used here to name the
+Chisel wire, \code{sel}, holding the output of the first bitwise-OR
+operator so that the output can be used multiple times in the second
+expression.
+
+\section{Builtin Operators}
+
+Chisel defines a set of hardware operators for the builtin types shown
+in Table~\ref{tbl:chisel-operators}.
+\begin{table*}
+\begin{center}
+\begin{tabular}{|l|l|}
+\hline
+Example & Explanation \\
+\hline
+\hline
+\multicolumn{2}{|l|}{Bitwise operators.  Valid on SInt, UInt, Bool.} \\
+\hline
+\hline
+\verb!val invertedX = ~x!                    &   Bitwise NOT  \\
+\verb!val hiBits = x & UInt("h_ffff_0000") ! &   Bitwise AND  \\
+\verb!val flagsOut = flagsIn | overflow !    &   Bitwise OR   \\
+\verb!val flagsOut = flagsIn ^ toggle !      &   Bitwise XOR  \\
+\hline
+\hline
+\multicolumn{2}{|l|}{Bitwise reductions.  Valid on SInt and
+  UInt.  Returns Bool. } \\
+\hline
+\hline
+\verb!val allSet = andR(x) ! & AND reduction  \\
+\verb!val anySet = orR(x)  ! & OR reduction   \\
+\verb!val parity = xorR(x) !  & XOR reduction  \\
+\hline
+\hline
+\multicolumn{2}{|l|}{Equality comparison. Valid on SInt, 
+UInt, and Bool. Returns Bool.} \\
+\hline
+\hline
+\verb@val equ = x === y@ & Equality \\
+\verb@val neq = x =/= y@ & Inequality \\
+\hline
+\hline
+\multicolumn{2}{|l|}{Shifts. Valid on SInt and UInt.} \\
+\hline
+\hline
+\verb@val twoToTheX = SInt(1) << x@  & Logical left shift. \\
+\verb@val hiBits = x >> UInt(16)@          & Right shift (logical on UInt and\&
+arithmetic on SInt). \\
+% \verb@val scaledX = x >>> 3@  & Arithmetic right shift, copies in sign bits. \\
+\hline
+\hline
+\multicolumn{2}{|l|}{Bitfield manipulation.  Valid on SInt, UInt, and Bool. } \\
+\hline
+\hline
+\verb@val xLSB = x(0)@  & Extract single bit, LSB has index 0. \\
+\verb@val xTopNibble = x(15,12)@  & Extract bit field  from end to start
+bit position. \\
+\verb@val usDebt = Fill(3, UInt("hA"))@ & Replicate a bit string multiple times. \\
+\verb@val float = Cat(sign,exponent,mantissa)@ & Concatenates bit fields, with first argument on left.\\
+\hline
+\hline
+\multicolumn{2}{|l|}{Logical operations.  Valid on Bools. } \\
+\hline
+\verb@val sleep = !busy@  & Logical NOT \\
+\verb@val hit = tagMatch && valid @  & Logical AND \\
+\verb@val stall = src1busy || src2busy@  & Logical OR \\
+\verb@val out = Mux(sel, inTrue, inFalse)@  & Two-input mux where sel is a Bool \\ % {\bf Why?} \\
+\hline
+\hline
+\multicolumn{2}{|l|}{Arithmetic operations.  Valid on Nums: SInt and UInt. } \\
+\hline
+\verb@val sum = a + b@  & Addition \\
+\verb@val diff = a - b @  & Subtraction \\
+\verb@val prod = a * b @  & Multiplication \\
+\verb@val div = a / b @  & Division \\
+\verb@val mod = a % b @  & Modulus \\
+\hline
+\hline
+\multicolumn{2}{|l|}{Arithmetic comparisons.  Valid on Nums: SInt and
+  UInt. Returns Bool.} \\
+\hline
+\verb@val gt = a > b@  & Greater than \\
+\verb@val gte = a >= b@  & Greater than or equal \\
+\verb@val lt = a < b@  & Less than \\
+\verb@val lte = a <= b@  & Less than or equal \\
+\hline
+\end{tabular}
+\end{center}
+\caption{Chisel operators on builtin data types.}
+\label{tbl:chisel-operators}
+\end{table*}
+
+\subsection{Bitwidth Inference}
+
+Users are required to set bitwidths of ports and registers, but otherwise,
+bit widths on wires are automatically inferred unless set manually by the user.
+% TODO: how do you set the width explicitly?
+The bit-width inference engine starts from the graph's input ports and 
+calculates node output bit widths from their respective input bit widths according to the following set of rules:
+
+\begin{tabular}{ll}
+{\bf operation} & {\bf bit width} \\ 
+\verb|z = x + y| & \verb|wz = max(wx, wy)| \\
+\verb+z = x - y+ & \verb|wz = max(wx, wy)|\\
+\verb+z = x & y+ & \verb+wz = min(wx, wy)+ \\
+\verb+z = Mux(c, x, y)+ & \verb+wz = max(wx, wy)+ \\
+\verb+z = w * y+ & \verb!wz = wx + wy! \\
+\verb+z = x << n+ & \verb!wz = wx + maxNum(n)! \\
+\verb+z = x >> n+ & \verb+wz = wx - minNum(n)+ \\
+\verb+z = Cat(x, y)+ & \verb!wz = wx + wy! \\
+\verb+z = Fill(n, x)+ & \verb+wz = wx * maxNum(n)+ \\
+% \verb+z = x < y+ & \verb+<= > >= && || != ===+ & \verb+wz = 1+ \\
+\end{tabular}
+
+\noindent
+where for instance $wz$ is the bit width of wire $z$, and the \verb+&+
+rule applies to all bitwise logical operations.
+
+\comment{maxNum and MinNum need to be explained.}
+
+The bit-width inference process continues until no bit width changes.
+Except for right shifts by known constant amounts, the bit-width
+inference rules specify output bit widths that are never smaller than
+the input bit widths, and thus, output bit widths either grow or stay
+the same.  Furthermore, the width of a register must be specified by
+the user either explicitly or from the bitwidth of the reset value or
+the \emph{next} parameter.
+From these two requirements, we can show that the bit-width inference
+process will converge to a fixpoint.
+
+\begin{commentary}
+Our choice of operator names was constrained by the Scala language.
+We have to use triple equals \code{===} for equality and \code{=/=}
+for inequality to allow the
+native Scala equals operator to remain usable.
+
+We are also planning to add further operators that constrain bitwidth
+to the larger of the two inputs.
+\end{commentary}
+
+\section{Functional Abstraction}
+
+We can define functions to factor out a repeated piece of logic that
+we later reuse multiple times in a design.  For example, we can wrap
+up our earlier example of a simple combinational logic block as
+follows:
+\begin{scala}
+def clb(a: UInt, b: UInt, c: UInt, d: UInt): UInt = 
+  (a & b) | (~c & d)
+\end{scala}
+
+\noindent
+where \code{clb} is the function which takes \code{a}, \code{b},
+\code{c}, \code{d} as arguments and returns a wire to the output of a
+boolean circuit.  The \code{def} keyword is part of Scala and
+introduces a function definition, with each argument followed by a colon then its type,
+and the function return type given after the colon following the
+argument list.  The equals (\code{=})
+sign separates the function argument list from the function
+definition.
+
+We can then use the block in another circuit as follows:
+\begin{scala}
+val out = clb(a,b,c,d)
+\end{scala}
+
+% TODO: SHIFTER DONE FUNCTIONAL WITH LOOP
+
+%% Because Scala has powerful type inference, we can in many cases drop
+%% the type declarations on the function:
+%% \begin{scala}
+%% def clb(a, b, c, d) = (a & b) | (~c & d) // No types needed.
+
+%% def bigblock(a: Bool, b: Bool, c: Bool, d: Bool,
+%%              f: UInt, g: UInt, h: UInt, i: UInt): Bool =
+%%                  clb(a, b, c, clb(f,g,h,i)!=0) 
+
+%% \end{scala}
+
+%% Here, we use \code{clb} twice.  The inner \verb!clb!  works with
+%% fixed-point values to calculate the value of an internal node that is
+%% compared with 0 to give a \code{Bool}, while the outer \verb!clb!
+%%   works with \code{Bool} values and returns the result of the
+%%   function.  Scala will perform type inference statically to check
+%%   that there are no type errors.
+
+We will later describe many powerful ways to use functions to
+construct hardware using Scala's functional programming support.
+
+\section{Bundles and Vecs}
+
+\code{Bundle} and \code{Vec} are classes that allow the user to expand
+the set of Chisel datatypes with aggregates of other types.
+
+Bundles group together several named fields of potentially different
+types into a coherent unit, much like a \code{struct} in C. Users
+define their own bundles by defining a class as a subclass of
+\code{Bundle}:
+\begin{scala}
+class MyFloat extends Bundle {
+  val sign        = Bool()
+  val exponent    = UInt(width = 8)
+  val significand = UInt(width = 23)
+}
+
+val x  = new MyFloat()
+val xs = x.sign
+\end{scala}
+
+\noindent
+A Scala convention is to capitalize the name of new classes and we
+suggest you follow that convention in Chisel too.  The \code{width}
+named parameter to the \code{UInt} constructor specificies the number
+of bits in the type.
+
+Vecs create an indexable vector of elements, and are constructed as
+follows:
+\begin{scala}
+// Vector of 5 23-bit signed integers.
+val myVec = Vec.fill(5){ SInt(width = 23) } 
+
+// Connect to one element of vector. 
+val reg3  = myVec(3) 
+\end{scala}
+
+\noindent
+(Note that we have to specify the type of the \code{Vec} elements
+inside the trailing curly brackets, as we have to pass the bitwidth
+parameter into the \code{SInt} constructor.)
+
+The set of primitive classes
+(\code{SInt}, \code{UInt}, and \code{Bool}) plus the aggregate
+classes (\code{Bundles} and \code{Vec}s) all inherit from a common
+superclass, \code{Data}.  Every object that ultimately inherits from
+\code{Data} can be represented as a bit vector in a hardware design.
+
+Bundles and Vecs can be arbitrarily nested to build complex data
+structures:
+\begin{scala}
+class BigBundle extends Bundle {
+ // Vector of 5 23-bit signed integers.
+ val myVec = Vec.fill(5) { SInt(width = 23) } 
+ val flag  = Bool()
+ // Previously defined bundle.
+ val f     = new MyFloat()              
+}
+\end{scala}
+
+\noindent
+Note that the builtin Chisel primitive and aggregate classes do not
+require the \code{new} when creating an instance, whereas new user
+datatypes will.  A Scala \code{apply} constructor can be defined so
+that a user datatype also does not require \code{new}, as described in
+Section~\ref{sec:funconstructor}.
+
+\section{Ports}
+
+Ports are used as interfaces to hardware components.  A port is simply
+any \code{Data} object that has directions assigned to its members.
+
+Chisel provides port constructors to allow a direction to be added
+(input or output) to an object at construction time.  Primitive port
+constructors take the direction as the first
+argument (where the direction is \code{INPUT} or
+\code{OUTPUT}) and the number of bits as the second argument (except
+booleans which are always one bit).
+
+An example port declaration is as follows:
+\begin{scala}
+class Decoupled extends Bundle {
+  val ready = Bool(OUTPUT)
+  val data  = UInt(INPUT, 32)
+  val valid = Bool(INPUT)
+}
+\end{scala}
+
+\noindent
+After defining \code{Decoupled}, it becomes a new type that can be
+used as needed for module interfaces or for named collections of
+wires.
+
+The direction of an object can also be assigned at instantation time:
+\begin{scala}
+class ScaleIO extends Bundle {
+  val in    = new MyFloat().asInput
+  val scale = new MyFloat().asInput
+  val out   = new MyFloat().asOutput
+}
+\end{scala}
+
+\noindent
+The methods \code{asInput} and \code{asOutput} force all modules of
+the data object to the requested direction.
+
+By folding directions into the object declarations, Chisel is able to
+provide powerful wiring constructs described later.
+%% \begin{scala}
+%% class MuxBundle extends Bundle {
+%%   val sel = UInt(INPUT,  1)
+%%   val in0 = UInt(INPUT,  1)
+%%   val in1 = UInt(INPUT,  1)
+%%   val out = UInt(OUTPUT, 1)
+%% }
+
+%% class Mux2 extends Module {
+%%   val io = new MuxBundle()
+%%   io.out := (io.sel & io.in1) | (~io.sel & io.in0)
+%% }
+%% \end{scala}
+
+
+\section{Modules}
+
+Chisel {\em modules} are very similar to Verilog {\em modules} in
+defining a hierarchical structure in the generated circuit.
+%Like functional generators, we can also parameterize the construction of
+%circuits by turning them into object-oriented modules.  Unlike
+%functional generators, modules also provide a coarse hierarchy on a
+%circuit and permit a level of generator abstraction that is often
+%useful.
+The hierarchical module namespace is accessible in downstream tools
+to aid in debugging and physical layout.  A user-defined module is
+defined as a {\em class} which:
+\begin{itemize}
+\item inherits from \code{Module},
+\item contains an interface stored in a port field named \code{io}, and
+\item wires together subcircuits in its constructor.
+\end{itemize}
+As an example, consider defining your own two-input multiplexer as a
+module:
+\begin{scala}
+class Mux2 extends Module {
+  val io = new Bundle{
+    val sel = UInt(INPUT, 1)
+    val in0 = UInt(INPUT, 1)
+    val in1 = UInt(INPUT, 1)
+    val out = UInt(OUTPUT, 1)
+  }
+  io.out := (io.sel & io.in1) | (~io.sel & io.in0)
+}
+\end{scala}
+
+\noindent
+The wiring interface to a module is a collection of ports in the
+form of a \code{Bundle}.  The interface to the module is defined
+through a field named \code{io}.  For \code{Mux2}, \code{io} is
+defined as a bundle with four fields, one for each multiplexer port.
+
+The \code{:=} assignment operator, used here in the body of the
+definition, is a special operator in Chisel that wires the input of
+left-hand side to the output of the right-hand side.
+
+\subsection{Module Hierarchy}
+
+We can now construct circuit hierarchies, where we build larger modules out
+of smaller sub-modules.  For example, we can build a 4-input
+multiplexer module in terms of the \code{Mux2} module by wiring
+together three 2-input multiplexers:
+
+\begin{scala}
+class Mux4 extends Module {
+  val io = new Bundle {
+    val in0 = UInt(INPUT, 1)
+    val in1 = UInt(INPUT, 1)
+    val in2 = UInt(INPUT, 1)
+    val in3 = UInt(INPUT, 1)
+    val sel = UInt(INPUT, 2)
+    val out = UInt(OUTPUT, 1)
+  }
+  val m0 = Module(new Mux2())
+  m0.io.sel := io.sel(0) 
+  m0.io.in0 := io.in0; m0.io.in1 := io.in1
+
+  val m1 = Module(new Mux2())
+  m1.io.sel := io.sel(0) 
+  m1.io.in0 := io.in2; m1.io.in1 := io.in3
+
+  val m3 = Module(new Mux2())
+  m3.io.sel := io.sel(1) 
+  m3.io.in0 := m0.io.out; m3.io.in1 := m1.io.out
+
+  io.out := m3.io.out
+}
+\end{scala}
+
+\noindent
+We again define the module interface as \code{io} and wire up the
+inputs and outputs.  In this case, we create three \code{Mux2}
+children modules, using the \code{Module} constructor function and 
+the Scala \code{new} keyword to create a
+new object.  We then wire them up to one another and to the ports of
+the \code{Mux4} interface.
+
+\section{Running and Testing Examples}
+
+Now that we have defined modules, we will discuss how we actually run and test a circuit.  Chisel translates into either \verb@C++@ or Verilog.   In order to build a circuit we need to call \code{chiselMain}:
+
+\begin{scala}
+object tutorial {
+  def main(args: Array[String]) = {
+    chiselMain(args, () => Module(new Mux2()))
+  }
+}
+\end{scala}
+
+\begin{figure}
+\begin{center}
+\includegraphics[width=0.45\textwidth]{../tutorial/figs/DUT.pdf}
+\end{center}
+\caption{DUT run using a Tester object in Scala with stdin and stdout connected}
+\label{fig:dut}
+\end{figure}
+ 
+Testing is a crucial part of circuit design, 
+and thus in Chisel we provide a mechanism for
+testing circuits by providing test vectors within Scala using
+subclasses of the \code{Tester} class:
+
+\begin{scala}
+class Tester[T <: Module] (val c: T, val isTrace: Boolean = true) {
+  var t: Int
+  val rnd: Random
+  def int(x: Boolean): BigInt
+  def int(x: Int): BigInt
+  def int(x: Bits): BigInt
+  def reset(n: Int = 1)
+  def step(n: Int): Int
+  def pokeAt(data: Mem[T], index: Int, x: BigInt)
+  def poke(data: Bits, x: BigInt)
+  def poke(data: Aggregate, x: Array[BigInt])
+  def peekAt(data: Mem[T], index: Int)
+  def peek(data: Bits): BigInt
+  def peek(data: Aggregate): Array[BigInt]
+  def expect (good: Boolean, msg: String): Boolean
+  def expect (data: Bits, target: BigInt): Boolean
+}
+\end{scala}
+
+\noindent
+which binds a tester to a module
+and allows users to write tests using the given debug protocol.  In particular, users utilize:
+\begin{itemize}
+\item \code{poke} to set input port and state values,
+\item \code{step} to execute the circuit one time unit,
+\item \code{peek} to read port and state values, and
+\item \code{expect} to compare peeked circuit values to expected arguments.
+\end{itemize}
+
+\noindent
+Users connect tester instances to modules using:
+
+
+\begin{scala}
+object chiselMainTest {
+  def apply[T <: Module]
+    (args: Array[String], comp: () => T)(
+     tester: T => Tester[T]): T
+}
+\end{scala}
+
+\noindent
+When \code{-{-}test} is given as an argument to \code{chiselMainTest}, a
+tester instance runs the Design Under Test (DUT) in a separate
+process with \code{stdin} and \code{stdout} connected so that debug commands can 
+be sent to the DUT and responses can be received from the DUT as shown in
+Figure~\ref{fig:dut}.
+\noindent
+
+For example, in the following:
+
+\begin{scala}
+class Mux2Tests(c: Mux2) extends Tester(c) {
+  val n = pow(2, 3).toInt
+  for (s <- 0 until 2) {
+    for (i0 <- 0 until 2) {
+      for (i1 <- 0 until 2) {
+        poke(c.io.sel, s)
+        poke(c.io.in1, i1)
+        poke(c.io.in0, i0)
+        step(1)
+        expect(c.io.out, (if (s == 1) i1 else i0))
+      }
+    }
+  }
+}
+\end{scala}
+
+\noindent
+assignments for each input of \verb+Mux2+ is set to the appropriate values using \verb+poke+. For this particular example, we are testing the \verb+Mux2+ by hardcoding the inputs to some known values and checking if the output corresponds to the known one. To do this, on each iteration we generate appropriate inputs to the module and tell the simulation to assign these values to the inputs of the device we are testing \verb+c+, step the circuit, and test the expected value.  
+\comment{Maybe elaborate a little bit what a step does. I assume it is one clock tick
+Is a step needed as well for testing plain combinational circuits?}
+Finally, the following shows how the tester is invoked:
+
+\begin{scala}
+chiselMainTest(args + "--test", () => Module(new Mux2())){ 
+  c => new Mux2Tests(c) 
+}
+\end{scala}
+
+Other command arguments are as follows:
+\begin{tabular}{lll}
+\verb+--targetDir+ & target pathname prefix \\
+\verb+--genHarness+ & generate harness file for C++ \\
+\verb+--backend v+ & generate verilog \\
+\verb+--backend c+ & generate C++ (default)\\
+\verb+--vcd+ & enable vcd dumping \\
+\verb+--debug+ & put all wires in class file \\
+\end{tabular}
+
+\comment{What does it mean to generate a harness file?}
+
+\section{State Elements}
+\label{sec:sequential}
+
+% SINGLE CLK and RESET
+
+The simplest form of state element supported by Chisel is a
+positive edge-triggered register, which can be instantiated
+as:
+\begin{scala}
+val reg = Reg(next = in)
+\end{scala}
+
+\noindent
+This circuit has an output that is a copy of the input signal \verb+in+
+delayed by one clock cycle.  Note that we do not have to specify the
+type of \verb+Reg+ as it will be automatically inferred from its input
+when instantiated in this way.  In the current version of Chisel,
+clock and reset are global signals that are implicity included where
+needed.
+
+Using registers, we can quickly define a number of useful circuit
+constructs.  For example, a rising-edge detector that takes a boolean
+signal in and outputs true when the current value is true and the
+previous value is false is given by:
+\begin{scala}
+def risingedge(x: Bool) = x && !Reg(next = x)
+\end{scala}
+
+Counters are an important sequential circuit.  To construct an
+up-counter that counts up to a maximum value, \verb+max+, then wraps
+around back to zero (i.e., modulo \verb!max+1!), we write:
+\begin{scala}
+def counter(max: UInt) = {
+  val x = Reg(init = UInt(0, max.getWidth))
+  x := Mux(x === max, UInt(0), x + UInt(1))
+  x
+}
+\end{scala}
+
+\noindent
+The counter register is created in the \verb!counter! function 
+with a reset value of \verb!0! (with width large enough to hold \verb+max+),
+to which the register will be initialized when the global reset for the circuit is asserted.
+The \verb!:=! assignment to \verb!x! in \verb!counter! wires an update combinational circuit 
+which increments the counter value unless it hits the \verb+max+ at which point it wraps back to zero.
+Note that when \verb!x! appears on the right-hand side of
+an assigment, its output is referenced, whereas when on the left-hand
+side, its input is referenced.
+
+Counters can be used to build a number of useful sequential circuits.
+For example, we can build a pulse generator by outputting true when
+a counter reaches zero:
+\begin{scala}
+// Produce pulse every n cycles.
+def pulse(n: UInt) = counter(n - UInt(1)) === UInt(0)
+\end{scala}
+
+\noindent
+A square-wave generator can then be toggled by the pulse train,
+toggling between true and false on each pulse:
+\begin{scala}[escapechar=@]
+// Flip internal state when input true.
+def toggle(p: Bool) = {
+  val x = Reg(init = Bool(false))
+  x := Mux(p, !x, x)
+  x
+}
+
+// Square wave of a given period.
+def squareWave(period: UInt) = toggle(pulse(period/2))
+\end{scala}
+
+\subsection{Forward Declarations}
+
+Purely combinational circuits cannot have cycles between nodes, and
+Chisel will report an error if such a cycle is detected.  Because they
+do not have cycles, combinational circuits can always be constructed
+in a feed-forward manner, by adding new nodes whose inputs are derived
+from nodes that have already been defined.  Sequential circuits
+naturally have feedback between nodes, and so it is sometimes
+necessary to reference an output wire before the producing node has
+been defined.  Because Scala evaluates program statements
+sequentially, we allow data nodes to serve as a wire providing
+a declaration of a node that can be used immediately, but whose
+input will be set later.  
+For example, in a simple CPU, we need to define the \verb!pcPlus4!
+and \verb!brTarget! wires so they can be referenced before defined:
+\begin{scala}
+val pcPlus4  = UInt()
+val brTarget = UInt()
+val pcNext   = Mux(io.ctrl.pcSel, brTarget, pcPlus4)
+val pcReg    = Reg(next = pcNext, init = UInt(0, 32))
+pcPlus4     := pcReg + UInt(4)
+...
+brTarget    := addOut
+\end{scala}
+
+\noindent
+The wiring operator
+\verb!:=! is used to wire up
+the connection after \verb!pcReg! and \verb!addOut! are defined.
+
+\subsection{Conditional Updates}
+
+In our previous examples using registers, we simply wired the
+combinational logic blocks to the inputs of the registers.
+When describing the operation of state
+elements, it is often useful to instead specify when updates to the
+registers will occur and to specify these updates spread across
+several separate statements.  Chisel provides conditional update rules
+in the form of the \code{when} construct to support this style of
+sequential logic description. For example,
+% MS: the following is not working (anymore), it results in a single bit register
+% with the incrementing code.
+% val r = Reg(UInt(16))
+% MS: is there any meaning having a single, unnamed parameter for Reg()?
+% MS: should this be allowed?
+\begin{scala}
+val r = Reg(init = UInt(0, 16))
+when (cond) {
+  r := r + UInt(1)
+}
+\end{scala}
+
+\noindent
+where register \code{r} is updated at the end of the current clock
+cycle only if \verb+cond+ is \code{true}.  The argument to \code{when} is a
+predicate circuit expression that returns a \code{Bool}.  The update
+block following \code{when} can only contain update statements using
+the assignment operator \verb+:=+, simple expressions, and named wires
+defined with \code{val}.
+
+In a sequence of conditional updates, the last conditional update
+whose condition is true takes priority.  For example,
+\begin{scala}
+when (c1) { r := UInt(1) }
+when (c2) { r := UInt(2) }
+\end{scala}
+
+\noindent
+leads to \code{r} being updated according to the following truth table:
+\begin{center}
+{\small
+\begin{tabular}{|c|c|c|l|}
+\hline
+c1 & c2  &  r & \\
+\hline
+0 &  0 & r &  r unchanged \\
+0 &  1 & 2 & \\
+1 &  0 & 1 & \\
+1 &  1 & 2& c2 takes precedence over c1 \\
+\hline
+\end{tabular}
+}
+\end{center}
+
+\begin{figure}[h]
+\centering
+\includegraphics[width=3in]{figs/condupdates.pdf}
+\caption{Equivalent hardware constructed for conditional updates.
+  Each \code{when} statement adds another level of data mux and ORs
+  the predicate into the enable chain.  The compiler effectively adds
+  the termination values to the end of the chain automatically.}
+\label{fig:condupdates}
+\end{figure}
+
+Figure~\ref{fig:condupdates} shows how each conditional update can be
+viewed as inserting a mux before the input of a register to select
+either the update expression or the previous input according to the
+\code{when} predicate.  In addition, the predicate is OR-ed into an
+enable signal that drives the load enable of the register.  The
+compiler places initialization values at the beginning of the chain so
+that if no conditional updates fire in a clock cycle, the load enable
+of the register will be deasserted and the register value will not
+change.
+ 
+Chisel provides some syntactic sugar for other common forms of
+conditional update.  The \verb+unless+ construct is the same as
+\verb+when+ but negates its condition.  In other words,
+\begin{scala}
+unless (c) { body }
+\end{scala}
+is the same as
+\begin{scala}
+when (!c) { body }
+\end{scala}
+
+% The \verb+otherwise+ construct is the same as \verb+when+ with a true
+% condition.  In other words,
+% \begin{scala}
+% otherwise { body }
+% \end{scala}
+% 
+% \noindent
+% is the same as
+% \begin{scala}
+% when (Bool(true)) { body }
+% \end{scala}
+
+The update block can target multiple registers, and there can be
+different overlapping subsets of registers present in different update
+blocks.  Each register is only affected by conditions in which it
+appears.  The same is possible for combinational circuits (update
+of a \code{Wire}). Note that all combinational
+circuits need a default value. For example:
+\begin{scala}
+r := SInt(3); s := SInt(3)
+when (c1)   { r := SInt(1); s := SInt(1) }
+when (c2)   { r := SInt(2) }
+\end{scala}
+
+\noindent
+leads to \code{r} and \code{s} being updated according to the
+following truth table:
+\begin{scala}
+c1 c2  r  s
+0   0  3  3
+0   1  2  3 // r updated in c2 block, s at top level.
+1   0  1  1
+1   1  2  1
+\end{scala}
+
+\begin{commentary}
+We are considering adding a different form of conditional update,
+where only a single update block will take effect.  These atomic
+updates are similar to Bluespec guarded atomic actions.
+% TODO: when / .elsewhen / .otherwise
+\end{commentary}
+
+Conditional update constructs can be nested and any given block is
+executed under the conjunction of all outer nesting conditions.  For
+example,
+\begin{scala}
+when (a) { when (b) { body } }
+\end{scala}
+
+\noindent
+is the same as:
+\begin{scala}
+when (a && b) { body }
+\end{scala}
+
+Conditionals can be chained together using
+\verb+when+, \verb+.elsewhen+, \verb+.otherwise+ corresponding to
+\verb+if+, \verb+else if+ and \verb+else+ in Scala.  For example,
+\begin{scala}
+when (c1) { u1 }
+.elsewhen (c2) { u2 }
+.otherwise { ud }
+\end{scala}
+\noindent
+is the same as:
+\begin{scala}
+when (c1) { u1 }
+when (!c1 && c2) { u2 }
+when (!(c1 || c2)) { ud }
+\end{scala}
+
+We introduce the \code{switch} statement for conditional updates
+involving a series of comparisons against a common key.  For example,
+\begin{scala}
+switch(idx) {
+ is(v1) { u1 }
+ is(v2) { u2 }
+}
+\end{scala}
+
+\noindent
+is equivalent to:
+\begin{scala}
+when (idx === v1) { u1 }
+.elsewhen (idx === v2) { u2 }
+\end{scala}
+
+Chisel also allows a \code{Wire}, i.e., the output of some
+combinational logic, to be the target of conditional update statements
+to allow complex combinational logic expressions to be built
+incrementally.  Chisel does not allow a combinational output to be
+incompletely specified and will report an error if an unconditional
+update is not encountered for a combinational output.
+\begin{commentary}
+In Verilog, if a procedural specification of a combinational logic
+block is incomplete, a latch will silently be inferred causing many
+frustrating bugs.
+
+It could be possible to add more analysis to the Chisel compiler, to
+determine if a set of predicates covers all possibilities.  But for
+now, we require a single predicate that is always true in the
+chain of conditional updates to a \code{Wire}.
+\end{commentary}
+
+
+\subsection{Finite State Machines}
+
+A common type of sequential circuit used in digital design is a Finite
+State Machine (FSM).  An example of a simple FSM is a parity
+generator:
+
+% \begin{scala}
+% class Parity extends Module {
+%   val io = new Bundle {
+%     val in  = Bool(INPUT)
+%     val out = Bool(OUTPUT) }
+%   val s_even :: s_odd :: Nil = Enum(2, UInt())
+%   val state  = Reg(init = s_even)
+%   switch(state, Array(
+%     (s_even, () => { when (io.in) { state := s_odd } }),
+%     (s_odd,  () => { when (io.in) { state := s_even } }) ))
+%   io.out := state === s_odd
+% }
+% \end{scala}
+
+\begin{scala}
+class Parity extends Module {
+  val io = new Bundle {
+    val in  = Bool(dir = INPUT)
+    val out = Bool(dir = OUTPUT) }
+  val s_even :: s_odd :: Nil = Enum(UInt(), 2)
+  val state  = Reg(init = s_even)
+  when (io.in) {
+    when (state === s_even) { state := s_odd  }
+    when (state === s_odd)  { state := s_even }
+  }
+  io.out := (state === s_odd)
+}
+\end{scala}
+
+\noindent
+where \verb+Enum(UInt(), 2)+ generates two \verb+UInt+ literals.
+States are updated when \verb+in+ is true.  It is worth
+noting that all of the mechanisms for FSMs are built upon registers,
+wires, and conditional updates.
+
+Below is a more complicated FSM example which is a circuit for
+accepting money for a vending machine:
+\begin{scala}
+class VendingMachine extends Module {
+  val io = new Bundle {
+    val nickel = Bool(dir = INPUT)
+    val dime   = Bool(dir = INPUT)
+    val valid    = Bool(dir = OUTPUT) }
+  val s_idle :: s_5 :: s_10 :: s_15 :: s_ok :: Nil = 
+    Enum(UInt(), 5)
+  val state = Reg(init = s_idle)
+  when (state === s_idle) {
+    when (io.nickel) { state := s_5 }
+    when (io.dime)   { state := s_10 }
+  }
+  when (state === s_5) {
+    when (io.nickel) { state := s_10 }
+    when (io.dime)   { state := s_15 }
+  }
+  when (state === s_10) {
+    when (io.nickel) { state := s_15 }
+    when (io.dime)   { state := s_ok }
+  }
+  when (state === s_15) {
+    when (io.nickel) { state := s_ok }
+    when (io.dime)   { state := s_ok }
+  }
+  when (state === s_ok) {
+    state := s_idle
+  }
+  io.valid := (state === s_ok)
+}
+\end{scala}
+
+\noindent
+Here is the vending machine FSM defined with \code{switch} statement:
+\begin{scala}
+class VendingMachine extends Module {
+  val io = new Bundle {
+    val nickel = Bool(dir = INPUT)
+    val dime   = Bool(dir = INPUT)
+    val valid    = Bool(dir = OUTPUT)
+  }
+  val s_idle :: s_5 :: s_10 :: s_15 :: s_ok :: Nil = Enum(UInt(), 5)
+  val state = Reg(init = s_idle)
+  
+  switch (state) {
+    is (s_idle) {
+      when (io.nickel) { state := s_5 }
+      when (io.dime) { state := s_10 }
+    }
+    is (s_5) {
+      when (io.nickel) { state := s_10 }
+      when (io.dime) { state := s_15 }
+    }
+    is (s_10) {
+      when (io.nickel) { state := s_15 }
+      when (io.dime) { state := s_ok }
+    }
+    is (s_15) {
+      when (io.nickel) { state := s_ok }
+      when (io.dime) { state := s_ok }
+    }
+    is (s_ok) {
+      state := s_idle
+    }
+  }
+  io.valid := (state ===s_ok)
+}
+\end{scala}
+
+\section{Memories}
+
+Chisel provides facilities for creating both read only and
+read/write memories.  
+
+\subsection{ROM}
+
+Users can define read only memories with a \code{Vec}:
+
+\begin{scala}
+Vec(inits: Seq[T])
+Vec(elt0: T, elts: T*)
+\end{scala}
+
+\noindent
+where \verb+inits+ is a sequence of initial \verb+Data+ literals that
+initialize the ROM.
+For example,  users can
+create a small ROM initialized to \verb+1, 2, 4, 8+ and 
+loop through all values using a counter as an address generator as follows:
+
+\begin{scala}
+val m = Vec(Array(UInt(1), UInt(2), UInt(4), UInt(8)))
+val r = m(counter(UInt(m.length)))
+\end{scala}
+
+\noindent
+We can create an \verb+n+ value sine lookup table using a ROM initialized as follows:
+
+\begin{scala}
+def sinTable (amp: Double, n: Int) = {
+  val times = 
+    Range(0, n, 1).map(i => (i*2*Pi)/(n.toDouble-1) - Pi)
+  val inits = 
+    times.map(t => SInt(round(amp * sin(t)), width = 32))
+  Vec(inits)
+}
+def sinWave (amp: Double, n: Int) = 
+  sinTable(amp, n)(counter(UInt(n))
+\end{scala}
+
+\noindent
+where \verb+amp+ is used to scale the fixpoint values stored in the ROM.
+
+\subsection{Mem}
+
+Memories are given special treatment in Chisel since hardware
+implementations of memory have many variations, e.g., FPGA memories
+are instantiated quite differently from ASIC memories.  Chisel defines
+a memory abstraction that can map to either simple Verilog behavioral
+descriptions, or to instances of memory modules that are available
+from external memory generators provided by foundry or IP vendors.  
+
+Chisel supports random-access memories via the \code{Mem} construct.
+Writes to Mems are positive-edge-triggered and reads are either
+combinational or positive-edge-triggered.\footnote{Current FPGA technology
+does not support combinational (asynchronous) reads (anymore). The read address
+needs to be registered.}
+
+
+\begin{scala}
+object Mem {
+  def apply[T <: Data](type: T, depth: Int, 
+          seqRead: Boolean = false): Mem
+}
+
+class Mem[T <: Data](type: T, depth: Int,
+      seqRead: Boolean = false)
+    extends Updateable {
+  def apply(idx: UInt): T
+}
+\end{scala}
+
+Ports into Mems are created by applying a \code{UInt} index.  A 32-entry
+register file with one write port and two combinational read ports might be
+expressed as follows:
+
+\begin{scala}
+val rf = Mem(UInt(width = 64), 32)
+when (wen) { rf(waddr) := wdata }
+val dout1 = rf(waddr1)
+val dout2 = rf(waddr2)
+\end{scala}
+
+If the optional parameter \code{seqRead} is set, Chisel will attempt to infer
+sequential read ports when the read address is a \code{Reg}.  A one-read port,
+one-write port SRAM might be described as follows:
+
+\begin{scala}
+val ram1r1w =
+  Mem(UInt(width = 32), 1024, seqRead = true)
+val reg_raddr = Reg(UInt())
+when (wen) { ram1r1w(waddr) := wdata }
+when (ren) { reg_raddr := raddr }
+val rdata = ram1r1w(reg_raddr)
+\end{scala}
+
+Single-ported SRAMs can be inferred when the read and write conditions are
+mutually exclusive in the same \code{when} chain:
+
+\begin{scala}
+val ram1p = 
+  Mem(UInt(width = 32), 1024, seqRead = true)
+val reg_raddr = Reg(UInt())
+when (wen) { ram1p(waddr) := wdata }
+.elsewhen (ren) { reg_raddr := raddr }
+val rdata = ram1p(reg_raddr)
+\end{scala}
+
+If the same \code{Mem} address is both written and sequentially read on the same clock
+edge, or if a sequential read enable is cleared, then the read data is
+undefined.
+
+\code{Mem} also supports write masks for subword writes.  A given bit is written if
+the corresponding mask bit is set.
+
+\begin{scala}
+val ram = Mem(UInt(width = 32), 256)
+when (wen) { ram.write(waddr, wdata, wmask) }
+\end{scala}
+
+
+% For example, an
+% audio recorder could be defined as follows:
+% 
+% \begin{scala}
+%   def audioRecorder(n: Int, button: Bool) = { 
+%     val addr   = counter(UInt(n))
+%     val ram    = Mem(n)
+%     ram(addr) := button
+%     ram(Mux(button(), UInt(0), addr))
+%   } 
+% \end{scala}
+% 
+% \noindent
+% where a counter is used as an address generator into a memory.  
+% The device records while \verb+button+ is \verb+true+, or plays back when \verb+false+.
+
+
+\section{Interfaces and Bulk Connections}
+\label{sec:interfaces}
+
+For more sophisticated modules it is often useful to define and
+instantiate interface classes while defining the IO for a module.  First and
+foremost, interface classes promote reuse allowing users to capture
+once and for all common interfaces in a useful form.  Secondly,
+interfaces allow users to dramatically reduce wiring by supporting
+{\em bulk connections} between producer and consumer modules.  Finally,
+users can make changes in large interfaces in one place reducing the
+number of updates required when adding or removing pieces of the
+interface.
+
+\subsection{Port Classes, Subclasses, and Nesting}
+
+As we saw earlier, users can define their own interfaces by defining a class that subclasses \verb+Bundle+.  
+For example, a user could define a simple link for handshaking data as follows:
+
+\begin{scala}
+class SimpleLink extends Bundle { 
+  val data  = UInt(16, OUTPUT) 
+  val valid = Bool(OUTPUT)
+}
+\end{scala}
+
+\noindent
+We can then extend \verb+SimpleLink+ by adding parity bits using
+bundle inheritance:
+
+\begin{scala}
+class PLink extends SimpleLink { 
+  val parity = UInt(5, OUTPUT) 
+}
+\end{scala}
+
+\noindent
+In general, users can organize their interfaces into hierarchies using inheritance.  
+
+From there we can define a filter interface by nesting two
+\verb+PLink+s into a new \verb+FilterIO+ bundle:
+
+\begin{scala}
+class FilterIO extends Bundle { 
+  val x = new PLink().flip
+  val y = new PLink()
+}
+\end{scala}
+
+\noindent
+where \verb+flip+ recursively changes the ``gender'' of a bundle,
+changing input to output and output to input.
+
+We can now define a filter by defining a filter class extending module:
+
+\begin{scala}
+class Filter extends Module { 
+  val io = new FilterIO()
+  ...
+}
+\end{scala}
+
+\noindent 
+where the \verb+io+ field contains \verb+FilterIO+. 
+
+\subsection{Bundle Vectors}
+
+Beyond single elements, vectors of elements form richer hierarchical interfaces.  
+For example, in order to create a crossbar with a vector of inputs, producing a vector of outputs, and selected by a UInt input, 
+we utilize the \verb+Vec+ constructor:
+
+\begin{scala}
+class CrossbarIo(n: Int) extends Bundle {
+  val in  = Vec.fill(n){ new PLink().flip() }
+  val sel = UInt(INPUT, sizeof(n))
+  val out = Vec.fill(n){ new PLink() }
+}
+\end{scala}
+
+% \begin{scala}
+% class CrossbarIo(n: Int) extends Bundle {
+%   val in  = Vec.fill(n){ UInt(w, INPUT) }
+%   val sel = Vec.fill(n){ UInt(sizeof(n),  INPUT) }
+%   val out = Vec.fill(n){ UInt(w, OUTPUT) }
+% }
+% \end{scala}
+
+\noindent
+where \verb+Vec+ takes a size as the first argument and a block returning a port as the second argument.
+
+\subsection{Bulk Connections}
+
+We can now compose two filters into a filter block as follows:
+
+\begin{scala}
+class Block extends Module { 
+  val io = new FilterIO()
+  val f1 = Module(new Filter())
+  val f2 = Module(new Filter())
+
+  f1.io.x <> io.x
+  f1.io.y <> f2.io.x
+  f2.io.y <> io.y
+}
+\end{scala}
+
+\noindent
+where \verb+<>+ bulk connects interfaces of opposite gender between
+sibling modules or interfaces of same gender between parent/child modules. 
+Bulk connections connect leaf ports of the same name to each other.
+After all connections are made and the circuit is being elaborated,
+Chisel warns users if ports have other than exactly one connection to them.
+
+\subsection{Interface Views}
+
+\begin{figure}
+\centerline{\includegraphics[width=3in]{figs/cpu.png}}
+\caption{Simple CPU involving control and data path submodules and host and memory interfaces.}
+\label{fig:cpu}
+\end{figure}
+
+Consider a simple CPU consisting of control path and data path submodules and host and memory interfaces shown in Figure~\ref{fig:cpu}.
+In this CPU we can see that the control path and data path each connect only to a part of the instruction and data memory interfaces. 
+Chisel allows users to do this with partial fulfillment of interfaces.
+A user first defines the complete interface to a ROM and Mem as follows:
+
+\begin{scala}
+class RomIo extends Bundle {
+  val isVal = Bool(INPUT)
+  val raddr = UInt(INPUT, 32)
+  val rdata = UInt(OUTPUT, 32)
+}
+
+class RamIo extends RomIo {
+  val isWr  = Bool(INPUT)
+  val wdata = UInt(INPUT, 32)
+}
+\end{scala}
+
+\noindent
+Now the control path can build an interface in terms of these interfaces:
+
+\begin{scala}
+class CpathIo extends Bundle {
+  val imem = RomIo().flip()
+  val dmem = RamIo().flip()
+  ...
+}
+\end{scala}
+
+\noindent
+and the control and data path modules can be built by partially assigning to
+this interfaces as follows:
+
+\begin{scala}
+class Cpath extends Module {
+  val io = new CpathIo();
+  ...
+  io.imem.isVal := ...;
+  io.dmem.isVal := ...;
+  io.dmem.isWr  := ...;
+  ...
+}
+
+class Dpath extends Module {
+  val io = new DpathIo();
+  ...
+  io.imem.raddr := ...;
+  io.dmem.raddr := ...;
+  io.dmem.wdata := ...;
+  ...
+}
+\end{scala}
+
+\noindent
+We can now wire up the CPU using bulk connects as we would with other bundles:
+
+\begin{scala}
+class Cpu extends Module {
+  val io = new CpuIo()
+  val c  = Module(new CtlPath())
+  val d  = Module(new DatPath())
+  c.io.ctl  <> d.io.ctl
+  c.io.dat  <> d.io.dat
+  c.io.imem <> io.imem
+  d.io.imem <> io.imem
+  c.io.dmem <> io.dmem
+  d.io.dmem <> io.dmem
+  d.io.host <> io.host
+}
+\end{scala}
+
+\noindent
+Repeated bulk connections of partially assigned control and data path interfaces
+completely connect up the CPU interface.
+
+% A Bool can be automatically treated as a single bit UInt (with values
+% 0 or 1), but an Int or UInt cannot be used as a Bool without an
+% explicit cast.
+%
+%   Lit(5) // means a constant node with decimal value 5. Bit width will
+%           // be inferred automatically if possible
+%
+% A node is a hardware operator that has zero or more inputs and that
+% drives one output.  An example of a node with zero inputs is a
+% constant generator.
+%
+% \begin{scala}
+% Lit(10, 4) // means a constant node of type UInt that is 4 bits
+%            // wide with decimal 10.
+% Lit(10)
+% LitInt(10, 4)
+% LitUInt(10, 4)
+% Lit(-1,4)
+% \end{scala}
+%
+% can more concisely write:
+%
+% Module correspond to Verilog modules
+% Cell is a sub-module, Chisel Module
+
+\section{Functional Creation of Modules}
+\label{sec:funconstructor}
+
+It is also useful to be able to make a functional interface for
+module construction.  For instance, we could build a constructor
+that takes multiplexer inputs as parameters and returns the
+multiplexer output:
+
+\begin{scala}
+object Mux2 {
+  def apply (sel: UInt, in0: UInt, in1: UInt) = {
+    val m = new Mux2()
+    m.io.in0 := in0
+    m.io.in1 := in1
+    m.io.sel := sel
+    m.io.out
+  }
+}
+\end{scala}
+
+\noindent
+where \code{object Mux2} creates a Scala singleton object on the \code{Mux2}
+module class, and \code{apply} defines a method for creation of a \code{Mux2} instance.
+%
+With this \code{Mux2} creation function, the specification of \code{Mux4} now is
+significantly simpler.
+
+\begin{scala}
+class Mux4 extends Module {
+  val io = new Bundle {
+    val in0 = UInt(INPUT, 1)
+    val in1 = UInt(INPUT, 1)
+    val in2 = UInt(INPUT, 1)
+    val in3 = UInt(INPUT, 1)
+    val sel = UInt(INPUT, 2)
+    val out = UInt(OUTPUT, 1)
+  }
+  io.out := Mux2(io.sel(1),
+                 Mux2(io.sel(0), io.in0, io.in1),
+                 Mux2(io.sel(0), io.in2, io.in3))
+}
+\end{scala}
+
+Selecting inputs is so useful that Chisel builds it in and calls it
+\code{Mux}.  However, unlike \code{Mux2} defined above, the builtin version allows any datatype on
+\code{in0} and \code{in1} as long as they have a common super class.
+In Section~\ref{sec:parameterization} we will see how to define this
+ourselves.
+
+Chisel provides \code{MuxCase} which is an n-way \code{Mux} 
+\begin{scala}
+MuxCase(default, Array(c1 -> a, c2 -> b, ...))
+\end{scala}
+ 
+\noindent
+where each condition / value is represented as a tuple in a Scala
+array and where \code{MuxCase} can be translated into the following
+\code{Mux} expression:
+
+\begin{scala}
+Mux(c1, a, Mux(c2, b, Mux(..., default)))
+\end{scala}
+
+\noindent
+Chisel also provides \code{MuxLookup} which is an n-way indexed multiplexer:
+
+\begin{scala}
+MuxLookup(idx, default, 
+          Array(UInt(0) -> a, UInt(1) -> b, ...))
+\end{scala}
+
+\noindent
+which can be rewritten in terms of:\verb+MuxCase+ as follows:
+
+\begin{scala}
+MuxCase(default, 
+        Array((idx === UInt(0)) -> a, 
+              (idx === UInt(1)) -> b, ...))
+\end{scala}
+
+\noindent
+Note that the cases (eg. c1, c2) must be in parentheses.
+
+% TODO: higher order filter
+
+% \Noindent
+% where the overall expression returns the value corresponding to the first condition evaluating to true.
+
+% FUNCTIONAL CREATION
+%
+% want to go from io to constructor
+%
+% \begin{scala}
+% val io = new Bundle{
+%   val sel = UInt(INPUT, 1)
+%   val in0 = UInt(INPUT, 1)
+%   val in1 = UInt(INPUT, 1)
+%   val out = UInt(OUTPUT, 1)
+% }
+% def Mux2(sel: UInt, in0: UInt, in0: UInt): UInt = {
+%   val m = new Mux2()
+%   m.io.wire(Array("sel" => sel, "in0" => in0, "in1" => in1), "out")
+% }
+% \end{scala}
+
+% picture of box in box
+
+
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\section{Polymorphism and Parameterization}
+\label{sec:parameterization}
+
+Scala is a strongly typed language and uses parameterized types to specify generic functions and classes.  
+In this section, we show how Chisel users can define their own reusable functions and classes using parameterized classes.
+\begin{commentary}
+This section is advanced and can be skipped at first reading.
+\end{commentary}
+
+\subsection{Parameterized Functions}
+
+Earlier we defined \code{Mux2} on \code{Bool}, but now we show how we can define a generic multiplexer function.
+We define this function as taking a boolean condition and con and alt arguments (corresponding to then and else expressions) of type \code{T}:
+
+\begin{scala}
+def Mux[T <: Bits](c: Bool, con: T, alt: T): T { ... }
+\end{scala}
+
+\noindent
+where \code{T} is required to be a subclass of \code{Bits}.
+Scala ensures that in each usage of \code{Mux}, it can find a common superclass of the actual con and alt argument types, 
+otherwise it causes a Scala compilation type error.
+For example,
+
+\begin{scala}
+Mux(c, UInt(10), UInt(11))
+\end{scala}
+
+\noindent
+yields a \code{UInt} wire because the \code{con} and \code{alt} arguments are each of type \code{UInt}.
+
+% Earlier we defined \code{Mux2} on \code{Bool}, but now we show how we can define a generic \code{Mux}.  
+% We define a function that takes a condition and two functions of no arguments (called thunks) for the {\it then} and {\it else} cases:
+% 
+% \begin{scala}
+% def Mux[T <: UInt](c: Bool, con: T, alt: T): T
+% def Mux[T <: UInt](c: Bool)(con: => T)(alt: => T): T
+% \end{scala}
+% 
+% \noindent
+% where the two thunk return types are parameterized to be a type \code{T} that is a subclass of \code{UInt}.
+% Scala ensures that it finds a common superclass of the two thunks' return types.
+
+We now present a more advanced example of parameterized functions for defining an inner product FIR digital filter generically over Chisel \code{Num}'s.
+The inner product FIR filter can be mathematically defined as:
+\begin{equation}
+y[t] = \sum_j w_j * x_j[t-j]
+\end{equation}
+
+\noindent 
+where $x$ is the input and $w$ is a vector of weights.
+In Chisel this can be defined as:
+
+% MS: just out of curiosity: does this example generate several delay lines?
+\begin{scala}
+def delays[T <: Data](x: T, n: Int): List[T] = 
+  if (n <= 1) List(x) else x :: Delays(RegNext(x), n-1)
+
+def FIR[T <: Data with Num[T]](ws: Seq[T], x: T): T = 
+  (ws, Delays(x, ws.length)).zipped.
+    map( _ * _ ).reduce( _ + _ )
+\end{scala}
+ 
+\noindent
+where 
+\code{delays} creates a list of incrementally increasing delays of its input and
+\code{reduce} constructs a reduction circuit given a binary combiner function \code{f}.  
+In this case, \code{reduce} creates a summation circuit.
+Finally, the \code{FIR} function is constrained to work on inputs of type \code{Num} where Chisel multiplication and addition are defined.
+
+\subsection{Parameterized Classes}
+
+Like parameterized functions, we can also parameterize classes to make them more reusable.
+For instance, we can generalize the Filter class to use any kind of link.  
+We do so by parameterizing the \verb+FilterIO+ class and defining the constructor to take a zero argument type constructor function as follow:
+
+\begin{scala}
+class FilterIO[T <: Data](type: T) extends Bundle { 
+  val x = type.asInput.flip
+  val y = type.asOutput
+}
+\end{scala}
+
+\noindent
+We can now define \verb+Filter+ by defining a module class that also takes a link type constructor argument and passes it through to the \verb+FilterIO+ interface constructor:
+
+\begin{scala}
+class Filter[T <: Data](type: T) extends Module { 
+  val io = new FilterIO(type)
+  ...
+}
+\end{scala}
+
+\noindent
+We can now define a \verb+PLink+ based \verb+Filter+ as follows:
+\begin{scala}
+val f = Module(new Filter(new PLink()))
+\end{scala}
+
+\noindent
+where the curly braces \verb+{ }+ denote a zero argument function (aka thunk) that in this case creates the link type.
+
+A generic FIFO could be defined as shown in Figure~\ref{fig:fifo} and
+used as follows:
+
+\begin{scala}
+class DataBundle extends Bundle {
+  val A = UInt(width = 32)
+  val B = UInt(width = 32)
+}
+
+object FifoDemo {
+  def apply () = new Fifo(new DataBundle, 32)
+}
+\end{scala}
+
+\begin{figure}[ht]
+\begin{scala}
+class Fifo[T <: Data] (type: T, n: Int) 
+    extends Module {
+  val io = new Bundle {
+    val enq_val = Bool(INPUT)
+    val enq_rdy = Bool(OUTPUT)
+    val deq_val = Bool(OUTPUT)
+    val deq_rdy = Bool(INPUT)
+    val enq_dat = type.asInput
+    val deq_dat = type.asOutput
+  }
+  val enq_ptr      = Reg(init = UInt(0, sizeof(n)))
+  val deq_ptr      = Reg(init = UInt(0, sizeof(n)))
+  val is_full      = Reg(init = Bool(false))
+  val do_enq       = io.enq_rdy && io.enq_val
+  val do_deq       = io.deq_rdy && io.deq_val
+  val is_empty     = !is_full && (enq_ptr === deq_ptr)
+  val deq_ptr_inc  = deq_ptr + UInt(1)
+  val enq_ptr_inc  = enq_ptr + UInt(1)
+  val is_full_next = 
+    Mux(do_enq && ~do_deq && (enq_ptr_inc === deq_ptr), 
+        Bool(true),
+        Mux(do_deq && is_full, Bool(false), is_full))
+  enq_ptr := Mux(do_enq, enq_ptr_inc, enq_ptr)
+  deq_ptr := Mux(do_deq, deq_ptr_inc, deq_ptr)
+  is_full := is_full_next
+  val ram = Mem(n)
+  when (do_enq) {
+    ram(enq_ptr) := io.enq_dat
+  }
+  io.enq_rdy := !is_full
+  io.deq_val := !is_empty
+  ram(deq_ptr) <> io.deq_dat
+}
+\end{scala}
+\caption{Parameterized FIFO example.}
+\label{fig:fifo}
+\end{figure}
+
+It is also possible to define a generic decoupled interface:
+
+\begin{scala}
+class DecoupledIO[T <: Data](data: T) 
+    extends Bundle {
+  val ready = Bool(INPUT)
+  val valid = Bool(OUTPUT)
+  val bits  = data.clone.asOutput
+}
+\end{scala}
+
+\noindent
+This template can then be used to add a handshaking protocol to any
+set of signals:
+
+\begin{scala}
+class DecoupledDemo 
+  extends DecoupledIO()( new DataBundle )
+\end{scala}
+
+\noindent
+The FIFO interface in Figure~\ref{fig:fifo} can be now be simplified as
+follows: 
+
+\begin{scala}
+class Fifo[T <: Data] (data: T, n: Int) 
+    extends Module {
+  val io = new Bundle {
+    val enq = new DecoupledIO( data ).flip()
+    val deq = new DecoupledIO( data )
+  }
+  ...
+}
+\end{scala}
+
+
+\section{Multiple Clock Domains}
+
+Chisel 2.0 introduces support of multiple clock domains.  
+
+\subsection{Creating Clock domains}
+
+In order to use multiple clock domains, users must create multiple clocks.  
+In Chisel, clocks are first class nodes created with a reset signal parameter and defined as follows:
+
+\begin{scala}
+class Clock (reset: Bool) extends Node {
+  def reset: Bool // returns reset pin
+}
+\end{scala}
+
+\noindent
+% Having reset in clock makes it easier to pass around.
+In Chisel there is a builtin implicit clock that state elements use by default:
+
+\begin{scala}
+var implicitClock = new Clock( implicitReset )
+\end{scala}
+
+The clock for state elements and modules can be defined using an additional named parameter called clock:
+
+\begin{scala}
+Reg(... clock: Clock = implicitClock)
+Mem(... clock: Clock = implicitClock)
+Module(... clock: Clock = implicitClock)
+\end{scala}
+
+\subsection{Crossing Clock Domains}
+
+There are two ways that circuits can be defined to send data between clock domains.
+The first and most primitive way is by using a synchronizer circuit comprised of two registers as follows:
+
+\begin{scala}
+// signalA is in clock domain clockA, 
+// want a version in clockB as signalB
+val s1 = Reg(init = UInt(0), clock = clockB)
+val s2 = Reg(init = UInt(0), clock = clockB)
+s1      := signalA
+s2      := s1; 
+signalB := s2
+\end{scala}
+
+\noindent
+Due to metastability issues, this technique is limited to communicating one bit data between domains.
+
+The second and more general way to send data between domains is by using an asynchronous fifo:
+
+\begin{scala}
+class AsyncFifo[T<:Data]
+    (gen: T, entries: Int, enq_clk: Clock, deq_clock: Clock)
+  extends Module
+\end{scala}
+
+\noindent
+When get a version of signalA from clock domains clockA to clockB by
+specifying the standard fifo parameters and the two clocks and then using the
+standard decoupled ready/valid signals:
+
+\begin{scala}
+val fifo =
+  new AsyncFifo(Uint(width = 32), 2, clockA, clockB)
+fifo.io.enq.bits  := signalA
+signalB           := fifo.io.deq.bits
+fifo.io.enq.valid := condA
+fifo.io.deq.ready := condB
+...
+\end{scala}
+
+\subsection{Backend Specific Multiple Clock Domains}
+
+Each Chisel backend requires the user to setup and control multiple clocks
+in a backend specific manner.  For the purposes of showing how to drive a
+multi clock design, consider the example of hardware with two modules
+communicating using an AsyncFifo with each module on separate clocks:
+\verb+fastClock+ and \verb+slowClock+.
+
+\subsubsection{C++}
+
+%MS: looks like the generated clock code is now a little bit different.
+In the C++ backend, for every clock \verb+i+ there is a
+\begin{itemize}
+\item \verb+size_t clk+.len field representing the clock \verb+i+'s period,
+\item \verb+clock_lo_i+ and \verb+clock_hi_i+, 
+\item \verb+int reset()+ function which ensures that all \verb+clock_lo+ and \verb+clock_hi+ functions are called at least once, and
+\item \verb+int clock(reset)+ function which computes min delta, invokes appropriate \verb+clock_lo+ and \verb+clock_hi+'s and returns min delta used.
+\end{itemize}
+
+\noindent
+In order to set up a C++ simulation, the user 
+\begin{itemize}
+\item initializes all period fields to desired period
+\item initializes all count fields to desired phase, 
+\item calls \verb+reset+ and then
+\item repeated calls clock to step the simulation.
+\end{itemize}
+
+\noindent
+The following is a C++ example of a main function for the \verb+slowClock+ / \verb+fastClock+ example:
+
+\begin{scala}
+int main(int argc, char** argv) {
+  ClkDomainTest_t dut;
+  dut.init(1);
+  dut.clk = 2;
+  dut.clk_cnt = 1;
+  dut.fastClock = 4;
+  dut.fastClock_cnt = 0;
+  dut.slowClock = 6;
+  dut.slowClock_cnt = 0;
+  for (int i = 0; i < 12; i ++) 
+    dut.reset();
+  for (int i = 0; i < 96; i ++) 
+    dut.clock(LIT<1>(0));
+}
+\end{scala}
+
+\subsubsection{Verilog}
+
+In Verilog, 
+
+\begin{itemize}
+\item Chisel creates a new port for each clock / reset,
+\item Chisel wires all the clocks to the top module, and
+\item the user must create an \verb+always+ block clock driver for every clock \verb+i+.
+\end{itemize}
+
+\noindent
+The following is a Verilog example of a top level harness to drive the  \verb+slowClock+ / \verb+fastClock+ example circuit:
+
+\begin{scala}
+module emulator;
+  reg fastClock = 0, slowClock = 0, 
+      resetFast = 1, resetSlow = 1;
+  wire [31:0] add, mul, test;
+  always #2 fastClock = ~fastClock;
+  always #4 slowClock = ~slowClock;
+  initial begin
+     #8 
+     resetFast = 0;
+     resetSlow = 0;
+     #400
+     $finish;
+  end
+  ClkDomainTest dut (
+     .fastClock(fastClock),
+     .slowClock(slowClock),
+     .io_resetFast(resetFast),
+     .io_resetSlow(resetSlow),
+     .io_add(add), .io_mul(mul), .io_test(test));
+endmodule
+\end{scala}
+
+\noindent
+See \url{http://www.asic-world.com/verilog/verifaq2.html} for more information about simulating clocks in Verilog.
+
+\section{Acknowlegements}
+
+Many people have helped out in the design of Chisel, and we thank them
+for their patience, bravery, and belief in a better way.  Many
+Berkeley EECS students in the Isis group gave weekly feedback as the
+design evolved including but not limited to Yunsup Lee, Andrew
+Waterman, Scott Beamer, Chris Celio, etc.  Yunsup Lee gave us feedback
+in response to the first RISC-V implementation, called TrainWreck,
+translated from Verilog to Chisel.  Andrew Waterman and Yunsup Lee
+helped us get our Verilog backend up and running and Chisel TrainWreck
+running on an FPGA.  Brian Richards was the first actual Chisel user,
+first translating (with Huy Vo) John Hauser's FPU Verilog code to
+Chisel, and later implementing generic memory blocks.  Brian gave many
+invaluable comments on the design and brought a vast experience in
+hardware design and design tools.  Chris Batten shared his fast
+multiword C++ template library that inspired our fast emulation
+library.  Huy Vo became our undergraduate research assistant and was
+the first to actually assist in the Chisel implementation.  We
+appreciate all the EECS students who participated in the Chisel
+bootcamp and proposed and worked on hardware design projects all of
+which pushed the Chisel envelope.  We appreciate the work that James
+Martin and Alex Williams did in writing and translating network and
+memory controllers and non-blocking caches.  Finally, Chisel's
+functional programming and bit-width inference ideas were inspired by
+earlier work on a hardware description language called Gel~\cite{gel} designed in
+collaboration with Dany Qumsiyeh and Mark Tobenkin.
+
+% \note{Who else?}
+
+\begin{thebibliography}{50}
+\bibitem{chisel-dac12} Bachrach, J., Vo, H., Richards, B., Lee, Y., Waterman,
+  A., Avi\v{z}ienis, Wawrzynek, J., Asanovi\'{c} \textsl{Chisel:
+    Constructing Hardware in a Scala Embedded Language}.
+in DAC '12.
+\bibitem{gel} Bachrach, J., Qumsiyeh, D., Tobenkin, M. \textsl{Hardware Scripting in Gel}.
+in Field-Programmable Custom Computing Machines, 2008. FCCM '08. 16th.
+\end{thebibliography}
+
+\end{document}
diff --git a/chisel/Buraq-mini/RV32i/doc/tutorial/tutorial.tex b/chisel/Buraq-mini/RV32i/doc/tutorial/tutorial.tex
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+\documentclass[twocolumn,10pt]{article}
+\setlength\textwidth{6.875in}
+\setlength\textheight{8.875in}
+% set both margins to 2.5 pc
+\setlength{\oddsidemargin}{-0.1875in}% 1 - (8.5 - 6.875)/2
+\setlength{\evensidemargin}{-0.1875in}
+\setlength{\marginparwidth}{0pc}
+\setlength{\marginparsep}{0pc}%
+\setlength{\topmargin}{0in} \setlength{\headheight}{0pt}
+\setlength{\headsep}{0pt}
+\setlength{\footskip}{37pt}%
+%\setlength{\columnsep}{0.3125in}
+%\setlength{\columnwidth}{3.28125in}% (6.875 - 0.3125)/2 = 3.28125in
+\setlength{\parindent}{1pc}
+\newcommand{\myMargin}{1.00in}
+\usepackage[top=\myMargin, left=\myMargin, right=\myMargin, bottom=\myMargin, nohead]{geometry}
+\usepackage{epsfig,graphicx}
+\usepackage{palatino}
+\usepackage{fancybox}
+\usepackage{url}
+\usepackage[procnames]{listings}
+
+\input{../style/scala.tex}
+
+\lstset{frame=, basicstyle={\footnotesize\ttfamily}}
+
+\newcommand{\todo}[1]{\emph{TODO: #1}}
+\newcommand{\comment}[1]{\emph{Comment: #1}}
+
+% uncomment following for final submission
+\renewcommand{\todo}[1]{}
+\renewcommand{\comment}[1]{}
+
+\newenvironment{commentary}
+{ \vspace{-0.1in}
+  \begin{quotation}
+  \noindent
+  \small \em
+  \rule{\linewidth}{1pt}\\
+}
+{
+  \end{quotation}
+}
+
+% \newenvironment{kode}%
+% {\footnotesize
+%  %\setlength{\parskip}{0pt}
+%   %\setlength{\topsep}{0pt}
+%   %\setlength{\partopsep}{0pt}
+%  \verbatim}
+% {\endverbatim 
+% %\vspace*{-0.1in}
+%  }
+
+% \newenvironment{kode}%
+% {\VerbatimEnvironment
+% \footnotesize\begin{Sbox}\begin{minipage}{6in}\begin{Verbatim}}%
+% {\end{Verbatim}\end{minipage}\end{Sbox}
+% \setlength{\fboxsep}{8pt}\fbox{\TheSbox}}
+
+% \newenvironment{kode}
+% {\begin{Sbox}
+% \footnotesize
+% \begin{minipage}{6in}
+%   %\setlength{\parskip}{0pt}
+%   %\setlength{\topsep}{0pt}
+%   %\setlength{\partopsep}{0pt}
+%   \verbatim}
+% {\endverbatim 
+% \end{minipage}
+% \end{Sbox} 
+% \fbox{\TheSbox}
+%  %\vspace*{-0.1in}
+%  }
+
+\title{Chisel 3.0 Tutorial (Beta)}
+\author{Jonathan Bachrach, Krste Asanovi\'{c}, John Wawrzynek \\
+EECS Department, UC Berkeley\\
+{\tt  \{jrb|krste|johnw\}@eecs.berkeley.edu}
+}
+\date{\today}
+
+\newenvironment{example}{\VerbatimEnvironment\begin{footnotesize}\begin{Verbatim}}{\end{Verbatim}\end{footnotesize}}
+\newcommand{\kode}[1]{\begin{footnotesize}{\tt #1}\end{footnotesize}}
+
+\def\code#1{{\tt #1}}
+
+\def\note#1{\noindent{\bf [Note: #1]}}
+%\def\note#1{}
+
+\begin{document}
+\maketitle{}
+
+% TODO: default
+% TODO: enum yields Bits
+% TODO: why hardware construction languages
+
+\section{Introduction}
+
+This document is a tutorial introduction to {\em Chisel} (Constructing
+Hardware In a Scala Embedded Language).  Chisel is a hardware
+construction language embedded in the high-level programming language
+Scala.  At some point we will provide a proper reference manual, in
+addition to more tutorial examples.  In the meantime, this document
+along with a lot of trial and error should set you on your way to
+using Chisel.  Chisel is really only a set of special class
+definitions, predefined objects, and usage conventions within Scala,
+so when you write a Chisel program you are actually writing a Scala
+program.  However, for the tutorial we don't presume that you
+understand how to program in Scala.  We will point out necessary Scala
+features through the Chisel examples we give, and significant hardware
+designs can be completed using only the material contained herein.
+But as you gain experience and want to make your code simpler or more
+reusable, you will find it important to leverage the underlying power
+of the Scala language. We recommend you consult one of the excellent
+Scala books to become more expert in Scala programming.
+
+% MS: maybe infancy can now be dropped. Chisel has proven
+% to be mature enough for serious designs.
+Chisel is still in its infancy and you are likely to encounter some
+implementation bugs, and perhaps even a few conceptual design
+problems.  However, we are actively fixing and improving the language,
+and are open to bug reports and suggestions.  Even in its early state,
+we hope Chisel will help designers be more productive in building
+designs that are easy to reuse and maintain.
+
+\begin{commentary}
+Through the tutorial, we format commentary on our design choices as in
+this paragraph.  You should be able to skip the commentary sections
+and still fully understand how to use Chisel, but we hope you'll find
+them interesting.
+
+We were motivated to develop a new hardware language by years of
+struggle with existing hardware description languages in our research
+projects and hardware design courses.  Verilog and VHDL were developed
+as hardware {\em simulation} languages, and only later did they become
+a basis for hardware {\em synthesis}.  Much of the semantics of these
+languages are not appropriate for hardware synthesis and, in fact,
+many constructs are simply not synthesizable.  Other constructs are
+non-intuitive in how they map to hardware implementations, or their
+use can accidentally lead to highly inefficient hardware structures.
+While it is possible to use a subset of these languages and yield
+acceptable results, they nonetheless present a cluttered and confusing
+specification model, particularly in an instructional setting.
+
+However, our strongest motivation for developing a new hardware
+language is our desire to change the way that electronic system design
+takes place.  We believe that it is important to not only teach
+students how to design circuits, but also to teach them how to design
+{\em circuit generators}---programs that automatically generate
+designs from a high-level set of design parameters and constraints.
+Through circuit generators, we hope to leverage the hard work of
+design experts and raise the level of design abstraction for everyone.
+To express flexible and scalable circuit construction, circuit
+generators must employ sophisticated programming techniques to make
+decisions concerning how to best customize their output circuits
+according to high-level parameter values and constraints.  While
+Verilog and VHDL include some primitive constructs for programmatic
+circuit generation, they lack the powerful facilities present in
+modern programming languages, such as object-oriented programming,
+type inference, support for functional programming, and reflection.
+
+Instead of building a new hardware design language from scratch, we
+chose to embed hardware construction primitives within an existing
+language.  We picked Scala not only because it includes the
+programming features we feel are important for building circuit
+generators, but because it was specifically developed as a base for
+domain-specific languages.
+\end{commentary}
+
+\section{Hardware expressible in Chisel}
+
+% The initial version of Chisel only supports the expression of
+% synchronous RTL (Register-Transfer Level) designs, with a single
+% common clock.  Synchronous RTL circuits can be expressed as a
+% hierarchical composition of modules containing combinational logic and
+% clocked state elements.  Although Chisel assumes a single global
+% clock, local clock gating logic is automatically generated for every
+% state element in the design to save power.
+% \begin{commentary}
+% Modern hardware designs often include multiple islands of logic, where
+% each island uses a different clock and where islands must correctly
+% communicate across clock island boundaries.  Although clock-crossing
+% synchronization circuits are notoriously difficult to design, there
+% are known good solutions for most scenarios, which can be packaged as
+% library elements for use by designers.  As a result, most effort in
+% new designs is spent in developing and verifying the functionality
+% within each synchronous island rather than on passing values between
+% islands.
+% 
+% In its current form, Chisel can be used to describe each of the
+% synchronous islands individually. Existing tool frameworks can tie
+% together these islands into a complete design.  For example, a
+% separate outer simulation framework can be used to model the assembly
+% of islands running together.  It should be noted that exhaustive
+% dynamic verification of asynchronous communications is usually
+% impossible and that more formal static approaches are usually
+% necessary.
+% \end{commentary}
+
+This version of Chisel only supports binary logic, and does not
+support tri-state signals.
+\begin{commentary}
+We focus on binary logic designs as they constitute the vast majority
+of designs in practice.  We omit support for tri-state logic in the
+current Chisel language as this is in any case poorly supported by
+industry flows, and difficult to use reliably outside of controlled
+hard macros.
+\end{commentary}
+
+\section{Datatypes in Chisel}
+
+Chisel datatypes are used to specify the type of values held in state
+elements or flowing on wires.  While hardware designs ultimately
+operate on vectors of binary digits, other more abstract
+representations for values allow clearer specifications and help the
+tools generate more optimal circuits.  In Chisel, a raw collection of
+bits is represented by the \code{Bits} type.  Signed and unsigned integers
+are considered subsets of fixed-point numbers and are represented by
+types \code{SInt} and \code{UInt} respectively. Signed fixed-point
+numbers, including integers, are represented using two's-complement
+format.  Boolean values are represented as type \code{Bool}.  Note
+that these types are distinct from Scala's builtin types such as
+\code{Int} or \code{Boolean}.  Additionally, Chisel defines {\em Bundles} for making
+collections of values with named fields (similar to {\em structs} in
+other languages), and {\em Vecs} for indexable collections of
+values.  Bundles and Vecs will be covered later.
+
+Constant or literal values are expressed using Scala integers or
+strings passed to constructors for the types:
+\begin{scala}
+1.U       // decimal 1-bit lit from Scala Int.
+"ha".U    // hexadecimal 4-bit lit from string.
+"o12".U   // octal 4-bit lit from string.
+"b1010".U // binary 4-bit lit from string.
+
+5.S    // signed decimal 4-bit lit from Scala Int.
+-8.S   // negative decimal 4-bit lit from Scala Int.
+5.U    // unsigned decimal 3-bit lit from Scala Int.
+
+true.B // Bool lits from Scala lits.
+false.B
+\end{scala}
+
+By default, the Chisel compiler will size each constant to the minimum
+number of bits required to hold the constant, including a sign bit for
+signed types.  Bit widths can also be specified explicitly on
+literals, as shown below:
+\begin{scala}
+"ha".U(8.W)     // hexadecimal 8-bit lit of type UInt
+"o12".U(6.W)    // octal 6-bit lit of type UInt
+"b1010".U(12.W) // binary 12-bit lit of type UInt
+
+5.S(7.W) // signed decimal 7-bit lit of type SInt
+5.U(8.W) // unsigned decimal 8-bit lit of type UInt
+\end{scala}
+
+\noindent
+For literals of type \code{UInt}, the value is
+zero-extended to the desired bit width.  For literals of type
+\code{SInt}, the value is sign-extended to fill the desired bit width.
+If the given bit width is too small to hold the argument value, then a
+Chisel error is generated.
+
+\begin{commentary}
+We are working on a more concise literal syntax for Chisel using
+symbolic prefix operators, but are stymied by the limitations of Scala
+operator overloading and have not yet settled on a syntax that is
+actually more readable than constructors taking strings.
+
+We have also considered allowing Scala literals to be automatically
+converted to Chisel types, but this can cause type ambiguity and
+requires an additional import.
+
+The SInt and UInt types will also later support an optional exponent
+field to allow Chisel to automatically produce optimized fixed-point
+arithmetic circuits.
+\end{commentary}
+
+\section{Combinational Circuits}
+
+A circuit is represented as a graph of nodes in Chisel.  Each node is
+a hardware operator that has zero or more inputs and that drives one
+output.  A literal, introduced above, is a degenerate kind of node
+that has no inputs and drives a constant value on its output.  One way
+to create and wire together nodes is using textual expressions.  For
+example, we can express a simple combinational logic circuit
+using the following expression:
+
+\begin{scala}
+(a & b) | (~c & d)
+\end{scala}
+
+The syntax should look familiar, with \code{\&} and \code{|}
+representing bitwise-AND and -OR respectively, and \code{\~{}}
+representing bitwise-NOT.  The names \code{a} through \code{d}
+represent named wires of some (unspecified) width.
+
+Any simple expression can be converted directly into a circuit tree,
+with named wires at the leaves and operators forming the internal
+nodes.  The final circuit output of the expression is taken from the
+operator at the root of the tree, in this example, the bitwise-OR.
+
+Simple expressions can build circuits in the shape of trees, but to
+construct circuits in the shape of arbitrary directed acyclic graphs
+(DAGs), we need to describe fan-out.  In Chisel, we do this by naming
+a wire that holds a subexpression that we can then reference multiple
+times in subsequent expressions.  We name a wire in Chisel by
+declaring a variable.  For example, consider the select expression,
+which is used twice in the following multiplexer description:
+\begin{scala}
+val sel = a | b
+val out = (sel & in1) | (~sel & in0)
+\end{scala}
+
+\noindent
+The keyword \code{val} is part of Scala, and is used to name variables
+that have values that won't change.  It is used here to name the
+Chisel wire, \code{sel}, holding the output of the first bitwise-OR
+operator so that the output can be used multiple times in the second
+expression.
+
+\section{Builtin Operators}
+
+Chisel defines a set of hardware operators for the builtin types shown
+in Table~\ref{tbl:chisel-operators}.
+\begin{table*}
+\begin{center}
+\begin{tabular}{|l|l|}
+\hline
+Example & Explanation \\
+\hline
+\hline
+\multicolumn{2}{|l|}{Bitwise operators.  Valid on SInt, UInt, Bool.} \\
+\hline
+\hline
+\verb!val invertedX = ~x!                    &   Bitwise NOT  \\
+\verb!val hiBits = x & "h_ffff_0000".U ! &   Bitwise AND  \\
+\verb!val flagsOut = flagsIn | overflow !    &   Bitwise OR   \\
+\verb!val flagsOut = flagsIn ^ toggle !      &   Bitwise XOR  \\
+\hline
+\hline
+\multicolumn{2}{|l|}{Bitwise reductions.  Valid on SInt and
+  UInt.  Returns Bool. } \\
+\hline
+\hline
+\verb!val allSet = andR(x) ! & AND reduction  \\
+\verb!val anySet = orR(x)  ! & OR reduction   \\
+\verb!val parity = xorR(x) !  & XOR reduction  \\
+\hline
+\hline
+\multicolumn{2}{|l|}{Equality comparison. Valid on SInt, 
+UInt, and Bool. Returns Bool.} \\
+\hline
+\hline
+\verb@val equ = x === y@ & Equality \\
+\verb@val neq = x =/= y@ & Inequality \\
+\hline
+\hline
+\multicolumn{2}{|l|}{Shifts. Valid on SInt and UInt.} \\
+\hline
+\hline
+\verb@val twoToTheX = 1.S << x@  & Logical left shift. \\
+\verb@val hiBits = x >> 16.U@          & Right shift (logical on UInt and\&
+arithmetic on SInt). \\
+% \verb@val scaledX = x >>> 3@  & Arithmetic right shift, copies in sign bits. \\
+\hline
+\hline
+\multicolumn{2}{|l|}{Bitfield manipulation.  Valid on SInt, UInt, and Bool. } \\
+\hline
+\hline
+\verb@val xLSB = x(0)@  & Extract single bit, LSB has index 0. \\
+\verb@val xTopNibble = x(15,12)@  & Extract bit field  from end to start
+bit position. \\
+\verb@val usDebt = Fill(3, "hA".U)@ & Replicate a bit string multiple times. \\
+\verb@val float = Cat(sign,exponent,mantissa)@ & Concatenates bit fields, with first argument on left.\\
+\hline
+\hline
+\multicolumn{2}{|l|}{Logical operations.  Valid on Bools. } \\
+\hline
+\verb@val sleep = !busy@  & Logical NOT \\
+\verb@val hit = tagMatch && valid @  & Logical AND \\
+\verb@val stall = src1busy || src2busy@  & Logical OR \\
+\verb@val out = Mux(sel, inTrue, inFalse)@  & Two-input mux where sel is a Bool \\ % {\bf Why?} \\
+\hline
+\hline
+\multicolumn{2}{|l|}{Arithmetic operations.  Valid on Nums: SInt and UInt. } \\
+\hline
+\verb@val sum = a + b@  & Addition \\
+\verb@val diff = a - b @  & Subtraction \\
+\verb@val prod = a * b @  & Multiplication \\
+\verb@val div = a / b @  & Division \\
+\verb@val mod = a % b @  & Modulus \\
+\hline
+\hline
+\multicolumn{2}{|l|}{Arithmetic comparisons.  Valid on Nums: SInt and
+  UInt. Returns Bool.} \\
+\hline
+\verb@val gt = a > b@  & Greater than \\
+\verb@val gte = a >= b@  & Greater than or equal \\
+\verb@val lt = a < b@  & Less than \\
+\verb@val lte = a <= b@  & Less than or equal \\
+\hline
+\end{tabular}
+\end{center}
+\caption{Chisel operators on builtin data types.}
+\label{tbl:chisel-operators}
+\end{table*}
+
+\subsection{Bitwidth Inference}
+
+Users are required to set bitwidths of ports and registers, but otherwise,
+bit widths on wires are automatically inferred unless set manually by the user.
+% TODO: how do you set the width explicitly?
+The bit-width inference engine starts from the graph's input ports and 
+calculates node output bit widths from their respective input bit widths according to the following set of rules:
+
+\begin{tabular}{ll}
+{\bf operation} & {\bf bit width} \\ 
+\verb|z = x + y| & \verb|wz = max(wx, wy)| \\
+\verb+z = x - y+ & \verb|wz = max(wx, wy)|\\
+\verb+z = x & y+ & \verb+wz = min(wx, wy)+ \\
+\verb+z = Mux(c, x, y)+ & \verb+wz = max(wx, wy)+ \\
+\verb+z = w * y+ & \verb!wz = wx + wy! \\
+\verb+z = x << n+ & \verb!wz = wx + maxNum(n)! \\
+\verb+z = x >> n+ & \verb+wz = wx - minNum(n)+ \\
+\verb+z = Cat(x, y)+ & \verb!wz = wx + wy! \\
+\verb+z = Fill(n, x)+ & \verb+wz = wx * maxNum(n)+ \\
+% \verb+z = x < y+ & \verb+<= > >= && || != ===+ & \verb+wz = 1+ \\
+\end{tabular}
+
+\noindent
+where for instance $wz$ is the bit width of wire $z$, and the \verb+&+
+rule applies to all bitwise logical operations.
+
+\comment{maxNum and MinNum need to be explained.}
+
+The bit-width inference process continues until no bit width changes.
+Except for right shifts by known constant amounts, the bit-width
+inference rules specify output bit widths that are never smaller than
+the input bit widths, and thus, output bit widths either grow or stay
+the same.  Furthermore, the width of a register must be specified by
+the user either explicitly or from the bitwidth of the reset value or
+the \emph{next} parameter.
+From these two requirements, we can show that the bit-width inference
+process will converge to a fixpoint.
+
+\begin{commentary}
+Our choice of operator names was constrained by the Scala language.
+We have to use triple equals \code{===} for equality and \code{=/=}
+for inequality to allow the
+native Scala equals operator to remain usable.
+
+We are also planning to add further operators that constrain bitwidth
+to the larger of the two inputs.
+\end{commentary}
+
+\section{Functional Abstraction}
+
+We can define functions to factor out a repeated piece of logic that
+we later reuse multiple times in a design.  For example, we can wrap
+up our earlier example of a simple combinational logic block as
+follows:
+\begin{scala}
+def clb(a: UInt, b: UInt, c: UInt, d: UInt): UInt = 
+  (a & b) | (~c & d)
+\end{scala}
+
+\noindent
+where \code{clb} is the function which takes \code{a}, \code{b},
+\code{c}, \code{d} as arguments and returns a wire to the output of a
+boolean circuit.  The \code{def} keyword is part of Scala and
+introduces a function definition, with each argument followed by a colon then its type,
+and the function return type given after the colon following the
+argument list.  The equals (\code{=})
+sign separates the function argument list from the function
+definition.
+
+We can then use the block in another circuit as follows:
+\begin{scala}
+val out = clb(a,b,c,d)
+\end{scala}
+
+% TODO: SHIFTER DONE FUNCTIONAL WITH LOOP
+
+%% Because Scala has powerful type inference, we can in many cases drop
+%% the type declarations on the function:
+%% \begin{scala}
+%% def clb(a, b, c, d) = (a & b) | (~c & d) // No types needed.
+
+%% def bigblock(a: Bool, b: Bool, c: Bool, d: Bool,
+%%              f: UInt, g: UInt, h: UInt, i: UInt): Bool =
+%%                  clb(a, b, c, clb(f,g,h,i)!=0) 
+
+%% \end{scala}
+
+%% Here, we use \code{clb} twice.  The inner \verb!clb!  works with
+%% fixed-point values to calculate the value of an internal node that is
+%% compared with 0 to give a \code{Bool}, while the outer \verb!clb!
+%%   works with \code{Bool} values and returns the result of the
+%%   function.  Scala will perform type inference statically to check
+%%   that there are no type errors.
+
+We will later describe many powerful ways to use functions to
+construct hardware using Scala's functional programming support.
+
+\section{Bundles and Vecs}
+
+\code{Bundle} and \code{Vec} are classes that allow the user to expand
+the set of Chisel datatypes with aggregates of other types.
+
+Bundles group together several named fields of potentially different
+types into a coherent unit, much like a \code{struct} in C. Users
+define their own bundles by defining a class as a subclass of
+\code{Bundle}:
+\begin{scala}
+class MyFloat extends Bundle {
+  val sign        = Bool()
+  val exponent    = UInt(8.W)
+  val significand = UInt(23.W)
+}
+
+val x  = new MyFloat()
+val xs = x.sign
+\end{scala}
+
+\noindent
+A Scala convention is to capitalize the name of new classes and we
+suggest you follow that convention in Chisel too.  The \code{W}
+method converts a Scala \code{Int} to a Chisel \code{Width},
+specifying the number of bits in the type.
+
+Vecs create an indexable vector of elements, and are constructed as
+follows:
+\begin{scala}
+// Vector of 5 23-bit signed integers.
+val myVec = Vec(5, SInt(23.W))
+
+// Connect to one element of vector. 
+val reg3  = myVec(3) 
+\end{scala}
+
+\noindent
+(Note that we have to specify the type of the \code{Vec} elements
+inside the trailing curly brackets, as we have to pass the bitwidth
+parameter into the \code{SInt} constructor.)
+
+The set of primitive classes
+(\code{SInt}, \code{UInt}, and \code{Bool}) plus the aggregate
+classes (\code{Bundles} and \code{Vec}s) all inherit from a common
+superclass, \code{Data}.  Every object that ultimately inherits from
+\code{Data} can be represented as a bit vector in a hardware design.
+
+Bundles and Vecs can be arbitrarily nested to build complex data
+structures:
+\begin{scala}
+class BigBundle extends Bundle {
+ // Vector of 5 23-bit signed integers.
+ val myVec = Vec(5, SInt(23.W))
+ val flag  = Bool()
+ // Previously defined bundle.
+ val f     = new MyFloat()              
+}
+\end{scala}
+
+\noindent
+Note that the builtin Chisel primitive and aggregate classes do not
+require the \code{new} when creating an instance, whereas new user
+datatypes will.  A Scala \code{apply} constructor can be defined so
+that a user datatype also does not require \code{new}, as described in
+Section~\ref{sec:funconstructor}.
+
+\section{Ports}
+
+Ports are used as interfaces to hardware components.  A port is simply
+any \code{Data} object that has directions assigned to its members.
+
+Chisel provides port constructors to allow a direction to be added
+(input or output) to an object at construction time.
+Simply wrap the object in an \code{Input()} or
+\code{Output()} function.
+
+An example port declaration is as follows:
+\begin{scala}
+class Decoupled extends Bundle {
+  val ready = Output(Bool())
+  val data  = Input(UInt(32.W))
+  val valid = Input(Bool())
+}
+\end{scala}
+
+\noindent
+After defining \code{Decoupled}, it becomes a new type that can be
+used as needed for module interfaces or for named collections of
+wires.
+
+The direction of an object can also be assigned at instantation time:
+\begin{scala}
+class ScaleIO extends Bundle {
+  val in    = new MyFloat().asInput
+  val scale = new MyFloat().asInput
+  val out   = new MyFloat().asOutput
+}
+\end{scala}
+
+\noindent
+The methods \code{asInput} and \code{asOutput} force all modules of
+the data object to the requested direction.
+
+By folding directions into the object declarations, Chisel is able to
+provide powerful wiring constructs described later.
+%% \begin{scala}
+%% class MuxBundle extends Bundle {
+%%   val sel = Input(UInt(1.W))
+%%   val in0 = Input(UInt(1.W))
+%%   val in1 = Input(UInt(1.W))
+%%   val out = Output(UInt(1.W))
+%% }
+
+%% class Mux2 extends Module {
+%%   val io = IO(new MuxBundle())
+%%   io.out := (io.sel & io.in1) | (~io.sel & io.in0)
+%% }
+%% \end{scala}
+
+
+\section{Modules}
+
+Chisel {\em modules} are very similar to Verilog {\em modules} in
+defining a hierarchical structure in the generated circuit.
+%Like functional generators, we can also parameterize the construction of
+%circuits by turning them into object-oriented modules.  Unlike
+%functional generators, modules also provide a coarse hierarchy on a
+%circuit and permit a level of generator abstraction that is often
+%useful.
+The hierarchical module namespace is accessible in downstream tools
+to aid in debugging and physical layout.  A user-defined module is
+defined as a {\em class} which:
+\begin{itemize}
+\item inherits from \code{Module},
+\item contains an interface wrapped in an \code{IO()} function and stored in a port field named \code{io}, and
+\item wires together subcircuits in its constructor.
+\end{itemize}
+As an example, consider defining your own two-input multiplexer as a
+module:
+\begin{scala}
+class Mux2 extends Module {
+  val io = IO(new Bundle{
+    val sel = Input(UInt(1.W))
+    val in0 = Input(UInt(1.W))
+    val in1 = Input(UInt(1.W))
+    val out = Output(UInt(1.W))
+  })
+  io.out := (io.sel & io.in1) | (~io.sel & io.in0)
+}
+\end{scala}
+
+\noindent
+The wiring interface to a module is a collection of ports in the
+form of a \code{Bundle}.  The interface to the module is defined
+through a field named \code{io}.  For \code{Mux2}, \code{io} is
+defined as a bundle with four fields, one for each multiplexer port.
+
+The \code{:=} assignment operator, used here in the body of the
+definition, is a special operator in Chisel that wires the input of
+left-hand side to the output of the right-hand side.
+
+\subsection{Module Hierarchy}
+
+We can now construct circuit hierarchies, where we build larger modules out
+of smaller sub-modules.  For example, we can build a 4-input
+multiplexer module in terms of the \code{Mux2} module by wiring
+together three 2-input multiplexers:
+
+\begin{scala}
+class Mux4 extends Module {
+  val io = IO(new Bundle {
+    val in0 = Input(UInt(1.W))
+    val in1 = Input(UInt(1.W))
+    val in2 = Input(UInt(1.W))
+    val in3 = Input(UInt(1.W))
+    val sel = Input(UInt(2.W))
+    val out = Output(UInt(1.W))
+  })
+  val m0 = Module(new Mux2())
+  m0.io.sel := io.sel(0) 
+  m0.io.in0 := io.in0; m0.io.in1 := io.in1
+
+  val m1 = Module(new Mux2())
+  m1.io.sel := io.sel(0) 
+  m1.io.in0 := io.in2; m1.io.in1 := io.in3
+
+  val m3 = Module(new Mux2())
+  m3.io.sel := io.sel(1) 
+  m3.io.in0 := m0.io.out; m3.io.in1 := m1.io.out
+
+  io.out := m3.io.out
+}
+\end{scala}
+
+\noindent
+We again define the module interface as \code{io} and wire up the
+inputs and outputs.  In this case, we create three \code{Mux2}
+children modules, using the \code{Module} constructor function and 
+the Scala \code{new} keyword to create a
+new object.  We then wire them up to one another and to the ports of
+the \code{Mux4} interface.
+
+\section{Running Examples}
+
+Now that we have defined modules, we will discuss how we actually run and test a circuit.
+
+%\begin{figure}
+%\begin{center}
+%\includegraphics[width=0.45\textwidth]{../tutorial/figs/DUT.pdf}
+%\end{center}
+%\caption{DUT is tested under the control of Tester object}
+%\label{fig:dut}
+%\end{figure}
+
+Testing is a crucial part of circuit design,
+and thus in Chisel we provide a mechanism for
+testing circuits by providing test vectors within Scala using
+tester method calls
+which binds a tester to a module
+and allows users to write tests using the given debug protocol.  In particular, users utilize:
+\begin{itemize}
+\item \code{poke} to set input port and state values,
+\item \code{step} to execute the circuit one time unit,
+\item \code{peek} to read port and state values, and
+\item \code{expect} to compare peeked circuit values to expected arguments.
+\end{itemize}
+
+\begin{commentary}
+Chisel produces \verb$Firrtl$
+intermediate representation (IR).  \verb$Firrtl$ can be interpreted directly or can be translated into \verb@Verilog@,
+which can then be used to generate a C++ simulator through verilator.
+\end{commentary}
+
+\noindent
+For example, in the following:
+\noindent
+
+\begin{scala}
+class Mux2Tests(c: Mux2, b: Option[TesterBackend] = None) extends PeekPokeTester(c, _backend=b) {
+  val n = pow(2, 3).toInt
+  for (s <- 0 until 2) {
+    for (i0 <- 0 until 2) {
+      for (i1 <- 0 until 2) {
+        poke(c.io.sel, s)
+        poke(c.io.in1, i1)
+        poke(c.io.in0, i0)
+        step(1)
+        expect(c.io.out, (if (s == 1) i1 else i0))
+      }
+    }
+  }
+}
+\end{scala}
+
+\noindent
+assignments for each input of \verb+Mux2+ are set to the appropriate values using \verb+poke+. For this particular
+example, we are testing the \verb+Mux2+ by hardcoding the inputs to some known values and checking
+if the output corresponds to the known one. To do this, on each iteration we generate appropriate inputs
+to the module and tell the simulation to assign these values to the inputs of the device we are testing \verb+c+, step
+the circuit 1 clock cycle, and test the expected value. Steps are necessary to update registers and the combinational
+logic driven by registers. For pure combinational paths, poke alone is sufficient to update all combinational paths
+connected to the poked input wire.
+
+Finally, the following the tester is invoked by calling \code{runPeekPokeTester}:
+
+\begin{scala}
+  def main(args: Array[String]): Unit = {
+    runPeekPokeTester(() => new GCD()){
+      (c,b) => new GCDTests(c,b)}
+  }
+\end{scala}
+
+\noindent
+This will run the tests defined in GCDTests with the GCD module being simulated but the \verb$Firrtl$ interpreter. We can instead have the GCD module be simulated by a C++ simulator generated by Verilator by calling the following:
+\comment{What does it mean to generate a harness file?}
+\begin{scala}
+  def main(args: Array[String]): Unit = {
+    runPeekPokeTester(() => new GCD(), "verilator"){
+      (c,b) => new GCDTests(c,b)}
+  }
+\end{scala}
+
+\section{State Elements}
+\label{sec:sequential}
+
+% SINGLE CLK and RESET
+
+The simplest form of state element supported by Chisel is a
+positive edge-triggered register, which can be instantiated
+as:
+\begin{scala}
+val reg = Reg(next = in)
+\end{scala}
+
+\noindent
+This circuit has an output that is a copy of the input signal \verb+in+
+delayed by one clock cycle.  Note that we do not have to specify the
+type of \verb+Reg+ as it will be automatically inferred from its input
+when instantiated in this way.  In the current version of Chisel,
+clock and reset are global signals that are implicity included where
+needed.
+
+Using registers, we can quickly define a number of useful circuit
+constructs.  For example, a rising-edge detector that takes a boolean
+signal in and outputs true when the current value is true and the
+previous value is false is given by:
+\begin{scala}
+def risingedge(x: Bool) = x && !Reg(next = x)
+\end{scala}
+
+Counters are an important sequential circuit.  To construct an
+up-counter that counts up to a maximum value, \verb+max+, then wraps
+around back to zero (i.e., modulo \verb!max+1!), we write:
+\begin{scala}
+def counter(max: UInt) = {
+  val x = Reg(init = 0.U(max.getWidth.W))
+  x := Mux(x === max, 0.U, x + 1.U)
+  x
+}
+\end{scala}
+
+\noindent
+The counter register is created in the \verb!counter! function 
+with a reset value of \verb!0! (with width large enough to hold \verb+max+),
+to which the register will be initialized when the global reset for the circuit is asserted.
+The \verb!:=! assignment to \verb!x! in \verb!counter! wires an update combinational circuit 
+which increments the counter value unless it hits the \verb+max+ at which point it wraps back to zero.
+Note that when \verb!x! appears on the right-hand side of
+an assigment, its output is referenced, whereas when on the left-hand
+side, its input is referenced.
+
+Counters can be used to build a number of useful sequential circuits.
+For example, we can build a pulse generator by outputting true when
+a counter reaches zero:
+\begin{scala}
+// Produce pulse every n cycles.
+def pulse(n: UInt) = counter(n - 1.U) === 0.U
+\end{scala}
+
+\noindent
+A square-wave generator can then be toggled by the pulse train,
+toggling between true and false on each pulse:
+\begin{scala}[escapechar=@]
+// Flip internal state when input true.
+def toggle(p: Bool) = {
+  val x = Reg(init = false.B)
+  x := Mux(p, !x, x)
+  x
+}
+
+// Square wave of a given period.
+def squareWave(period: UInt) = toggle(pulse(period/2))
+\end{scala}
+
+\subsection{Forward Declarations}
+
+Purely combinational circuits cannot have cycles between nodes, and
+Chisel will report an error if such a cycle is detected.  Because they
+do not have cycles, combinational circuits can always be constructed
+in a feed-forward manner, by adding new nodes whose inputs are derived
+from nodes that have already been defined.  Sequential circuits
+naturally have feedback between nodes, and so it is sometimes
+necessary to reference an output wire before the producing node has
+been defined.  Because Scala evaluates program statements
+sequentially, we allow data nodes to serve as a wire providing
+a declaration of a node that can be used immediately, but whose
+input will be set later.  
+For example, in a simple CPU, we need to define the \verb!pcPlus4!
+and \verb!brTarget! wires so they can be referenced before defined:
+\begin{scala}
+val pcPlus4  = UInt()
+val brTarget = UInt()
+val pcNext   = Mux(io.ctrl.pcSel, brTarget, pcPlus4)
+val pcReg    = Reg(next = pcNext, init = 0.U(32.W))
+pcPlus4     := pcReg + 4.U
+...
+brTarget    := addOut
+\end{scala}
+
+\noindent
+The wiring operator
+\verb!:=! is used to wire up
+the connection after \verb!pcReg! and \verb!addOut! are defined.
+
+\subsection{Conditional Updates}
+
+In our previous examples using registers, we simply wired the
+combinational logic blocks to the inputs of the registers.
+When describing the operation of state
+elements, it is often useful to instead specify when updates to the
+registers will occur and to specify these updates spread across
+several separate statements.  Chisel provides conditional update rules
+in the form of the \code{when} construct to support this style of
+sequential logic description. For example,
+% MS: the following is not working (anymore), it results in a single bit register
+% with the incrementing code.
+% val r = Reg(16.U)
+% MS: is there any meaning having a single, unnamed parameter for Reg()?
+% MS: should this be allowed?
+\begin{scala}
+val r = Reg(init = 0.U(16.W))
+when (cond) {
+  r := r + 1.U
+}
+\end{scala}
+
+\noindent
+where register \code{r} is updated at the end of the current clock
+cycle only if \verb+cond+ is \code{true}.  The argument to \code{when} is a
+predicate circuit expression that returns a \code{Bool}.  The update
+block following \code{when} can only contain update statements using
+the assignment operator \verb+:=+, simple expressions, and named wires
+defined with \code{val}.
+
+In a sequence of conditional updates, the last conditional update
+whose condition is true takes priority.  For example,
+\begin{scala}
+when (c1) { r := 1.U }
+when (c2) { r := 2.U }
+\end{scala}
+
+\noindent
+leads to \code{r} being updated according to the following truth table:
+\begin{center}
+{\small
+\begin{tabular}{|c|c|c|l|}
+\hline
+c1 & c2  &  r & \\
+\hline
+0 &  0 & r &  r unchanged \\
+0 &  1 & 2 & \\
+1 &  0 & 1 & \\
+1 &  1 & 2& c2 takes precedence over c1 \\
+\hline
+\end{tabular}
+}
+\end{center}
+
+\begin{figure}[h]
+\centering
+\includegraphics[width=3in]{figs/condupdates.pdf}
+\caption{Equivalent hardware constructed for conditional updates.
+  Each \code{when} statement adds another level of data mux and ORs
+  the predicate into the enable chain.  The compiler effectively adds
+  the termination values to the end of the chain automatically.}
+\label{fig:condupdates}
+\end{figure}
+
+Figure~\ref{fig:condupdates} shows how each conditional update can be
+viewed as inserting a mux before the input of a register to select
+either the update expression or the previous input according to the
+\code{when} predicate.  In addition, the predicate is OR-ed into an
+enable signal that drives the load enable of the register.  The
+compiler places initialization values at the beginning of the chain so
+that if no conditional updates fire in a clock cycle, the load enable
+of the register will be deasserted and the register value will not
+change.
+ 
+Chisel provides some syntactic sugar for other common forms of
+conditional update.  The \verb+unless+ construct is the same as
+\verb+when+ but negates its condition.  In other words,
+\begin{scala}
+unless (c) { body }
+\end{scala}
+is the same as
+\begin{scala}
+when (!c) { body }
+\end{scala}
+
+% The \verb+otherwise+ construct is the same as \verb+when+ with a true
+% condition.  In other words,
+% \begin{scala}
+% otherwise { body }
+% \end{scala}
+% 
+% \noindent
+% is the same as
+% \begin{scala}
+% when (true.B) { body }
+% \end{scala}
+
+The update block can target multiple registers, and there can be
+different overlapping subsets of registers present in different update
+blocks.  Each register is only affected by conditions in which it
+appears.  The same is possible for combinational circuits (update
+of a \code{Wire}). Note that all combinational
+circuits need a default value. For example:
+\begin{scala}
+r := 3.S; s := 3.S
+when (c1)   { r := 1.S; s := 1.S }
+when (c2)   { r := 2.S }
+\end{scala}
+
+\noindent
+leads to \code{r} and \code{s} being updated according to the
+following truth table:
+\begin{scala}
+c1 c2  r  s
+0   0  3  3
+0   1  2  3 // r updated in c2 block, s at top level.
+1   0  1  1
+1   1  2  1
+\end{scala}
+
+\begin{commentary}
+We are considering adding a different form of conditional update,
+where only a single update block will take effect.  These atomic
+updates are similar to Bluespec guarded atomic actions.
+% TODO: when / .elsewhen / .otherwise
+\end{commentary}
+
+Conditional update constructs can be nested and any given block is
+executed under the conjunction of all outer nesting conditions.  For
+example,
+\begin{scala}
+when (a) { when (b) { body } }
+\end{scala}
+
+\noindent
+is the same as:
+\begin{scala}
+when (a && b) { body }
+\end{scala}
+
+Conditionals can be chained together using
+\verb+when+, \verb+.elsewhen+, \verb+.otherwise+ corresponding to
+\verb+if+, \verb+else if+ and \verb+else+ in Scala.  For example,
+\begin{scala}
+when (c1) { u1 }
+.elsewhen (c2) { u2 }
+.otherwise { ud }
+\end{scala}
+\noindent
+is the same as:
+\begin{scala}
+when (c1) { u1 }
+when (!c1 && c2) { u2 }
+when (!(c1 || c2)) { ud }
+\end{scala}
+
+We introduce the \code{switch} statement for conditional updates
+involving a series of comparisons against a common key.  For example,
+\begin{scala}
+switch(idx) {
+ is(v1) { u1 }
+ is(v2) { u2 }
+}
+\end{scala}
+
+\noindent
+is equivalent to:
+\begin{scala}
+when (idx === v1) { u1 }
+.elsewhen (idx === v2) { u2 }
+\end{scala}
+
+Chisel also allows a \code{Wire}, i.e., the output of some
+combinational logic, to be the target of conditional update statements
+to allow complex combinational logic expressions to be built
+incrementally.  Chisel does not allow a combinational output to be
+incompletely specified and will report an error if an unconditional
+update is not encountered for a combinational output.
+\begin{commentary}
+In Verilog, if a procedural specification of a combinational logic
+block is incomplete, a latch will silently be inferred causing many
+frustrating bugs.
+
+It could be possible to add more analysis to the Chisel compiler, to
+determine if a set of predicates covers all possibilities.  But for
+now, we require a single predicate that is always true in the
+chain of conditional updates to a \code{Wire}.
+\end{commentary}
+
+
+\subsection{Finite State Machines}
+
+A common type of sequential circuit used in digital design is a Finite
+State Machine (FSM).  An example of a simple FSM is a parity
+generator:
+
+% \begin{scala}
+% class Parity extends Module {
+%   val io = IO(new Bundle {
+%     val in  = Input(Bool())
+%     val out = Output(Bool()) })
+%   val s_even :: s_odd :: Nil = Enum(2)
+%   val state  = Reg(init = s_even)
+%   switch(state, Array(
+%     (s_even, () => { when (io.in) { state := s_odd } }),
+%     (s_odd,  () => { when (io.in) { state := s_even } }) ))
+%   io.out := state === s_odd
+% }
+% \end{scala}
+
+\begin{scala}
+class Parity extends Module {
+  val io = IO(new Bundle {
+    val in  = Input(Bool())
+    val out = Output(Bool()) })
+  val s_even :: s_odd :: Nil = Enum(2)
+  val state  = Reg(init = s_even)
+  when (io.in) {
+    when (state === s_even) { state := s_odd  }
+    when (state === s_odd)  { state := s_even }
+  }
+  io.out := (state === s_odd)
+}
+\end{scala}
+
+\noindent
+where \verb+Enum(2)+ generates two \verb+UInt+ literals.
+States are updated when \verb+in+ is true.  It is worth
+noting that all of the mechanisms for FSMs are built upon registers,
+wires, and conditional updates.
+
+Below is a more complicated FSM example which is a circuit for
+accepting money for a vending machine:
+\begin{scala}
+class VendingMachine extends Module {
+  val io = IO(new Bundle {
+    val nickel = Input(Bool())
+    val dime   = Input(Bool())
+    val valid    = Output(Bool()) })
+  val s_idle :: s_5 :: s_10 :: s_15 :: s_ok :: Nil = Enum(5)
+  val state = Reg(init = s_idle)
+  when (state === s_idle) {
+    when (io.nickel) { state := s_5 }
+    when (io.dime)   { state := s_10 }
+  }
+  when (state === s_5) {
+    when (io.nickel) { state := s_10 }
+    when (io.dime)   { state := s_15 }
+  }
+  when (state === s_10) {
+    when (io.nickel) { state := s_15 }
+    when (io.dime)   { state := s_ok }
+  }
+  when (state === s_15) {
+    when (io.nickel) { state := s_ok }
+    when (io.dime)   { state := s_ok }
+  }
+  when (state === s_ok) {
+    state := s_idle
+  }
+  io.valid := (state === s_ok)
+}
+\end{scala}
+
+\noindent
+Here is the vending machine FSM defined with \code{switch} statement:
+\begin{scala}
+class VendingMachine extends Module {
+  val io = IO(new Bundle {
+    val nickel = Input(Bool())
+    val dime   = Input(Bool())
+    val valid  = Output(Bool())
+  })
+  val s_idle :: s_5 :: s_10 :: s_15 :: s_ok :: Nil = Enum(5)
+  val state = Reg(init = s_idle)
+  
+  switch (state) {
+    is (s_idle) {
+      when (io.nickel) { state := s_5 }
+      when (io.dime) { state := s_10 }
+    }
+    is (s_5) {
+      when (io.nickel) { state := s_10 }
+      when (io.dime) { state := s_15 }
+    }
+    is (s_10) {
+      when (io.nickel) { state := s_15 }
+      when (io.dime) { state := s_ok }
+    }
+    is (s_15) {
+      when (io.nickel) { state := s_ok }
+      when (io.dime) { state := s_ok }
+    }
+    is (s_ok) {
+      state := s_idle
+    }
+  }
+  io.valid := (state === s_ok)
+}
+\end{scala}
+
+\section{Memories}
+
+Chisel provides facilities for creating both read only and
+read/write memories.  
+
+\subsection{ROM}
+
+Users can define read only memories with a \code{Vec}:
+
+\begin{scala}
+Vec(inits: Seq[T])
+Vec(elt0: T, elts: T*)
+\end{scala}
+
+\noindent
+where \verb+inits+ is a sequence of initial \verb+Data+ literals that
+initialize the ROM.
+For example,  users can
+create a small ROM initialized to \verb+1, 2, 4, 8+ and 
+loop through all values using a counter as an address generator as follows:
+
+\begin{scala}
+val m = Vec(Array(1.U, 2.U, 4.U, 8.U))
+val r = m(counter(UInt(m.length.W)))
+\end{scala}
+
+\noindent
+We can create an \verb+n+ value sine lookup table using a ROM initialized as follows:
+
+\begin{scala}
+def sinTable (amp: Double, n: Int) = {
+  val times = 
+    Range(0, n, 1).map(i => (i*2*Pi)/(n.toDouble-1) - Pi)
+  val inits = 
+    times.map(t => SInt(round(amp * sin(t)), width = 32))
+  Vec(inits)
+}
+def sinWave (amp: Double, n: Int) = 
+  sinTable(amp, n)(counter(UInt(n.W))
+\end{scala}
+
+\noindent
+where \verb+amp+ is used to scale the fixpoint values stored in the ROM.
+
+\subsection{Mem}
+
+Memories are given special treatment in Chisel since hardware
+implementations of memory have many variations, e.g., FPGA memories
+are instantiated quite differently from ASIC memories.  Chisel defines
+a memory abstraction that can map to either simple Verilog behavioral
+descriptions, or to instances of memory modules that are available
+from external memory generators provided by foundry or IP vendors.  
+
+Chisel supports random-access memories via the \code{Mem} construct.
+Writes to Mems are positive-edge-triggered and reads are either
+combinational or positive-edge-triggered.\footnote{Current FPGA technology
+does not support combinational (asynchronous) reads (anymore). The read address
+needs to be registered.}
+
+
+Ports into Mems are created by applying a \code{UInt} index.  A 32-entry
+register file with one write port and two combinational read ports might be
+expressed as follows:
+
+\begin{scala}
+val rf = Mem(32, UInt(64.W))
+when (wen) { rf(waddr) := wdata }
+val dout1 = rf(waddr1)
+val dout2 = rf(waddr2)
+\end{scala}
+
+If the optional parameter \code{seqRead} is set, Chisel will attempt to infer
+sequential read ports when the read address is a \code{Reg}.  A one-read port,
+one-write port SRAM might be described as follows:
+
+\begin{scala}
+val ram1r1w =
+  Mem(1024, UInt(32.W))
+val reg_raddr = Reg(UInt())
+when (wen) { ram1r1w(waddr) := wdata }
+when (ren) { reg_raddr := raddr }
+val rdata = ram1r1w(reg_raddr)
+\end{scala}
+
+Single-ported SRAMs can be inferred when the read and write conditions are
+mutually exclusive in the same \code{when} chain:
+
+\begin{scala}
+val ram1p = Mem(1024, UInt(32.W))
+val reg_raddr = Reg(UInt())
+when (wen) { ram1p(waddr) := wdata }
+.elsewhen (ren) { reg_raddr := raddr }
+val rdata = ram1p(reg_raddr)
+\end{scala}
+
+If the same \code{Mem} address is both written and sequentially read on the same clock
+edge, or if a sequential read enable is cleared, then the read data is
+undefined.
+
+\code{Mem} also supports write masks for subword writes.  A given bit is written if
+the corresponding mask bit is set.
+
+\begin{scala}
+val ram = Mem(256, UInt(32.W))
+when (wen) { ram.write(waddr, wdata, wmask) }
+\end{scala}
+
+
+% For example, an
+% audio recorder could be defined as follows:
+% 
+% \begin{scala}
+%   def audioRecorder(n: Int, button: Bool) = { 
+%     val addr   = counter(UInt(n.W))
+%     val ram    = Mem(n)
+%     ram(addr) := button
+%     ram(Mux(button(), 0.U, addr))
+%   } 
+% \end{scala}
+% 
+% \noindent
+% where a counter is used as an address generator into a memory.  
+% The device records while \verb+button+ is \verb+true+, or plays back when \verb+false+.
+
+
+\section{Interfaces \& Bulk Connections}
+\label{sec:interfaces}
+
+For more sophisticated modules it is often useful to define and
+instantiate interface classes while defining the IO for a module.  First and
+foremost, interface classes promote reuse allowing users to capture
+once and for all common interfaces in a useful form.  Secondly,
+interfaces allow users to dramatically reduce wiring by supporting
+{\em bulk connections} between producer and consumer modules.  Finally,
+users can make changes in large interfaces in one place reducing the
+number of updates required when adding or removing pieces of the
+interface.
+
+\subsection{Ports: Subclasses  \& Nesting}
+
+As we saw earlier, users can define their own interfaces by defining a class that subclasses \verb+Bundle+.  
+For example, a user could define a simple link for handshaking data as follows:
+
+\begin{scala}
+class SimpleLink extends Bundle { 
+  val data  = Output(UInt(16.W)) 
+  val valid = Output(Bool())
+}
+\end{scala}
+
+\noindent
+We can then extend \verb+SimpleLink+ by adding parity bits using
+bundle inheritance:
+
+\begin{scala}
+class PLink extends SimpleLink { 
+  val parity = Output(UInt(5.W)) 
+}
+\end{scala}
+
+\noindent
+In general, users can organize their interfaces into hierarchies using inheritance.  
+
+From there we can define a filter interface by nesting two
+\verb+PLink+s into a new \verb+FilterIO+ bundle:
+
+\begin{scala}
+class FilterIO extends Bundle { 
+  val x = new PLink().flip
+  val y = new PLink()
+}
+\end{scala}
+
+\noindent
+where \verb+flip+ recursively changes the ``gender'' of a bundle,
+changing input to output and output to input.
+
+We can now define a filter by defining a filter class extending module:
+
+\begin{scala}
+class Filter extends Module { 
+  val io = IO(new FilterIO())
+  ...
+}
+\end{scala}
+
+\noindent 
+where the \verb+io+ field contains \verb+FilterIO+. 
+
+\subsection{Bundle Vectors}
+
+Beyond single elements, vectors of elements form richer hierarchical interfaces.  
+For example, in order to create a crossbar with a vector of inputs, producing a vector of outputs, and selected by a UInt input, 
+we utilize the \verb+Vec+ constructor:
+
+\begin{scala}
+class CrossbarIo(n: Int) extends Bundle {
+  val in  = Vec(n, new PLink().flip())
+  val sel = Input(UInt(sizeof(n).W))
+  val out = Vec(n, new PLink())
+}
+\end{scala}
+
+% \begin{scala}
+% class CrossbarIo(n: Int) extends Bundle {
+%   val in  = Vec(n, Input(UInt(w.W)))
+%   val sel = Vec(n, Input(UInt(sizeof(n).W)))
+%   val out = Vec(n, Output(UInt(w.W)))
+% }
+% \end{scala}
+
+\noindent
+where \verb+Vec+ takes a size as the first argument and a block returning a port as the second argument.
+
+\subsection{Bulk Connections}
+
+We can now compose two filters into a filter block as follows:
+
+\begin{scala}
+class Block extends Module { 
+  val io = IO(new FilterIO())
+  val f1 = Module(new Filter())
+  val f2 = Module(new Filter())
+
+  f1.io.x <> io.x
+  f1.io.y <> f2.io.x
+  f2.io.y <> io.y
+}
+\end{scala}
+
+\noindent
+where \verb+<>+ bulk connects interfaces of opposite gender between
+sibling modules or interfaces of same gender between parent/child modules. 
+Bulk connections connect leaf ports of the same name to each other.
+After all connections are made and the circuit is being elaborated,
+Chisel warns users if ports have other than exactly one connection to them.
+
+\subsection{Interface Views}
+
+\begin{figure}
+\centerline{\includegraphics[width=3in]{figs/cpu.png}}
+\caption{Simple CPU involving control and data path submodules and host and memory interfaces.}
+\label{fig:cpu}
+\end{figure}
+
+Consider a simple CPU consisting of control path and data path submodules and host and memory interfaces shown in Figure~\ref{fig:cpu}.
+In this CPU we can see that the control path and data path each connect only to a part of the instruction and data memory interfaces. 
+Chisel allows users to do this with partial fulfillment of interfaces.
+A user first defines the complete interface to a ROM and Mem as follows:
+
+\begin{scala}
+class RomIo extends Bundle {
+  val isVal = Input(Bool())
+  val raddr = Input(UInt(32.W))
+  val rdata = Output(UInt(32.W))
+}
+
+class RamIo extends RomIo {
+  val isWr  = Input(Bool())
+  val wdata = Input(UInt(32.W))
+}
+\end{scala}
+
+\noindent
+Now the control path can build an interface in terms of these interfaces:
+
+\begin{scala}
+class CpathIo extends Bundle {
+  val imem = RomIo().flip()
+  val dmem = RamIo().flip()
+  ...
+}
+\end{scala}
+
+\noindent
+and the control and data path modules can be built by partially assigning to
+this interfaces as follows:
+
+\begin{scala}
+class Cpath extends Module {
+  val io = IO(new CpathIo())
+  ...
+  io.imem.isVal := ...
+  io.dmem.isVal := ...
+  io.dmem.isWr  := ...
+  ...
+}
+
+class Dpath extends Module {
+  val io = IO(new DpathIo())
+  ...
+  io.imem.raddr := ...
+  io.dmem.raddr := ...
+  io.dmem.wdata := ...
+  ...
+}
+\end{scala}
+
+\noindent
+We can now wire up the CPU using bulk connects as we would with other bundles:
+
+\begin{scala}
+class Cpu extends Module {
+  val io = IO(new CpuIo())
+  val c  = Module(new CtlPath())
+  val d  = Module(new DatPath())
+  c.io.ctl  <> d.io.ctl
+  c.io.dat  <> d.io.dat
+  c.io.imem <> io.imem
+  d.io.imem <> io.imem
+  c.io.dmem <> io.dmem
+  d.io.dmem <> io.dmem
+  d.io.host <> io.host
+}
+\end{scala}
+
+\noindent
+Repeated bulk connections of partially assigned control and data path interfaces
+completely connect up the CPU interface.
+
+% A Bool can be automatically treated as a single bit UInt (with values
+% 0 or 1), but an Int or UInt cannot be used as a Bool without an
+% explicit cast.
+%
+%   Lit(5) // means a constant node with decimal value 5. Bit width will
+%           // be inferred automatically if possible
+%
+% A node is a hardware operator that has zero or more inputs and that
+% drives one output.  An example of a node with zero inputs is a
+% constant generator.
+%
+% \begin{scala}
+% Lit(10, 4) // means a constant node of type UInt that is 4 bits
+%            // wide with decimal 10.
+% Lit(10)
+% LitInt(10, 4)
+% LitUInt(10, 4)
+% Lit(-1,4)
+% \end{scala}
+%
+% can more concisely write:
+%
+% Module correspond to Verilog modules
+% Cell is a sub-module, Chisel Module
+
+\section{Functional Module Creation}
+\label{sec:funconstructor}
+
+It is also useful to be able to make a functional interface for
+module construction.  For instance, we could build a constructor
+that takes multiplexer inputs as parameters and returns the
+multiplexer output:
+
+\begin{scala}
+object Mux2 {
+  def apply (sel: UInt, in0: UInt, in1: UInt) = {
+    val m = new Mux2()
+    m.io.in0 := in0
+    m.io.in1 := in1
+    m.io.sel := sel
+    m.io.out
+  }
+}
+\end{scala}
+
+\noindent
+where \code{object Mux2} creates a Scala singleton object on the \code{Mux2}
+module class, and \code{apply} defines a method for creation of a \code{Mux2} instance.
+%
+With this \code{Mux2} creation function, the specification of \code{Mux4} now is
+significantly simpler.
+
+\begin{scala}
+class Mux4 extends Module {
+  val io = IO(new Bundle {
+    val in0 = Input(UInt(1.W))
+    val in1 = Input(UInt(1.W))
+    val in2 = Input(UInt(1.W))
+    val in3 = Input(UInt(1.W))
+    val sel = Input(UInt(2.W))
+    val out = Output(UInt(1.W))
+  })
+  io.out := Mux2(io.sel(1),
+                 Mux2(io.sel(0), io.in0, io.in1),
+                 Mux2(io.sel(0), io.in2, io.in3))
+}
+\end{scala}
+
+Selecting inputs is so useful that Chisel builds it in and calls it
+\code{Mux}.  However, unlike \code{Mux2} defined above, the builtin version allows any datatype on
+\code{in0} and \code{in1} as long as they are the same subclass of \code{Data}.
+In Section~\ref{sec:parameterization} we will see how to define this
+ourselves.
+
+Chisel provides \code{MuxCase} which is an n-way \code{Mux} 
+\begin{scala}
+MuxCase(default, Array(c1 -> a, c2 -> b, ...))
+\end{scala}
+ 
+\noindent
+where each condition / value is represented as a tuple in a Scala
+array and where \code{MuxCase} can be translated into the following
+\code{Mux} expression:
+
+\begin{scala}
+Mux(c1, a, Mux(c2, b, Mux(..., default)))
+\end{scala}
+
+\noindent
+Chisel also provides \code{MuxLookup} which is an n-way indexed multiplexer:
+
+\begin{scala}
+MuxLookup(idx, default, 
+          Array(0.U -> a, 1.U -> b, ...))
+\end{scala}
+
+\noindent
+which can be rewritten in terms of:\verb+MuxCase+ as follows:
+
+\begin{scala}
+MuxCase(default, 
+        Array((idx === 0.U) -> a,
+              (idx === 1.U) -> b, ...))
+\end{scala}
+
+\noindent
+Note that the cases (eg. c1, c2) must be in parentheses.
+
+% TODO: higher order filter
+
+% \Noindent
+% where the overall expression returns the value corresponding to the first condition evaluating to true.
+
+% FUNCTIONAL CREATION
+%
+% want to go from io to constructor
+%
+% \begin{scala}
+% val io = IO(new Bundle{
+%   val sel = Input(UInt(1.W))
+%   val in0 = Input(UInt(1.W))
+%   val in1 = Input(UInt(1.W))
+%   val out = Output(UInt(1.W))
+% })
+% def Mux2(sel: UInt, in0: UInt, in0: UInt): UInt = {
+%   val m = new Mux2()
+%   m.io.wire(Array("sel" => sel, "in0" => in0, "in1" => in1), "out")
+% }
+% \end{scala}
+
+% picture of box in box
+
+
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\section{Polymorphism and \newline Parameterization}
+\label{sec:parameterization}
+
+Scala is a strongly typed language and uses parameterized types to specify generic functions and classes.  
+In this section, we show how Chisel users can define their own reusable functions and classes using parameterized classes.
+\begin{commentary}
+This section is advanced and can be skipped at first reading.
+\end{commentary}
+
+\subsection{Parameterized Functions}
+
+Earlier we defined \code{Mux2} on \code{Bool}, but now we show how we can define a generic multiplexer function.
+We define this function as taking a boolean condition and con and alt arguments (corresponding to then and else expressions) of type \code{T}:
+
+\begin{scala}
+def Mux[T <: Bits](c: Bool, con: T, alt: T): T { ... }
+\end{scala}
+
+\noindent
+where \code{T} is required to be a subclass of \code{Bits}.
+Scala ensures that in each usage of \code{Mux}, it can find a common superclass of the actual con and alt argument types, 
+otherwise it causes a Scala compilation type error.
+For example,
+
+\begin{scala}
+Mux(c, 10.U, 11.U)
+\end{scala}
+
+\noindent
+yields a \code{UInt} wire because the \code{con} and \code{alt} arguments are each of type \code{UInt}.
+
+% Earlier we defined \code{Mux2} on \code{Bool}, but now we show how we can define a generic \code{Mux}.  
+% We define a function that takes a condition and two functions of no arguments (called thunks) for the {\it then} and {\it else} cases:
+% 
+% \begin{scala}
+% def Mux[T <: UInt](c: Bool, con: T, alt: T): T
+% def Mux[T <: UInt](c: Bool)(con: => T)(alt: => T): T
+% \end{scala}
+% 
+% \noindent
+% where the two thunk return types are parameterized to be a type \code{T} that is a subclass of \code{UInt}.
+% Scala ensures that it finds a common superclass of the two thunks' return types.
+
+We now present a more advanced example of parameterized functions for defining an inner product FIR digital filter generically over Chisel \code{Num}'s.
+The inner product FIR filter can be mathematically defined as:
+\begin{equation}
+y[t] = \sum_j w_j * x_j[t-j]
+\end{equation}
+
+\noindent 
+where $x$ is the input and $w$ is a vector of weights.
+In Chisel this can be defined as:
+
+% MS: just out of curiosity: does this example generate several delay lines?
+\begin{scala}
+def delays[T <: Data](x: T, n: Int): List[T] = 
+  if (n <= 1) List(x) else x :: Delays(RegNext(x), n-1)
+
+def FIR[T <: Data with Num[T]](ws: Seq[T], x: T): T = 
+  (ws, Delays(x, ws.length)).zipped.
+    map( _ * _ ).reduce( _ + _ )
+\end{scala}
+ 
+\noindent
+where 
+\code{delays} creates a list of incrementally increasing delays of its input and
+\code{reduce} constructs a reduction circuit given a binary combiner function \code{f}.  
+In this case, \code{reduce} creates a summation circuit.
+Finally, the \code{FIR} function is constrained to work on inputs of type \code{Num} where Chisel multiplication and addition are defined.
+
+\subsection{Parameterized Classes}
+
+Like parameterized functions, we can also parameterize classes to make them more reusable.
+For instance, we can generalize the Filter class to use any kind of link.  
+We do so by parameterizing the \verb+FilterIO+ class and defining the constructor to take a zero argument type constructor function as follow:
+
+\begin{scala}
+class FilterIO[T <: Data](type: T) extends Bundle { 
+  val x = type.asInput.flip
+  val y = type.asOutput
+}
+\end{scala}
+
+\noindent
+We can now define \verb+Filter+ by defining a module class that also takes a link type constructor argument and passes it through to the \verb+FilterIO+ interface constructor:
+
+\begin{scala}
+class Filter[T <: Data](type: T) extends Module { 
+  val io = IO(new FilterIO(type))
+  ...
+}
+\end{scala}
+
+\noindent
+We can now define a \verb+PLink+ based \verb+Filter+ as follows:
+\begin{scala}
+val f = Module(new Filter(new PLink()))
+\end{scala}
+
+\noindent
+A generic FIFO could be defined as shown in Figure~\ref{fig:fifo} and
+used as follows:
+
+\begin{scala}
+class DataBundle extends Bundle {
+  val A = UInt(32.W)
+  val B = UInt(32.W)
+}
+
+object FifoDemo {
+  def apply () = new Fifo(new DataBundle, 32)
+}
+\end{scala}
+
+\begin{figure}[ht]
+\begin{scala}
+class Fifo[T <: Data] (type: T, n: Int) 
+    extends Module {
+  val io = IO(new Bundle {
+    val enq_val = Input(Bool())
+    val enq_rdy = Output(Bool())
+    val deq_val = Output(Bool())
+    val deq_rdy = Input(Bool())
+    val enq_dat = type.asInput
+    val deq_dat = type.asOutput
+  })
+  val enq_ptr      = Reg(init = 0.U(sizeof(n).W))
+  val deq_ptr      = Reg(init = 0.U(sizeof(n).W))
+  val is_full      = Reg(init = false.B)
+  val do_enq       = io.enq_rdy && io.enq_val
+  val do_deq       = io.deq_rdy && io.deq_val
+  val is_empty     = !is_full && (enq_ptr === deq_ptr)
+  val deq_ptr_inc  = deq_ptr + 1.U
+  val enq_ptr_inc  = enq_ptr + 1.U
+  val is_full_next = 
+    Mux(do_enq && ~do_deq && (enq_ptr_inc === deq_ptr), 
+        true.B,
+        Mux(do_deq && is_full, false.B, is_full))
+  enq_ptr := Mux(do_enq, enq_ptr_inc, enq_ptr)
+  deq_ptr := Mux(do_deq, deq_ptr_inc, deq_ptr)
+  is_full := is_full_next
+  val ram = Mem(n)
+  when (do_enq) {
+    ram(enq_ptr) := io.enq_dat
+  }
+  io.enq_rdy := !is_full
+  io.deq_val := !is_empty
+  ram(deq_ptr) <> io.deq_dat
+}
+\end{scala}
+\caption{Parameterized FIFO example.}
+\label{fig:fifo}
+\end{figure}
+
+It is also possible to define a generic decoupled interface:
+
+\begin{scala}
+class DecoupledIO[T <: Data](data: T) 
+    extends Bundle {
+  val ready = Input(Bool())
+  val valid = Output(Bool())
+  val bits  = data.cloneType.asOutput
+}
+\end{scala}
+
+\noindent
+This template can then be used to add a handshaking protocol to any
+set of signals:
+
+\begin{scala}
+class DecoupledDemo 
+  extends DecoupledIO()( new DataBundle )
+\end{scala}
+
+\noindent
+The FIFO interface in Figure~\ref{fig:fifo} can be now be simplified as
+follows: 
+
+\begin{scala}
+class Fifo[T <: Data] (data: T, n: Int) 
+    extends Module {
+  val io = IO(new Bundle {
+    val enq = new DecoupledIO( data ).flip()
+    val deq = new DecoupledIO( data )
+  })
+  ...
+}
+\end{scala}
+
+
+\section{Multiple Clock Domains}
+
+Chisel 3.0 does not yet support of multiple clock domains. That support will be coming shortly.
+
+
+\section{Acknowlegements}
+
+Many people have helped out in the design of Chisel, and we thank them
+for their patience, bravery, and belief in a better way.  Many
+Berkeley EECS students in the Isis group gave weekly feedback as the
+design evolved including but not limited to Yunsup Lee, Andrew
+Waterman, Scott Beamer, Chris Celio, etc.  Yunsup Lee gave us feedback
+in response to the first RISC-V implementation, called TrainWreck,
+translated from Verilog to Chisel.  Andrew Waterman and Yunsup Lee
+helped us get our Verilog backend up and running and Chisel TrainWreck
+running on an FPGA.  Brian Richards was the first actual Chisel user,
+first translating (with Huy Vo) John Hauser's FPU Verilog code to
+Chisel, and later implementing generic memory blocks.  Brian gave many
+invaluable comments on the design and brought a vast experience in
+hardware design and design tools.  Chris Batten shared his fast
+multiword C++ template library that inspired our fast emulation
+library.  Huy Vo became our undergraduate research assistant and was
+the first to actually assist in the Chisel implementation.  We
+appreciate all the EECS students who participated in the Chisel
+bootcamp and proposed and worked on hardware design projects all of
+which pushed the Chisel envelope.  We appreciate the work that James
+Martin and Alex Williams did in writing and translating network and
+memory controllers and non-blocking caches.  Finally, Chisel's
+functional programming and bit-width inference ideas were inspired by
+earlier work on a hardware description language called Gel~\cite{gel} designed in
+collaboration with Dany Qumsiyeh and Mark Tobenkin.
+
+% \note{Who else?}
+
+\begin{thebibliography}{50}
+\bibitem{chisel-dac12} Bachrach, J., Vo, H., Richards, B., Lee, Y., Waterman,
+  A., Avi\v{z}ienis, Wawrzynek, J., Asanovi\'{c} \textsl{Chisel:
+    Constructing Hardware in a Scala Embedded Language}.
+in DAC '12.
+\bibitem{gel} Bachrach, J., Qumsiyeh, D., Tobenkin, M. \textsl{Hardware Scripting in Gel}.
+in Field-Programmable Custom Computing Machines, 2008. FCCM '08. 16th.
+\end{thebibliography}
+
+\end{document}
diff --git a/chisel/Buraq-mini/RV32i/instructions b/chisel/Buraq-mini/RV32i/instructions
new file mode 100644
index 0000000..c3658a4
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/instructions
@@ -0,0 +1,3 @@
+01700513
+01800593
+01900613
diff --git a/chisel/Buraq-mini/RV32i/project/build.properties b/chisel/Buraq-mini/RV32i/project/build.properties
new file mode 100644
index 0000000..210243d
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/project/build.properties
@@ -0,0 +1 @@
+sbt.version = 1.1.1
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/common/ALU_operations_Sel.scala b/chisel/Buraq-mini/RV32i/src/main/scala/common/ALU_operations_Sel.scala
new file mode 100644
index 0000000..cfdb39c
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/common/ALU_operations_Sel.scala
@@ -0,0 +1,61 @@
+package common
+
+
+import chisel3._
+import chisel3.util._
+
+class ALU_operations_Sel(func3 : UInt, func7 : UInt, AluOp : UInt)
+{
+     def JAL    : Bool  = { AluOp === "b0011".U  }
+     def LUI    : Bool  = { AluOp === "b0110".U  }
+     def AUIPC  : Bool  = { AluOp === "b0111".U  }
+     def ADDI   : Bool  = { func3 === "b000".U  && AluOp==="b0001".U  }
+     def SLTI   : Bool  = { func3 === "b010".U  && AluOp==="b0001".U  }
+     def SLTIU  : Bool  = { func3 === "b011".U  && AluOp==="b0001".U  }
+     def XORI   : Bool  = { func3 === "b100".U  && AluOp==="b0001".U  }
+     def ORI    : Bool  = { func3 === "b110".U  && AluOp==="b0001".U  }
+     def ANDI   : Bool  = { func3 === "b111".U  && AluOp==="b0001".U  }
+     def BEQ    : Bool  = { func3 === "b000".U  && AluOp==="b0010".U  }
+     def BNE    : Bool  = { func3 === "b001".U  && AluOp==="b0010".U  }
+     def BLT    : Bool  = { func3 === "b100".U  && AluOp==="b0010".U  }
+     def BGE    : Bool  = { func3 === "b101".U  && AluOp==="b0010".U  }
+     def BLTU   : Bool  = { func3 === "b110".U  && AluOp==="b0010".U  }
+     def BGEU   : Bool  = { func3 === "b111".U  && AluOp==="b0010".U  }
+     def JALR   : Bool  = { func3 === "b000".U  && AluOp==="b0011".U  }
+     def LB     : Bool  = { func3 === "b000".U  && AluOp==="b0100".U  }
+     def LH     : Bool  = { func3 === "b001".U  && AluOp==="b0100".U  }
+     def LW     : Bool  = { func3 === "b010".U  && AluOp==="b0100".U  }
+     def LBU    : Bool  = { func3 === "b100".U  && AluOp==="b0100".U  }
+     def LHU    : Bool  = { func3 === "b101".U  && AluOp==="b0100".U  }
+     def LWU    : Bool  = { func3 === "b110".U  && AluOp==="b0100".U  }
+     def SB     : Bool  = { func3 === "b000".U  && AluOp==="b0101".U  }
+     def SH     : Bool  = { func3 === "b001".U  && AluOp==="b0101".U  }
+     def SW     : Bool  = { func3 === "b010".U  && AluOp==="b0101".U  }
+     def SLLI   : Bool  = { func3 === "b001".U  && AluOp==="b0001".U  && func7 === "b0000000".U}
+     def SRLI   : Bool  = { func3 === "b101".U  && AluOp==="b0001".U  && func7 === "b0000000".U}
+     def SRAI   : Bool  = { func3 === "b101".U  && AluOp==="b0001".U  && func7 === "b0100000".U}
+     def ADD    : Bool  = { func3 === "b000".U  && AluOp==="b0000".U  && func7 === "b0000000".U}
+     def SUB    : Bool  = { func3 === "b000".U  && AluOp==="b0000".U  && func7 === "b0100000".U}
+     def SLL    : Bool  = { func3 === "b001".U  && AluOp==="b0000".U  && func7 === "b0000000".U}
+     def SLT    : Bool  = { func3 === "b010".U  && AluOp==="b0000".U  && func7 === "b0000000".U}
+     def SLTU   : Bool  = { func3 === "b011".U  && AluOp==="b0000".U  && func7 === "b0000000".U}
+     def XOR    : Bool  = { func3 === "b100".U  && AluOp==="b0000".U  && func7 === "b0000000".U}
+     def SRL    : Bool  = { func3 === "b101".U  && AluOp==="b0000".U  && func7 === "b0000000".U}
+     def SRA    : Bool  = { func3 === "b101".U  && AluOp==="b0000".U  && func7 === "b0100000".U}
+     def OR     : Bool  = { func3 === "b110".U  && AluOp==="b0000".U  && func7 === "b0000000".U}
+     def AND    : Bool  = { func3 === "b111".U  && AluOp==="b0000".U  && func7 === "b0000000".U}
+     def MUL    : Bool  = { func3 === "b000".U  && AluOp==="b1001".U  && func7 === "b0000001".U}
+     def MULH   : Bool  = { func3 === "b001".U  && AluOp==="b1001".U  && func7 === "b0000001".U}
+     def MULHSU : Bool  = { func3 === "b010".U  && AluOp==="b1001".U  && func7 === "b0000001".U}
+     def MULHU  : Bool  = { func3 === "b011".U  && AluOp==="b1001".U  && func7 === "b0000001".U}
+     def DIV    : Bool  = { func3 === "b100".U  && AluOp==="b1001".U  && func7 === "b0000001".U}
+     def DIVU   : Bool  = { func3 === "b101".U  && AluOp==="b1001".U  && func7 === "b0000001".U}
+     def REM    : Bool  = { func3 === "b110".U  && AluOp==="b1001".U  && func7 === "b0000001".U}
+     def REMU   : Bool  = { func3 === "b111".U  && AluOp==="b1001".U  && func7 === "b0000001".U}
+     def CSRRW  : Bool  = { func3 === "b001".U  && AluOp==="b1000".U}
+     def CSRRS  : Bool  = { func3 === "b010".U  && AluOp==="b1000".U}
+     def CSRRC  : Bool  = { func3 === "b011".U  && AluOp==="b1000".U}
+     def CSRRWI : Bool  = { func3 === "b101".U  && AluOp==="b1000".U}
+     def CSRRSI : Bool  = { func3 === "b110".U  && AluOp==="b1000".U}
+     def CSRRCI : Bool  = { func3 === "b111".U  && AluOp==="b1000".U}
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/.metals/metals.h2.db b/chisel/Buraq-mini/RV32i/src/main/scala/core/.metals/metals.h2.db
new file mode 100644
index 0000000..e23b54a
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/.metals/metals.h2.db
Binary files differ
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/.metals/metals.log b/chisel/Buraq-mini/RV32i/src/main/scala/core/.metals/metals.log
new file mode 100644
index 0000000..1dcfd83
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/.metals/metals.log
@@ -0,0 +1,2177 @@
+2020.09.13 01:53:57 INFO  started: Metals version 0.9.3 in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core' for client vscode.
+2020.09.13 01:53:59 INFO  time: initialize in 2.33s
+2020.09.13 01:54:00 WARN  no build tool detected in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core'. The most common cause for this problem is that the editor was opened in the wrong working directory, for example if you use sbt then the workspace directory should contain build.sbt. 
+2020.09.13 01:54:00 INFO  no build target: using presentation compiler with only scala-library
+2020.09.13 01:54:05 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 01:55:00 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 01:55:32 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 01:55:39 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Pc.scala
+2020.09.13 01:55:44 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Pc.scala
+2020.09.13 01:55:57 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Pc.scala
+2020.09.13 01:55:59 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Pc.scala
+2020.09.13 01:56:02 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Pc.scala
+2020.09.13 01:56:04 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Pc.scala
+2020.09.13 01:56:06 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Pc.scala
+2020.09.13 01:56:09 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Pc.scala
+2020.09.13 01:56:25 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/IF_ID.scala
+2020.09.13 01:57:45 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 01:57:47 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 01:58:02 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 01:58:19 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 01:58:21 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 01:58:22 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:00:09 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Core.scala
+2020.09.13 02:08:56 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:09:01 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:09:03 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:09:05 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:09:06 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:09:08 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:09:09 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:09:40 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:09:43 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:10:36 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:10:40 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:11:10 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:11:11 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:11:35 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:11:40 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:11:41 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:11:59 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:12:02 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:12:05 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:12:10 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:12:12 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:12:16 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:12:18 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:12:23 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:12:25 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:12:26 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:12:34 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:12:38 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:12:41 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:12:57 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:15:42 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 02:23:27 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/test/scala/core/Launcher.scala
+2020.09.13 02:23:56 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/test/scala/core/Launcher.scala
+2020.09.13 02:26:46 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/test/scala/core/Load_unitTests.scala
+2020.09.13 02:28:22 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/test/scala/core/Launcher.scala
+2020.09.13 02:29:26 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/test/scala/core/PcTests.scala
+2020.09.13 02:29:32 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/test/scala/core/PcTests.scala
+2020.09.13 02:29:37 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/test/scala/core/PcTests.scala
+2020.09.13 02:29:46 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/test/scala/core/FetchTests.scala
+2020.09.13 02:29:51 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/test/scala/core/FetchTests.scala
+2020.09.13 02:40:19 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/test/scala/core/Launcher.scala
+2020.09.13 02:40:32 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/test/scala/core/Launcher.scala
+2020.09.13 02:40:34 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/test/scala/core/Launcher.scala
+2020.09.13 02:40:47 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.13 02:40:52 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.13 02:40:59 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.13 02:43:40 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.13 04:28:23 INFO  shutting down Metals
+2020.09.14 01:35:11 INFO  started: Metals version 0.9.3 in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core' for client vscode.
+2020.09.14 01:35:13 INFO  time: initialize in 2.04s
+2020.09.14 01:35:14 WARN  no build tool detected in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core'. The most common cause for this problem is that the editor was opened in the wrong working directory, for example if you use sbt then the workspace directory should contain build.sbt. 
+2020.09.14 01:35:14 INFO  no build target: using presentation compiler with only scala-library
+2020.09.14 01:35:18 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.14 01:35:52 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 03:19:03 INFO  shutting down Metals
+2020.09.14 12:49:54 INFO  started: Metals version 0.9.3 in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core' for client vscode.
+2020.09.14 12:49:56 INFO  time: initialize in 2.28s
+2020.09.14 12:49:57 WARN  no build tool detected in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core'. The most common cause for this problem is that the editor was opened in the wrong working directory, for example if you use sbt then the workspace directory should contain build.sbt. 
+2020.09.14 12:49:57 INFO  no build target: using presentation compiler with only scala-library
+2020.09.14 12:50:00 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:50:45 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.14 12:52:05 WARN  no build tool detected in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core'. The most common cause for this problem is that the editor was opened in the wrong working directory, for example if you use sbt then the workspace directory should contain build.sbt. 
+2020.09.14 12:52:21 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:52:22 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:52:24 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:52:27 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:52:30 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:52:31 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:52:33 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:52:35 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:52:37 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:52:42 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:52:44 WARN  no build tool detected in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core'. The most common cause for this problem is that the editor was opened in the wrong working directory, for example if you use sbt then the workspace directory should contain build.sbt. 
+2020.09.14 12:52:44 WARN  no build tool detected in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core'. The most common cause for this problem is that the editor was opened in the wrong working directory, for example if you use sbt then the workspace directory should contain build.sbt. 
+2020.09.14 12:52:46 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:52:50 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:52:52 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:52:57 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:52:59 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:53:01 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:53:27 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:53:35 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:54:11 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:58:42 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:58:51 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 12:59:02 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.14 12:59:24 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.14 12:59:30 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.14 12:59:34 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.14 12:59:48 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.14 12:59:52 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.14 12:59:54 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.14 13:00:02 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.14 13:00:11 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.14 13:00:19 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.14 13:00:41 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 13:00:43 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 13:01:14 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 13:01:36 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.14 13:02:01 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/RegisterFile.scala
+2020.09.14 13:02:11 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/RegisterFile.scala
+2020.09.14 13:02:35 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/RegisterFile.scala
+2020.09.14 13:02:40 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/RegisterFile.scala
+2020.09.14 13:02:50 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
+2020.09.14 13:03:13 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Pc.scala
+2020.09.14 13:03:25 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
+2020.09.14 13:03:30 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
+2020.09.14 13:03:37 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
+2020.09.14 13:03:46 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
+2020.09.14 13:03:52 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
+2020.09.14 13:04:08 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/InstructionTypeDecode.scala
+2020.09.14 13:04:20 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/InstructionTypeDecode.scala
+2020.09.14 13:04:44 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/InstructionTypeDecode.scala
+2020.09.14 13:04:46 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/InstructionTypeDecode.scala
+2020.09.14 13:04:50 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/InstructionTypeDecode.scala
+2020.09.14 13:04:56 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/InstructionTypeDecode.scala
+2020.09.14 13:05:05 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ControlDecode.scala
+2020.09.14 13:05:10 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ControlDecode.scala
+2020.09.14 13:05:22 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ControlDecode.scala
+2020.09.14 13:05:39 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ControlDecode.scala
+2020.09.14 13:05:46 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ControlDecode.scala
+2020.09.14 13:05:47 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ControlDecode.scala
+2020.09.14 13:05:49 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ControlDecode.scala
+2020.09.14 13:06:32 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Control.scala
+2020.09.14 13:06:39 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Control.scala
+2020.09.14 13:06:43 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Control.scala
+2020.09.14 13:07:12 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Control.scala
+2020.09.14 13:07:43 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Execute.scala
+2020.09.14 13:07:51 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Execute.scala
+2020.09.14 13:08:05 WARN  no build tool detected in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core'. The most common cause for this problem is that the editor was opened in the wrong working directory, for example if you use sbt then the workspace directory should contain build.sbt. 
+Sep 14, 2020 1:08:05 PM scala.meta.internal.pc.CompilerAccess retryWithCleanCompiler
+INFO: compiler crashed due to an error in the Scala compiler, retrying with new compiler instance.
+Sep 14, 2020 1:08:05 PM scala.meta.internal.pc.CompilerAccess handleError
+SEVERE: 
+  unexpected tree: class scala.reflect.internal.Trees$Template
+<Bundle: error> {
+  def <init>(): <$anon: <error>> = {
+    super.<init>();
+    ()
+  };
+  private[this] val <EX_MEM_rd_sel: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <MEM_WB_rd_sel: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <ID_EX_rs1_sel: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <ID_EX_rs2_sel: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <EX_MEM_ctrl_RegWr: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <MEM_WB_ctrl_RegWr: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ID_EX_ctrl_OpA_sel: error>: <error> = <Input: error>(<UInt: error>(2.<W: error>));
+  private[this] val <ID_EX_ctrl_OpB_sel: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ID_EX_pc4: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <ID_EX_pc_out: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <ID_EX_rs1: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <ID_EX_rs2: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <EX_MEM_alu_output: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <writeback_write_data: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <ID_EX_imm: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <ID_EX_ctrl_AluOp: error>: <error> = <Input: error>(<UInt: error>(4.<W: error>));
+  private[this] val <ID_EX_func7: error>: <error> = <Input: error>(<UInt: error>(7.<W: error>));
+  private[this] val <ID_EX_func3: error>: <error> = <Input: error>(<UInt: error>(3.<W: error>));
+  private[this] val <ID_EX_rd_sel: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <ID_EX_ctrl_MemWr: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ID_EX_ctrl_MemRd: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ID_EX_ctrl_RegWr: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ID_EX_ctrl_MemToReg: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <rs2_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <alu_output: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rd_sel_out: error>: <error> = <Output: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs2_sel_out: error>: <error> = <Output: error>(<UInt: error>(5.<W: error>));
+  private[this] val <ctrl_MemWr_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_MemRd_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_RegWr_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_MemToReg_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <func3_out: error>: <error> = <Output: error>(<UInt: error>(3.<W: error>))
+}
+     while compiling: file:///home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Execute.scala
+        during phase: globalPhase=<no phase>, enteringPhase=parser
+     library version: version 2.12.12
+    compiler version: version 2.12.12
+  reconstructed args: -classpath /home/sajjad/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.12/scala-library-2.12.12.jar -Ymacro-expand:discard -Ycache-plugin-class-loader:last-modified -Ypresentation-any-thread
+
+  last tree to typer: Template(value <local $anon>)
+       tree position: line 6 of file:///home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Execute.scala
+              symbol: value <local $anon>
+   symbol definition: val <local $anon>: <notype> (a TermSymbol)
+      symbol package: core
+       symbol owners: value <local $anon> -> <$anon: <error>> -> value io -> class Execute
+           call site: <none> in <none>
+
+== Source file context for tree position ==
+
+     3 import chisel3._
+     4 
+     5 class Execute extends Module {
+     6   val io = IO(new Bundle {
+     7     val EX_MEM_rd_sel = Input(UInt(5.W))
+     8     val MEM_WB_rd_sel = Input(UInt(5.W))
+     9     val ID_EX_rs1_sel = Input(UInt(5.W))
+scala.reflect.internal.FatalError: 
+  unexpected tree: class scala.reflect.internal.Trees$Template
+<Bundle: error> {
+  def <init>(): <$anon: <error>> = {
+    super.<init>();
+    ()
+  };
+  private[this] val <EX_MEM_rd_sel: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <MEM_WB_rd_sel: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <ID_EX_rs1_sel: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <ID_EX_rs2_sel: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <EX_MEM_ctrl_RegWr: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <MEM_WB_ctrl_RegWr: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ID_EX_ctrl_OpA_sel: error>: <error> = <Input: error>(<UInt: error>(2.<W: error>));
+  private[this] val <ID_EX_ctrl_OpB_sel: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ID_EX_pc4: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <ID_EX_pc_out: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <ID_EX_rs1: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <ID_EX_rs2: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <EX_MEM_alu_output: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <writeback_write_data: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <ID_EX_imm: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <ID_EX_ctrl_AluOp: error>: <error> = <Input: error>(<UInt: error>(4.<W: error>));
+  private[this] val <ID_EX_func7: error>: <error> = <Input: error>(<UInt: error>(7.<W: error>));
+  private[this] val <ID_EX_func3: error>: <error> = <Input: error>(<UInt: error>(3.<W: error>));
+  private[this] val <ID_EX_rd_sel: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <ID_EX_ctrl_MemWr: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ID_EX_ctrl_MemRd: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ID_EX_ctrl_RegWr: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ID_EX_ctrl_MemToReg: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <rs2_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <alu_output: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rd_sel_out: error>: <error> = <Output: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs2_sel_out: error>: <error> = <Output: error>(<UInt: error>(5.<W: error>));
+  private[this] val <ctrl_MemWr_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_MemRd_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_RegWr_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_MemToReg_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <func3_out: error>: <error> = <Output: error>(<UInt: error>(3.<W: error>))
+}
+     while compiling: file:///home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Execute.scala
+        during phase: globalPhase=<no phase>, enteringPhase=parser
+     library version: version 2.12.12
+    compiler version: version 2.12.12
+  reconstructed args: -classpath /home/sajjad/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.12/scala-library-2.12.12.jar -Ymacro-expand:discard -Ycache-plugin-class-loader:last-modified -Ypresentation-any-thread
+
+  last tree to typer: Template(value <local $anon>)
+       tree position: line 6 of file:///home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Execute.scala
+              symbol: value <local $anon>
+   symbol definition: val <local $anon>: <notype> (a TermSymbol)
+      symbol package: core
+       symbol owners: value <local $anon> -> <$anon: <error>> -> value io -> class Execute
+           call site: <none> in <none>
+
+== Source file context for tree position ==
+
+     3 import chisel3._
+     4 
+     5 class Execute extends Module {
+     6   val io = IO(new Bundle {
+     7     val EX_MEM_rd_sel = Input(UInt(5.W))
+     8     val MEM_WB_rd_sel = Input(UInt(5.W))
+     9     val ID_EX_rs1_sel = Input(UInt(5.W))
+	at scala.reflect.internal.Reporting.abort(Reporting.scala:68)
+	at scala.reflect.internal.Reporting.abort$(Reporting.scala:64)
+	at scala.reflect.internal.SymbolTable.abort(SymbolTable.scala:28)
+	at scala.tools.nsc.typechecker.Typers$Typer.typedOutsidePatternMode$1(Typers.scala:5671)
+	at scala.tools.nsc.typechecker.Typers$Typer.typed1(Typers.scala:5688)
+	at scala.tools.nsc.typechecker.Typers$Typer.typed(Typers.scala:5724)
+	at scala.tools.nsc.typechecker.Typers$Typer.typedQualifier(Typers.scala:5808)
+	at scala.meta.internal.pc.PcDefinitionProvider.definitionTypedTreeAt(PcDefinitionProvider.scala:111)
+	at scala.meta.internal.pc.PcDefinitionProvider.definition(PcDefinitionProvider.scala:24)
+
+2020.09.14 13:08:15 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Execute.scala
+2020.09.14 13:08:18 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/AluControl.scala
+2020.09.14 13:08:24 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/AluControl.scala
+2020.09.14 13:08:36 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/AluControl.scala
+2020.09.14 13:08:37 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/AluControl.scala
+2020.09.14 13:08:43 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/AluControl.scala
+2020.09.14 13:10:08 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/BranchLogic.scala
+2020.09.14 13:10:16 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ImmediateGeneration.scala
+2020.09.14 13:10:21 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 13:10:34 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Store_unit.scala
+2020.09.14 13:10:37 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/WriteBack.scala
+2020.09.14 13:11:41 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ImmediateGeneration.scala
+2020.09.14 13:16:24 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Staller.scala
+2020.09.14 13:18:03 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:09:58 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 2:10:02 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 14:10:03 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:10:48 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:10:53 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 2:10:54 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 2:10:55 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 2:10:55 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 14:10:56 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 2:11:00 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 2:11:00 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 2:11:00 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 2:11:00 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 2:11:01 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 14:11:02 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 2:11:04 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 2:11:04 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 2:11:04 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 14:11:07 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 2:11:12 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 2:11:13 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 2:11:13 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 2:11:13 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 14:11:14 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 2:11:16 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 14:11:17 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 2:11:19 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 14:11:20 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:11:25 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:11:28 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:11:30 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:11:34 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:11:35 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 2:11:38 PM scala.meta.internal.pc.CompletionProvider expected$1
+WARNING: offset 467, count -46, length 1114
+Sep 14, 2020 2:11:39 PM scala.meta.internal.pc.CompletionProvider expected$1
+WARNING: offset 468, count -46, length 1115
+2020.09.14 14:11:40 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:11:43 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:11:46 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:11:47 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:11:48 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:11:50 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:12:14 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 2:12:16 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 2:12:16 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 2:12:16 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 14:12:17 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 2:12:20 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 14:12:22 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:12:23 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 2:12:25 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 2:12:25 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 2:12:25 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 2:12:25 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 14:12:26 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 2:12:27 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 2:12:28 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 14:12:29 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:12:37 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:12:41 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:12:43 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 2:12:45 PM scala.meta.internal.pc.CompletionProvider expected$1
+WARNING: offset 543, count -42, length 1153
+Sep 14, 2020 2:12:45 PM scala.meta.internal.pc.CompletionProvider expected$1
+WARNING: offset 544, count -42, length 1154
+2020.09.14 14:12:46 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:12:48 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:13:10 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:13:12 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:13:14 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 14:13:17 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:24:48 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:27:20 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:27:20 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:27:20 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:27:22 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:27:29 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:27:31 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:27:34 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:27:36 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:27:36 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:27:37 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:27:37 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:27:38 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:27:40 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:27:43 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:27:46 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:27:48 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:27:55 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:27:57 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:27:59 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:28:03 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:28:08 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:29:10 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:29:16 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:29:18 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:30:29 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:30:33 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:30:45 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:30:57 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:30:58 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:30:58 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:30:58 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:31:00 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:31:01 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:31:02 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:31:03 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:31:06 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:31:10 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:31:10 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:31:11 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:31:12 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:31:13 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:31:13 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:31:14 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:31:17 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:31:19 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:31:21 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:31:25 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:31:28 PM scala.meta.internal.pc.CompletionProvider expected$1
+WARNING: offset 427, count -44, length 1230
+Sep 14, 2020 4:31:29 PM scala.meta.internal.pc.CompletionProvider expected$1
+WARNING: offset 428, count -44, length 1231
+2020.09.14 16:31:30 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:33:26 WARN  no build tool detected in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core'. The most common cause for this problem is that the editor was opened in the wrong working directory, for example if you use sbt then the workspace directory should contain build.sbt. 
+2020.09.14 16:33:29 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:33:38 WARN  no build tool detected in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core'. The most common cause for this problem is that the editor was opened in the wrong working directory, for example if you use sbt then the workspace directory should contain build.sbt. 
+2020.09.14 16:33:39 WARN  no build tool detected in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core'. The most common cause for this problem is that the editor was opened in the wrong working directory, for example if you use sbt then the workspace directory should contain build.sbt. 
+2020.09.14 16:33:53 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:34:19 WARN  no build tool detected in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core'. The most common cause for this problem is that the editor was opened in the wrong working directory, for example if you use sbt then the workspace directory should contain build.sbt. 
+2020.09.14 16:34:21 WARN  no build tool detected in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core'. The most common cause for this problem is that the editor was opened in the wrong working directory, for example if you use sbt then the workspace directory should contain build.sbt. 
+2020.09.14 16:34:21 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:34:43 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:35:22 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:36:59 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:37:00 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:37:00 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:37:00 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:37:01 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:37:05 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:37:07 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:37:08 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:37:09 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:37:09 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:37:10 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:37:13 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:37:20 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:37:24 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:37:27 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:37:28 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:37:32 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:37:32 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:37:32 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:37:32 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:37:33 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:37:35 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:37:38 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:37:39 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:37:39 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:37:40 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:37:40 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:37:41 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:37:42 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:37:42 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:37:45 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:37:48 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:37:50 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:37:53 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:43:01 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:43:03 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:43:03 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:43:04 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:500)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:43:05 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:43:06 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:43:08 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:43:09 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:43:10 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+Sep 14, 2020 4:43:10 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+Sep 14, 2020 4:43:11 PM scala.meta.internal.pc.completions.Completions completionPosition
+SEVERE: null
+java.lang.NullPointerException
+	at scala.meta.internal.pc.completions.OverrideCompletions$OverrideCompletion.<init>(OverrideCompletions.scala:46)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe(Completions.scala:478)
+	at scala.meta.internal.pc.completions.Completions.completionPositionUnsafe$(Completions.scala:409)
+	at scala.meta.internal.pc.MetalsGlobal.completionPositionUnsafe(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.completions.Completions.completionPosition(Completions.scala:401)
+	at scala.meta.internal.pc.completions.Completions.completionPosition$(Completions.scala:386)
+	at scala.meta.internal.pc.MetalsGlobal.completionPosition(MetalsGlobal.scala:29)
+	at scala.meta.internal.pc.CompletionProvider.safeCompletionsAt(CompletionProvider.scala:444)
+	at scala.meta.internal.pc.CompletionProvider.completions(CompletionProvider.scala:57)
+	at scala.meta.internal.pc.ScalaPresentationCompiler.$anonfun$complete$1(ScalaPresentationCompiler.scala:184)
+	at scala.meta.internal.pc.CompilerAccess.withSharedCompiler(CompilerAccess.scala:137)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$withInterruptableCompiler$1(CompilerAccess.scala:87)
+	at scala.meta.internal.pc.CompilerAccess.$anonfun$onCompilerJobQueue$1(CompilerAccess.scala:197)
+	at scala.meta.internal.pc.CompilerJobQueue$Job.run(CompilerJobQueue.scala:103)
+	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
+	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
+	at java.base/java.lang.Thread.run(Thread.java:834)
+
+2020.09.14 16:43:13 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:43:19 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:43:24 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:43:26 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:43:28 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.14 16:44:03 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
+2020.09.14 16:44:08 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
+2020.09.14 16:44:27 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
+2020.09.14 16:44:45 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
+2020.09.14 16:44:50 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
+2020.09.14 16:45:08 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Execute.scala
+2020.09.14 16:45:47 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Execute.scala
+2020.09.14 16:45:52 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Execute.scala
+2020.09.14 16:46:01 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.14 16:46:29 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.14 16:46:42 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.14 16:46:54 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.14 16:47:00 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.14 18:40:29 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.14 18:40:38 WARN  no build tool detected in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core'. The most common cause for this problem is that the editor was opened in the wrong working directory, for example if you use sbt then the workspace directory should contain build.sbt. 
+Sep 14, 2020 6:40:38 PM scala.meta.internal.pc.CompilerAccess retryWithCleanCompiler
+INFO: compiler crashed due to an error in the Scala compiler, retrying with new compiler instance.
+Sep 14, 2020 6:40:38 PM scala.meta.internal.pc.CompilerAccess handleError
+SEVERE: 
+  unexpected tree: class scala.reflect.internal.Trees$Template
+<Bundle: error> {
+  def <init>(): <$anon: <error>> = {
+    super.<init>();
+    ()
+  };
+  private[this] val <pc_in: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <pc4_in: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rs1_sel_in: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs2_sel_in: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs1_in: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rs2_in: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <imm: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rd_sel_in: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <func3_in: error>: <error> = <Input: error>(<UInt: error>(3.<W: error>));
+  private[this] val <func7_in: error>: <error> = <Input: error>(<UInt: error>(7.<W: error>));
+  private[this] val <ctrl_MemWr_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_Branch_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_RegWr_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_MemToReg_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_AluOp_in: error>: <error> = <Input: error>(<UInt: error>(4.<W: error>));
+  private[this] val <ctrl_OpA_sel_in: error>: <error> = <Input: error>(<UInt: error>(2.<W: error>));
+  private[this] val <ctrl_OpB_sel_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_nextPc_sel_in: error>: <error> = <Input: error>(<UInt: error>(2.<W: error>));
+  private[this] val <pc_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <pc4_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rs1_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rs2_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <imm_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <func3_out: error>: <error> = <Output: error>(<UInt: error>(3.<W: error>));
+  private[this] val <func7_out: error>: <error> = <Output: error>(<UInt: error>(7.<W: error>));
+  private[this] val <rd_sel_out: error>: <error> = <Output: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs1_sel_out: error>: <error> = <Output: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs2_sel_out: error>: <error> = <Output: error>(<UInt: error>(5.<W: error>));
+  private[this] val <ctrl_MemWr_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_Branch_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_RegWr_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_MemToReg_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_AluOp_out: error>: <error> = <Output: error>(<UInt: error>(4.<W: error>));
+  private[this] val <ctrl_OpA_sel_out: error>: <error> = <Output: error>(<UInt: error>(2.<W: error>));
+  private[this] val <ctrl_OpB_sel_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_nextPc_sel_out: error>: <error> = <Output: error>(<UInt: error>(2.<W: error>))
+}
+     while compiling: file:///home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+        during phase: globalPhase=<no phase>, enteringPhase=parser
+     library version: version 2.12.12
+    compiler version: version 2.12.12
+  reconstructed args: -classpath /home/sajjad/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.12/scala-library-2.12.12.jar -Ymacro-expand:discard -Ycache-plugin-class-loader:last-modified -Ypresentation-any-thread
+
+  last tree to typer: Template(value <local $anon>)
+       tree position: line 6 of file:///home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+              symbol: value <local $anon>
+   symbol definition: val <local $anon>: <notype> (a TermSymbol)
+      symbol package: core
+       symbol owners: value <local $anon> -> <$anon: <error>> -> value io -> class ID_EX
+           call site: <none> in <none>
+
+== Source file context for tree position ==
+
+     3 import chisel3._
+     4 
+     5 class ID_EX extends Module {
+     6     val io = IO(new Bundle {
+     7         val pc_in = Input(SInt(32.W))
+     8         val pc4_in = Input(SInt(32.W))
+     9         val rs1_sel_in = Input(UInt(5.W))
+scala.reflect.internal.FatalError: 
+  unexpected tree: class scala.reflect.internal.Trees$Template
+<Bundle: error> {
+  def <init>(): <$anon: <error>> = {
+    super.<init>();
+    ()
+  };
+  private[this] val <pc_in: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <pc4_in: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rs1_sel_in: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs2_sel_in: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs1_in: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rs2_in: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <imm: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rd_sel_in: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <func3_in: error>: <error> = <Input: error>(<UInt: error>(3.<W: error>));
+  private[this] val <func7_in: error>: <error> = <Input: error>(<UInt: error>(7.<W: error>));
+  private[this] val <ctrl_MemWr_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_Branch_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_RegWr_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_MemToReg_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_AluOp_in: error>: <error> = <Input: error>(<UInt: error>(4.<W: error>));
+  private[this] val <ctrl_OpA_sel_in: error>: <error> = <Input: error>(<UInt: error>(2.<W: error>));
+  private[this] val <ctrl_OpB_sel_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_nextPc_sel_in: error>: <error> = <Input: error>(<UInt: error>(2.<W: error>));
+  private[this] val <pc_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <pc4_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rs1_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rs2_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <imm_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <func3_out: error>: <error> = <Output: error>(<UInt: error>(3.<W: error>));
+  private[this] val <func7_out: error>: <error> = <Output: error>(<UInt: error>(7.<W: error>));
+  private[this] val <rd_sel_out: error>: <error> = <Output: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs1_sel_out: error>: <error> = <Output: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs2_sel_out: error>: <error> = <Output: error>(<UInt: error>(5.<W: error>));
+  private[this] val <ctrl_MemWr_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_Branch_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_RegWr_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_MemToReg_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_AluOp_out: error>: <error> = <Output: error>(<UInt: error>(4.<W: error>));
+  private[this] val <ctrl_OpA_sel_out: error>: <error> = <Output: error>(<UInt: error>(2.<W: error>));
+  private[this] val <ctrl_OpB_sel_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_nextPc_sel_out: error>: <error> = <Output: error>(<UInt: error>(2.<W: error>))
+}
+     while compiling: file:///home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+        during phase: globalPhase=<no phase>, enteringPhase=parser
+     library version: version 2.12.12
+    compiler version: version 2.12.12
+  reconstructed args: -classpath /home/sajjad/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.12/scala-library-2.12.12.jar -Ymacro-expand:discard -Ycache-plugin-class-loader:last-modified -Ypresentation-any-thread
+
+  last tree to typer: Template(value <local $anon>)
+       tree position: line 6 of file:///home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+              symbol: value <local $anon>
+   symbol definition: val <local $anon>: <notype> (a TermSymbol)
+      symbol package: core
+       symbol owners: value <local $anon> -> <$anon: <error>> -> value io -> class ID_EX
+           call site: <none> in <none>
+
+== Source file context for tree position ==
+
+     3 import chisel3._
+     4 
+     5 class ID_EX extends Module {
+     6     val io = IO(new Bundle {
+     7         val pc_in = Input(SInt(32.W))
+     8         val pc4_in = Input(SInt(32.W))
+     9         val rs1_sel_in = Input(UInt(5.W))
+	at scala.reflect.internal.Reporting.abort(Reporting.scala:68)
+	at scala.reflect.internal.Reporting.abort$(Reporting.scala:64)
+	at scala.reflect.internal.SymbolTable.abort(SymbolTable.scala:28)
+	at scala.tools.nsc.typechecker.Typers$Typer.typedOutsidePatternMode$1(Typers.scala:5671)
+	at scala.tools.nsc.typechecker.Typers$Typer.typed1(Typers.scala:5688)
+	at scala.tools.nsc.typechecker.Typers$Typer.typed(Typers.scala:5724)
+	at scala.tools.nsc.typechecker.Typers$Typer.typedQualifier(Typers.scala:5808)
+	at scala.meta.internal.pc.PcDefinitionProvider.definitionTypedTreeAt(PcDefinitionProvider.scala:111)
+	at scala.meta.internal.pc.PcDefinitionProvider.definition(PcDefinitionProvider.scala:24)
+
+2020.09.14 18:40:42 WARN  no build tool detected in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core'. The most common cause for this problem is that the editor was opened in the wrong working directory, for example if you use sbt then the workspace directory should contain build.sbt. 
+Sep 14, 2020 6:40:42 PM scala.meta.internal.pc.CompilerAccess retryWithCleanCompiler
+INFO: compiler crashed due to an error in the Scala compiler, retrying with new compiler instance.
+Sep 14, 2020 6:40:42 PM scala.meta.internal.pc.CompilerAccess handleError
+SEVERE: 
+  unexpected tree: class scala.reflect.internal.Trees$Template
+<Bundle: error> {
+  def <init>(): <$anon: <error>> = {
+    super.<init>();
+    ()
+  };
+  private[this] val <pc_in: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <pc4_in: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rs1_sel_in: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs2_sel_in: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs1_in: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rs2_in: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <imm: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rd_sel_in: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <func3_in: error>: <error> = <Input: error>(<UInt: error>(3.<W: error>));
+  private[this] val <func7_in: error>: <error> = <Input: error>(<UInt: error>(7.<W: error>));
+  private[this] val <ctrl_MemWr_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_Branch_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_RegWr_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_MemToReg_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_AluOp_in: error>: <error> = <Input: error>(<UInt: error>(4.<W: error>));
+  private[this] val <ctrl_OpA_sel_in: error>: <error> = <Input: error>(<UInt: error>(2.<W: error>));
+  private[this] val <ctrl_OpB_sel_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_nextPc_sel_in: error>: <error> = <Input: error>(<UInt: error>(2.<W: error>));
+  private[this] val <pc_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <pc4_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rs1_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rs2_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <imm_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <func3_out: error>: <error> = <Output: error>(<UInt: error>(3.<W: error>));
+  private[this] val <func7_out: error>: <error> = <Output: error>(<UInt: error>(7.<W: error>));
+  private[this] val <rd_sel_out: error>: <error> = <Output: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs1_sel_out: error>: <error> = <Output: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs2_sel_out: error>: <error> = <Output: error>(<UInt: error>(5.<W: error>));
+  private[this] val <ctrl_MemWr_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_Branch_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_RegWr_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_MemToReg_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_AluOp_out: error>: <error> = <Output: error>(<UInt: error>(4.<W: error>));
+  private[this] val <ctrl_OpA_sel_out: error>: <error> = <Output: error>(<UInt: error>(2.<W: error>));
+  private[this] val <ctrl_OpB_sel_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_nextPc_sel_out: error>: <error> = <Output: error>(<UInt: error>(2.<W: error>))
+}
+     while compiling: file:///home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+        during phase: globalPhase=<no phase>, enteringPhase=parser
+     library version: version 2.12.12
+    compiler version: version 2.12.12
+  reconstructed args: -classpath /home/sajjad/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.12/scala-library-2.12.12.jar -Ymacro-expand:discard -Ycache-plugin-class-loader:last-modified -Ypresentation-any-thread
+
+  last tree to typer: Template(value <local $anon>)
+       tree position: line 6 of file:///home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+              symbol: value <local $anon>
+   symbol definition: val <local $anon>: <notype> (a TermSymbol)
+      symbol package: core
+       symbol owners: value <local $anon> -> <$anon: <error>> -> value io -> class ID_EX
+           call site: <none> in <none>
+
+== Source file context for tree position ==
+
+     3 import chisel3._
+     4 
+     5 class ID_EX extends Module {
+     6     val io = IO(new Bundle {
+     7         val pc_in = Input(SInt(32.W))
+     8         val pc4_in = Input(SInt(32.W))
+     9         val rs1_sel_in = Input(UInt(5.W))
+scala.reflect.internal.FatalError: 
+  unexpected tree: class scala.reflect.internal.Trees$Template
+<Bundle: error> {
+  def <init>(): <$anon: <error>> = {
+    super.<init>();
+    ()
+  };
+  private[this] val <pc_in: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <pc4_in: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rs1_sel_in: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs2_sel_in: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs1_in: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rs2_in: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <imm: error>: <error> = <Input: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rd_sel_in: error>: <error> = <Input: error>(<UInt: error>(5.<W: error>));
+  private[this] val <func3_in: error>: <error> = <Input: error>(<UInt: error>(3.<W: error>));
+  private[this] val <func7_in: error>: <error> = <Input: error>(<UInt: error>(7.<W: error>));
+  private[this] val <ctrl_MemWr_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_Branch_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_RegWr_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_MemToReg_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_AluOp_in: error>: <error> = <Input: error>(<UInt: error>(4.<W: error>));
+  private[this] val <ctrl_OpA_sel_in: error>: <error> = <Input: error>(<UInt: error>(2.<W: error>));
+  private[this] val <ctrl_OpB_sel_in: error>: <error> = <Input: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_nextPc_sel_in: error>: <error> = <Input: error>(<UInt: error>(2.<W: error>));
+  private[this] val <pc_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <pc4_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rs1_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <rs2_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <imm_out: error>: <error> = <Output: error>(<SInt: error>(32.<W: error>));
+  private[this] val <func3_out: error>: <error> = <Output: error>(<UInt: error>(3.<W: error>));
+  private[this] val <func7_out: error>: <error> = <Output: error>(<UInt: error>(7.<W: error>));
+  private[this] val <rd_sel_out: error>: <error> = <Output: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs1_sel_out: error>: <error> = <Output: error>(<UInt: error>(5.<W: error>));
+  private[this] val <rs2_sel_out: error>: <error> = <Output: error>(<UInt: error>(5.<W: error>));
+  private[this] val <ctrl_MemWr_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_Branch_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_RegWr_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_MemToReg_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_AluOp_out: error>: <error> = <Output: error>(<UInt: error>(4.<W: error>));
+  private[this] val <ctrl_OpA_sel_out: error>: <error> = <Output: error>(<UInt: error>(2.<W: error>));
+  private[this] val <ctrl_OpB_sel_out: error>: <error> = <Output: error>(<UInt: error>(1.<W: error>));
+  private[this] val <ctrl_nextPc_sel_out: error>: <error> = <Output: error>(<UInt: error>(2.<W: error>))
+}
+     while compiling: file:///home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+        during phase: globalPhase=<no phase>, enteringPhase=parser
+     library version: version 2.12.12
+    compiler version: version 2.12.12
+  reconstructed args: -classpath /home/sajjad/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.12/scala-library-2.12.12.jar -Ymacro-expand:discard -Ycache-plugin-class-loader:last-modified -Ypresentation-any-thread
+
+  last tree to typer: Template(value <local $anon>)
+       tree position: line 6 of file:///home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+              symbol: value <local $anon>
+   symbol definition: val <local $anon>: <notype> (a TermSymbol)
+      symbol package: core
+       symbol owners: value <local $anon> -> <$anon: <error>> -> value io -> class ID_EX
+           call site: <none> in <none>
+
+== Source file context for tree position ==
+
+     3 import chisel3._
+     4 
+     5 class ID_EX extends Module {
+     6     val io = IO(new Bundle {
+     7         val pc_in = Input(SInt(32.W))
+     8         val pc4_in = Input(SInt(32.W))
+     9         val rs1_sel_in = Input(UInt(5.W))
+	at scala.reflect.internal.Reporting.abort(Reporting.scala:68)
+	at scala.reflect.internal.Reporting.abort$(Reporting.scala:64)
+	at scala.reflect.internal.SymbolTable.abort(SymbolTable.scala:28)
+	at scala.tools.nsc.typechecker.Typers$Typer.typedOutsidePatternMode$1(Typers.scala:5671)
+	at scala.tools.nsc.typechecker.Typers$Typer.typed1(Typers.scala:5688)
+	at scala.tools.nsc.typechecker.Typers$Typer.typed(Typers.scala:5724)
+	at scala.tools.nsc.typechecker.Typers$Typer.typedQualifier(Typers.scala:5808)
+	at scala.meta.internal.pc.PcDefinitionProvider.definitionTypedTreeAt(PcDefinitionProvider.scala:111)
+	at scala.meta.internal.pc.PcDefinitionProvider.definition(PcDefinitionProvider.scala:24)
+
+2020.09.14 18:40:44 WARN  no build tool detected in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core'. The most common cause for this problem is that the editor was opened in the wrong working directory, for example if you use sbt then the workspace directory should contain build.sbt. 
+2020.09.14 18:40:44 WARN  no build tool detected in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core'. The most common cause for this problem is that the editor was opened in the wrong working directory, for example if you use sbt then the workspace directory should contain build.sbt. 
+2020.09.14 18:46:03 INFO  shutting down Metals
+2020.09.15 01:21:06 INFO  started: Metals version 0.9.3 in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core' for client vscode.
+2020.09.15 01:21:09 INFO  time: initialize in 2.42s
+2020.09.15 01:21:09 WARN  no build tool detected in workspace '/home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core'. The most common cause for this problem is that the editor was opened in the wrong working directory, for example if you use sbt then the workspace directory should contain build.sbt. 
+2020.09.15 01:21:09 INFO  no build target: using presentation compiler with only scala-library
+2020.09.15 01:21:14 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+Sep 15, 2020 1:21:14 AM org.eclipse.lsp4j.jsonrpc.RemoteEndpoint handleCancellation
+WARNING: Unmatched cancel notification for request id 8
+Sep 15, 2020 1:21:14 AM org.eclipse.lsp4j.jsonrpc.RemoteEndpoint handleCancellation
+WARNING: Unmatched cancel notification for request id 4
+2020.09.15 01:21:14 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.15 01:21:20 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.15 01:21:25 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.15 01:21:27 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.15 01:21:31 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
+2020.09.15 01:21:43 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
+2020.09.15 01:21:59 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Execute.scala
+2020.09.15 01:22:04 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Execute.scala
+2020.09.15 01:22:23 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/Execute.scala
+2020.09.15 01:22:34 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
+2020.09.15 01:22:41 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
+2020.09.15 01:22:46 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
+Sep 15, 2020 1:22:48 AM org.eclipse.lsp4j.jsonrpc.RemoteEndpoint handleCancellation
+WARNING: Unmatched cancel notification for request id 82
+2020.09.15 01:22:50 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
+2020.09.15 01:22:59 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
+2020.09.15 01:23:05 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
+2020.09.15 01:23:14 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.15 01:23:19 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.15 01:23:26 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.15 01:23:30 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.15 01:24:14 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.15 01:24:22 WARN  no build target for: /home/sajjad/Desktop/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
+2020.09.15 04:28:21 INFO  shutting down Metals
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/.vscode/settings.json b/chisel/Buraq-mini/RV32i/src/main/scala/core/.vscode/settings.json
new file mode 100644
index 0000000..32cfc61
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/.vscode/settings.json
@@ -0,0 +1,5 @@
+{
+    "files.watcherExclude": {
+        "**/target": true
+    }
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/Alu.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/Alu.scala
new file mode 100644
index 0000000..a87c361
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/Alu.scala
@@ -0,0 +1,145 @@
+package core
+
+import chisel3._
+import chisel3.util.Cat
+import chisel3.util._
+import common._
+class Alu extends Module {
+    val io = IO(new Bundle {
+        val oper_a = Input(SInt(32.W))
+        val oper_b = Input(SInt(32.W))
+        val aluCtrl = Input(UInt(5.W))
+        val output = Output(SInt(32.W))
+      //  val branch = Output(UInt(1.W))
+    })
+    
+
+    when(io.aluCtrl === "b00000".U) {
+        // ADD
+        io.output := io.oper_a + io.oper_b
+    } .elsewhen(io.aluCtrl === "b00001".U) {
+        // SLL/SLLI     // works for both signed and unsigned numbers
+        val shift_left_by = io.oper_b(4,0)
+        io.output := io.oper_a << shift_left_by
+    } .elsewhen(io.aluCtrl === "b00010".U) {
+        // SLT/SLTI
+        when(io.oper_a < io.oper_b) {
+            io.output := 1.S
+        } .otherwise {
+            io.output := 0.S
+        } 
+    } .elsewhen(io.aluCtrl === "b00011".U || io.aluCtrl === "b10110".U) {
+        // SLTU/SLTUI   BLTU
+        when(io.oper_a.asUInt < io.oper_b.asUInt) {
+            io.output := 1.S
+        } .otherwise {
+            io.output := 0.S
+        }
+    } .elsewhen(io.aluCtrl === "b00100".U) {
+        // XOR/XORI
+        io.output := io.oper_a ^ io.oper_b
+    } .elsewhen(io.aluCtrl === "b00101".U || io.aluCtrl === "b01101".U) {
+        // Since SRL/SRLI deals shifting unsigned numbers right and SRA/SRAI deals with shifting
+        // signed numbers right, chisel has the same operator of doing right shift for
+        // both the signed and unsigned numbers. So we combined the alu control signals
+        // of both the instructions here and performed the right shift.
+
+        // SRL/SRLI SRA/SRAI
+        val shift_right_by = io.oper_b(4,0)
+        io.output := io.oper_a >> shift_right_by
+    } .elsewhen(io.aluCtrl === "b00110".U) {
+        // OR/ORI
+        io.output := io.oper_a | io.oper_b
+    } .elsewhen(io.aluCtrl === "b00111".U) {
+        // AND/ANDI
+        io.output := io.oper_a & io.oper_b
+    } .elsewhen(io.aluCtrl === "b01000".U) {
+        // SUB
+        io.output := io.oper_a - io.oper_b
+    
+    } .elsewhen(io.aluCtrl === "b10000".U) {
+        // BEQ
+        when(io.oper_a === io.oper_b) {
+            io.output := 1.S
+        } .otherwise {
+            io.output := 0.S
+        }
+    } .elsewhen(io.aluCtrl === "b10001".U) {
+        // BNE
+        when(~(io.oper_a === io.oper_b)) {
+            io.output := 1.S
+        } .otherwise {
+            io.output := 0.S
+        }
+    } .elsewhen(io.aluCtrl === "b10100".U) {
+        // BLT
+        when(io.oper_a < io.oper_b) {
+            io.output := 1.S
+        } .otherwise {
+            io.output := 0.S
+        }
+    } .elsewhen(io.aluCtrl === "b10101".U) {
+        // BGE
+        when(io.oper_a >= io.oper_b) {
+            io.output := 1.S
+        } .otherwise {
+            io.output := 0.S
+        }
+    } .elsewhen(io.aluCtrl === "b10111".U) {
+        // BGEU
+        when(io.oper_a.asUInt >= io.oper_b.asUInt) {
+            io.output := 1.S
+        } .otherwise {
+            io.output := 0.S
+        }
+    } .elsewhen(io.aluCtrl === "b11111".U) {
+        // JALR/JAL/CSRRW
+        io.output := io.oper_a
+    }
+    .elsewhen(io.aluCtrl === 11.U)
+    {
+        io.output := io.oper_b
+    }
+    // M extension
+    .elsewhen(io.aluCtrl === 30.U)
+    {
+        io.output := io.oper_a * io.oper_b // MUL
+    }
+    .elsewhen(io.aluCtrl === 29.U)
+    {
+        io.output := io.oper_a / io.oper_b // DIV
+    }
+    .elsewhen(io.aluCtrl === 27.U)
+    {
+        io.output := ((io.oper_a.asUInt) / (io.oper_b.asUInt)).asSInt // DIVU
+    }
+    .elsewhen(io.aluCtrl === 26.U)
+    {
+        io.output := io.oper_a % io.oper_b // REM
+    }
+    .elsewhen(io.aluCtrl === 25.U)
+    {
+        io.output := ((io.oper_a.asUInt) % (io.oper_b.asUInt)).asSInt // REMU
+    }
+    .elsewhen(io.aluCtrl === 24.U)
+    {
+        val result_in_64bits_MULH = io.oper_a * io.oper_b // MULH
+        io.output := result_in_64bits_MULH(63,32).asSInt
+    }
+    .elsewhen(io.aluCtrl === 19.U)
+    {
+        val result_in_64bits_MULHSU = io.oper_a * io.oper_b.asUInt // MULHSU
+        io.output := result_in_64bits_MULHSU(63,32).asSInt
+    }
+    .elsewhen(io.aluCtrl === 18.U)
+    {
+        val result_in_64bits_MULHU = io.oper_a.asUInt * io.oper_b.asUInt // MULHU
+        io.output := result_in_64bits_MULHU(63,32).asSInt
+    }
+    .otherwise {
+        io.output := DontCare
+    }
+
+  
+
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/AluControl.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/AluControl.scala
new file mode 100644
index 0000000..dd9f25e
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/AluControl.scala
@@ -0,0 +1,45 @@
+package core
+
+import chisel3._
+import chisel3.util._
+import chisel3.util.Cat
+import common._
+
+class AluControl extends Module {
+    val io = IO(new Bundle {
+       // val M_extension = Input(UInt(1.W))
+        val aluOp = Input(UInt(4.W))
+        val func7 = Input(UInt(7.W))
+        val func3 = Input(UInt(3.W))
+        val output = Output(UInt(5.W))        
+    })
+
+    val AluOP = new ALU_operations_Sel( io.func3, io.func7, io.aluOp)
+    
+    when(AluOP.ADD || AluOP.ADDI || AluOP.SW || AluOP.SB || AluOP.SH || AluOP.LW || AluOP.LB || AluOP.LH || AluOP.LBU || AluOP.LHU || AluOP.LWU || AluOP.LUI || AluOP.AUIPC) 
+    { io.output := 0.U}
+    .elsewhen(AluOP.SLL || AluOP.SLLI) { io.output := 1.U}
+    .elsewhen(AluOP.SLT || AluOP.SLTI) { io.output := 2.U}
+    .elsewhen(AluOP.SLTU|| AluOP.SLTIU || AluOP.BLTU) { io.output := 3.U}
+    .elsewhen(AluOP.XOR || AluOP.XORI) { io.output := 4.U}
+    .elsewhen(AluOP.SRL || AluOP.SRLI || AluOP.SRA || AluOP.SRAI) { io.output := 5.U}
+    .elsewhen(AluOP.OR  || AluOP.ORI)  { io.output := 6.U}
+    .elsewhen(AluOP.AND || AluOP.ANDI) { io.output := 7.U}
+    .elsewhen(AluOP.SUB) { io.output := 8.U}
+    .elsewhen(AluOP.BEQ) { io.output := 16.U}
+    .elsewhen(AluOP.BNE) { io.output := 17.U}
+    .elsewhen(AluOP.BLT) { io.output := 20.U}
+    .elsewhen(AluOP.BGE) { io.output := 21.U}
+    .elsewhen(AluOP.BGEU){ io.output := 23.U}
+    .elsewhen(AluOP.JAL || AluOP.JALR || AluOP.CSRRW || AluOP.CSRRS || AluOP.CSRRC || AluOP.CSRRWI || AluOP.CSRRSI || AluOP.CSRRCI) { io.output := 31.U}  //making the ALU pass operand a on output
+    .elsewhen(AluOP.MUL) { io.output := 30.U}
+    .elsewhen(AluOP.DIV) { io.output := 29.U}
+    .elsewhen(AluOP.DIVU){ io.output := 27.U}
+    .elsewhen(AluOP.REM) { io.output := 26.U}
+    .elsewhen(AluOP.REMU){ io.output := 25.U}
+    .elsewhen(AluOP.MULH){ io.output := 24.U}
+    .elsewhen(AluOP.MULHSU) { io.output := 19.U}
+    .elsewhen(AluOP.MULHU) { io.output := 18.U}
+    .otherwise { io.output := DontCare}
+
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/BranchLogic.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/BranchLogic.scala
new file mode 100644
index 0000000..26b1a3a
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/BranchLogic.scala
@@ -0,0 +1,59 @@
+package core
+
+import chisel3._
+
+class BranchLogic extends Module {
+  val io = IO(new Bundle {
+    val in_rs1 = Input(SInt(32.W))
+    val in_rs2 = Input(SInt(32.W))
+    val in_func3 = Input(UInt(3.W))
+    val output = Output(UInt(1.W))
+  })
+
+  when(io.in_func3 === "b000".U) {
+    // BEQ
+    when(io.in_rs1 === io.in_rs2) {
+      io.output := 1.U
+    } .otherwise {
+      io.output := 0.U
+    }
+  } .elsewhen(io.in_func3 === "b001".U) {
+    // BNE
+    when(io.in_rs1 =/= io.in_rs2) {
+      io.output := 1.U
+    } .otherwise {
+      io.output := 0.U
+    }
+  } .elsewhen(io.in_func3 === "b100".U) {
+    // BLT
+    when(io.in_rs1 < io.in_rs2) {
+      io.output := 1.U
+    } .otherwise {
+      io.output := 0.U
+    }
+  } .elsewhen(io.in_func3 === "b101".U) {
+    // BGE
+    when(io.in_rs1 >= io.in_rs2) {
+      io.output := 1.U
+    } .otherwise {
+      io.output := 0.U
+    }
+  } .elsewhen(io.in_func3 === "b110".U) {
+    // BLTU
+    when(io.in_rs1.asUInt < io.in_rs2.asUInt) {
+      io.output := 1.U
+    } .otherwise {
+      io.output := 0.U
+    }
+  } .elsewhen(io.in_func3 === "b111".U) {
+    // BGEU
+    when(io.in_rs1.asUInt >= io.in_rs2.asUInt) {
+      io.output := 1.U
+    } .otherwise {
+      io.output := 0.U
+    }
+  } .otherwise {
+    io.output := 0.U
+  }
+
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/Control.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/Control.scala
new file mode 100644
index 0000000..3cef65a
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/Control.scala
@@ -0,0 +1,59 @@
+package core
+
+import chisel3._
+
+class Control extends Module {
+    val io = IO(new Bundle {
+        val in_opcode = Input(UInt(7.W))
+        val func7     = Input(UInt(7.W))
+        val func3     = Input(UInt(3.W))
+      //  val enable_M_extension = Input(UInt(1.W))
+        val out_memWrite = Output(UInt(1.W))
+        val out_branch = Output(UInt(1.W))
+        val out_memRead = Output(UInt(1.W))
+        val out_regWrite = Output(UInt(1.W))
+        val csr_we_o = Output(Bool())
+        val csr_imm_type = Output(Bool())
+        val csr_op_o = Output(UInt(2.W))
+        val out_memToReg = Output(UInt(1.W))
+        val out_aluOp = Output(UInt(4.W))
+        val out_operand_a_sel = Output(UInt(2.W))
+        val out_operand_b_sel = Output(UInt(1.W))
+        val out_extend_sel = Output(UInt(2.W))
+        val out_next_pc_sel = Output(UInt(2.W))
+      //  val M_extension_enabled = Output(UInt(1.W))
+    })
+    val instruction_type_decode = Module(new InstructionTypeDecode())
+    val control_decode = Module(new ControlDecode())
+    instruction_type_decode.io.opcode := io.in_opcode
+    instruction_type_decode.io.func3  := io.func3
+    control_decode.io.in_r_type := instruction_type_decode.io.r_type
+    control_decode.io.in_load_type := instruction_type_decode.io.load_type
+    control_decode.io.in_s_type := instruction_type_decode.io.s_type
+    control_decode.io.in_sb_type := instruction_type_decode.io.sb_type
+    control_decode.io.in_i_type := instruction_type_decode.io.i_type
+    control_decode.io.in_jalr_type := instruction_type_decode.io.jalr_type
+    control_decode.io.in_jal_type := instruction_type_decode.io.jal_type
+    control_decode.io.in_lui_type := instruction_type_decode.io.lui_type
+    control_decode.io.Auipc       := instruction_type_decode.io.Auipc
+    control_decode.io.multiply    := instruction_type_decode.io.multiply
+    control_decode.io.in_csr_type := instruction_type_decode.io.csr_type
+    control_decode.io.in_csr_imm_type := instruction_type_decode.io.csr_imm_type
+    
+    io.out_memWrite := control_decode.io.memWrite
+    io.out_branch := control_decode.io.branch
+    io.out_memRead := control_decode.io.memRead
+    io.out_regWrite := control_decode.io.regWrite
+    io.csr_we_o := control_decode.io.csr_wen
+    io.out_memToReg := control_decode.io.memToReg
+    io.out_aluOp := control_decode.io.aluOperation
+    io.out_operand_a_sel := control_decode.io.operand_a_sel
+    io.out_operand_b_sel := control_decode.io.operand_b_sel
+    io.out_extend_sel := control_decode.io.extend_sel
+    io.out_next_pc_sel := control_decode.io.next_pc_sel
+//    instruction_type_decode.io.enable_M_extension := io.enable_M_extension 
+ //   io.M_extension_enabled := control_decode.io.M_extension_enabled
+    io.csr_op_o := instruction_type_decode.io.csr_op
+    io.csr_imm_type := instruction_type_decode.io.csr_imm_type
+    instruction_type_decode.io.func7 := io.func7
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/ControlDecode.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/ControlDecode.scala
new file mode 100644
index 0000000..e5572de
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/ControlDecode.scala
@@ -0,0 +1,201 @@
+package core
+
+import chisel3._
+
+class ControlDecode extends Module {
+    val io = IO(new Bundle {
+        // Inputs
+        val in_r_type = Input(UInt(1.W))
+        val in_load_type = Input(UInt(1.W))
+        val in_s_type = Input(UInt(1.W))
+        val in_sb_type = Input(UInt(1.W))
+        val in_i_type = Input(UInt(1.W))
+        val in_jalr_type = Input(UInt(1.W))
+        val in_jal_type = Input(UInt(1.W))
+        val in_lui_type = Input(UInt(1.W))
+        val in_csr_type = Input(UInt(1.W))
+        val in_csr_imm_type = Input(UInt(1.W))
+        val Auipc       = Input(UInt(1.W))
+        val multiply    = Input(UInt(1.W))
+        // Outputs
+        val memWrite = Output(UInt(1.W))
+        val memRead  = Output(UInt(1.W))
+        val branch = Output(UInt(1.W))
+        val regWrite = Output(UInt(1.W))
+        val csr_wen = Output(Bool())
+        val memToReg = Output(UInt(1.W))
+        val aluOperation = Output(UInt(4.W))
+        val operand_a_sel = Output(UInt(2.W))
+        val operand_b_sel = Output(UInt(1.W))
+        val extend_sel = Output(UInt(2.W))
+        val next_pc_sel = Output(UInt(2.W))
+      //  val M_extension_enabled = Output(UInt(1.W))
+    })
+        default_signals()
+
+    // R-Type instruction    
+    when(io.in_r_type === 1.U) {
+        io.memWrite := 0.U
+        io.memRead  := 0.U
+        io.branch := 0.U
+        io.regWrite := 1.U
+        io.memToReg := 0.U
+        io.aluOperation := "b0000".U
+        io.operand_a_sel := "b00".U
+        io.operand_b_sel := 0.U
+        io.extend_sel := "b00".U
+        io.next_pc_sel := "b00".U
+      //  io.M_extension_enabled := 0.U
+    } 
+    .elsewhen(io.in_load_type === 1.U) {
+        // Load type instruction
+        io.memWrite := 0.U
+        io.memRead  := 1.U
+        io.branch := 0.U
+        io.regWrite := 1.U
+        io.memToReg := 1.U
+        io.aluOperation := "b0100".U
+        io.operand_a_sel := "b00".U
+        io.operand_b_sel := 1.U
+        io.extend_sel := "b00".U
+        io.next_pc_sel := "b00".U
+    } .elsewhen(io.in_s_type === 1.U) {
+        // S-Type instruction
+        io.memWrite := 1.U
+        io.memRead  := 0.U
+        io.branch := 0.U
+        io.regWrite := 0.U
+        io.memToReg := 0.U
+        io.aluOperation := "b0101".U
+        io.operand_a_sel := "b00".U
+        io.operand_b_sel := 1.U
+        io.extend_sel := "b01".U
+        io.next_pc_sel := "b00".U
+    } .elsewhen(io.in_sb_type === 1.U) {
+        io.memWrite := 0.U
+        io.memRead  := 0.U
+        io.branch := 1.U
+        io.regWrite := 0.U
+        io.memToReg := 0.U
+        io.aluOperation := "b0010".U
+        io.operand_a_sel := "b00".U
+        io.operand_b_sel := 0.U
+        io.extend_sel := "b00".U
+        io.next_pc_sel := "b01".U
+    } .elsewhen(io.in_i_type === 1.U) {
+        io.memWrite := 0.U
+        io.memRead  := 0.U
+        io.branch := 0.U
+        io.regWrite := 1.U
+        io.memToReg := 0.U
+        io.aluOperation := "b0001".U
+        io.operand_a_sel := "b00".U
+        io.operand_b_sel := 1.U
+        io.extend_sel := "b00".U
+        io.next_pc_sel := "b00".U
+    } .elsewhen(io.in_jalr_type === 1.U) {
+        io.memWrite := 0.U
+        io.memRead  := 0.U
+        io.branch := 0.U
+        io.regWrite := 1.U
+        io.memToReg := 0.U
+        io.aluOperation := "b0011".U
+        io.operand_a_sel := "b10".U
+        io.operand_b_sel := 0.U
+        io.extend_sel := "b00".U
+        io.next_pc_sel := "b11".U
+    } .elsewhen(io.in_jal_type === 1.U) {
+        io.memWrite := 0.U
+        io.memRead  := 0.U
+        io.branch := 0.U
+        io.regWrite := 1.U
+        io.memToReg := 0.U
+        io.aluOperation := "b0011".U
+        io.operand_a_sel := "b10".U
+        io.operand_b_sel := 0.U
+        io.extend_sel := "b00".U
+        io.next_pc_sel := "b10".U
+    } 
+    .elsewhen(io.in_lui_type === 1.U) 
+    {
+        io.memWrite := 0.U
+        io.memRead  := 0.U
+        io.branch := 0.U
+        io.regWrite := 1.U
+        io.memToReg := 0.U
+        io.aluOperation := "b0110".U
+        io.operand_a_sel := "b11".U
+        io.operand_b_sel := 1.U
+        io.extend_sel := "b10".U
+        io.next_pc_sel := "b00".U
+    } 
+    .elsewhen(io.Auipc === 1.U) 
+    {
+        io.memWrite := 0.U
+        io.memRead  := 0.U
+        io.branch := 0.U
+        io.regWrite := 1.U
+        io.memToReg := 0.U
+        io.aluOperation := "b0111".U
+        io.operand_a_sel := "b01".U
+        io.operand_b_sel := 1.U
+        io.extend_sel := "b10".U
+        io.next_pc_sel := "b00".U
+    } 
+    .elsewhen(io.multiply === 1.U) {
+        io.memWrite := 0.U
+        io.memRead  := 0.U
+        io.branch := 0.U
+        io.regWrite := 1.U
+        io.memToReg := 0.U
+        io.aluOperation := "b1001".U
+        io.operand_a_sel := "b00".U
+        io.operand_b_sel := 0.U
+        io.extend_sel := "b00".U
+        io.next_pc_sel := "b00".U
+     //   io.M_extension_enabled := 1.U
+    } .elsewhen(io.in_csr_type === 1.U) {
+        io.memWrite := 0.U
+        io.memRead := 0.U
+        io.branch := 0.U
+        io.regWrite := 1.U
+        io.csr_wen := true.B
+        io.memToReg := 0.U
+        io.aluOperation := "b1000".U
+        io.operand_a_sel := "b00".U
+        io.operand_b_sel := 1.U
+        io.extend_sel := "b00".U
+        io.next_pc_sel := "b00".U
+    } .elsewhen(io.in_csr_imm_type === 1.U) {
+        io.memWrite := 0.U
+        io.memRead := 0.U
+        io.branch := 0.U
+        io.regWrite := 1.U
+        io.csr_wen := true.B
+        io.memToReg := 0.U
+        io.aluOperation := "b1000".U
+        io.operand_a_sel := "b00".U
+        io.operand_b_sel := 1.U
+        io.extend_sel := "b00".U
+        io.next_pc_sel := "b00".U
+    }
+    .otherwise {
+        default_signals()
+    }
+
+    def default_signals(): Unit =
+    {
+        io.memWrite := 0.U
+        io.memRead  := 0.U
+        io.branch := 0.U
+        io.regWrite := 0.U
+        io.memToReg := 0.U
+        io.aluOperation := 28.U
+        io.operand_a_sel := "b00".U
+        io.operand_b_sel := 0.U
+        io.extend_sel := "b00".U
+        io.next_pc_sel := "b00".U
+        io.csr_wen := false.B
+     //   io.M_extension_enabled := 0.U
+    }
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/Core.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/Core.scala
new file mode 100644
index 0000000..114f866
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/Core.scala
@@ -0,0 +1,329 @@
+package core
+
+import chisel3._
+import chisel3.util.Cat
+import main.scala.core.csrs.CsrRegisterFile
+
+class Core extends Module {
+  val io = IO(new Bundle {
+    // Data Memory Interface
+    val data_gnt_i      =      Input(Bool())
+    val data_rvalid_i   =      Input(Bool())
+    val data_rdata_i    =      Input(SInt(32.W))
+    val data_req_o      =      Output(Bool())
+    val data_we_o       =      Output(Bool())
+    val data_be_o       =      Output(Vec(4, Bool()))
+    val data_addr_o     =      Output(SInt(32.W))
+    val data_wdata_o    =      Output(Vec(4, SInt(8.W)))
+
+    // instruction memory interface
+    val instr_gnt_i     =      Input(Bool())
+    val instr_rvalid_i  =      Input(Bool())
+    val instr_rdata_i   =      Input(UInt(32.W))
+    val instr_req_o     =      Output(Bool())
+    val instr_addr_o    =      Output(UInt(32.W))
+
+    // stall signal coming from SoC to stall until the UART writes into ICCM
+    val stall_core_i    =      Input(Bool())
+
+    // external interrupt signal coming from the GPIO (in future from PLIC)
+    val irq_external_i  =      Input(Bool())
+    val reg_7           =      Output(SInt(32.W))
+    val reg_out         =      Output(SInt(32.W))
+  })
+
+  //        ██████╗░██╗░░░██╗██████╗░░█████╗░░██████╗░      ███╗░░░███╗██╗███╗░░██╗██╗
+  //        ██╔══██╗██║░░░██║██╔══██╗██╔══██╗██╔═══██╗      ████╗░████║██║████╗░██║██║
+  //        ██████╦╝██║░░░██║██████╔╝███████║██║██╗██║      ██╔████╔██║██║██╔██╗██║██║
+  //        ██╔══██╗██║░░░██║██╔══██╗██╔══██║╚██████╔╝      ██║╚██╔╝██║██║██║╚████║██║
+  //        ██████╦╝╚██████╔╝██║░░██║██║░░██║░╚═██╔═╝░      ██║░╚═╝░██║██║██║░╚███║██║
+  //        ╚═════╝░░╚═════╝░╚═╝░░╚═╝╚═╝░░╚═╝░░░╚═╝░░░      ╚═╝░░░░░╚═╝╚═╝╚═╝░░╚══╝╚═╝
+
+
+  //                      ____________________s???s???s???s
+  //                      ___________________s$$$$$$s..s..?..?..?
+  //                      __________________$$$$$$$$$$$$s..s.?..?
+  //                      ____________________$$$$$$$$$$$$$$s…?
+  //                      ______________ s$$$$$$(O)$$$$$$$$$$$$.?
+  //                      ____________ €$$$$$$$$$$$$$$$$$$$$s..?..s
+  //                      _____________s$$$$$$$$$$$$$$$$$$$$$$s..?
+  //                      _____________________s$$$$$$$$$$$$$$..s..?
+  //                      ______________________$$$$$$$$$$$$s..s..?
+  //                      ______________________$$$$$$$$$$$$.s.?.s.?
+  //                      _____________________$$$$$$$$$$$$$s..s….?
+  //                      ____________________$$$$$$$$$$$$$$s_??s.?
+  //                      ___________________$$$$$$$$$$$$$$$s.s….?
+  //                      _____s$$$$________$$$$$$$$$$$$$$$$$..s?
+  //                      ____$$$$$$$$_____$$$$$$$$$$$$$$$$$$s…s
+  //                      ____$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$_s_?__s$s
+  //                      ____$$__$$$$$$$$$$$$$$$$$$$$$$$$$$_____s$$$
+  //                      ____$$____$$$$$$$$$$$$$$$$$$$$$$s_____s$$$$s
+  //                      ___$$$$$$$$$$$$$$$$$$$$$$$$$$_$$_____s$$$$$$
+  //                      __$$$$$$$$$$$$$$$$$$$$$$$$$$$$_$____s$$$$$$$
+  //                      __$$$$__$$$$$$$$$$$$$$$$$$$$$$$____s$$$$$$$$
+  //                      ___$$$________$$$$$$$$$$$$$$$$$$___s$$$$$$$
+  //                      ____$$$s______$$$$$$$$$$$$$$$$$$$__s$$$$$$
+  //                      _____$$$_______$$$$$$$$$$$$$$$$$$$_s$$
+
+  // val IF_ID = Module(new IF_ID())
+  val ID_EX            =      Module(new           ID_EX())
+  val EX_MEM           =      Module(new          EX_MEM())
+  val MEM_WB           =      Module(new          MEM_WB())
+  val fetch            =      Module(new           Fetch())
+  val decode           =      Module(new          Decode())
+  val execute          =      Module(new         Execute())
+  val memory_stage     =      Module(new     MemoryStage())
+  val writeback        =      Module(new       WriteBack())
+//  val csrRegFile       =      Module(new CsrRegisterFile())
+
+  // stalling the core either for loads/stores or after initial boot up to wait until UART writes program into ICCM.
+  val stall            =      memory_stage.io.stall || io.stall_core_i
+
+  // *********** ----------- CSR REGISTER FILE ----------- ********* //
+//  csrRegFile.io.i_hart_id                       :=      0.U
+//  csrRegFile.io.i_boot_addr                     :=      0.U
+//  csrRegFile.io.i_csr_mtvec_init                :=      fetch.io.csrRegFile_csr_mtvec_init_o
+//  csrRegFile.io.i_csr_access                    :=      MEM_WB.io.ctrl_CsrWen_out
+//  csrRegFile.io.i_csr_wdata                     :=      writeback.io.write_data.asUInt()  // data from rs1
+//  csrRegFile.io.i_csr_op                        :=      MEM_WB.io.csr_op_out
+//  csrRegFile.io.i_csr_op_en                     :=      MEM_WB.io.ctrl_CsrWen_out   // right now the operation enables when csr instruction is in writeback stage
+//  csrRegFile.io.i_csr_addr                      :=      MEM_WB.io.csr_addr_out(11,0).asUInt()
+//  csrRegFile.io.i_irq_software                  :=      false.B
+//  csrRegFile.io.i_irq_timer                     :=      false.B
+//  csrRegFile.io.i_irq_external                  :=      io.irq_external_i
+//  csrRegFile.io.i_nmi_mode                      :=      false.B
+//  csrRegFile.io.i_pc_if                         :=      fetch.io.csrRegFile_csr_if_pc_o
+//  csrRegFile.io.i_pc_id                         :=      0.U
+//  csrRegFile.io.i_pc_wb                         :=      0.U
+//  csrRegFile.io.i_csr_save_if                   :=      fetch.io.csrRegFile_csr_save_if_o
+//  csrRegFile.io.i_csr_save_id                   :=      false.B
+//  csrRegFile.io.i_csr_save_wb                   :=      false.B
+//  csrRegFile.io.i_csr_restore_mret              :=      decode.io.mret_inst_o
+//  csrRegFile.io.i_csr_restore_dret              :=      false.B
+//  csrRegFile.io.i_csr_mcause                    :=      fetch.io.csrRegFile_exc_cause_o
+//  csrRegFile.io.i_csr_save_cause                :=      fetch.io.csrRegFile_csr_save_cause_o
+//  csrRegFile.io.i_csr_mtval                     :=      0.U
+//  csrRegFile.io.i_instr_ret                     :=      false.B
+//  csrRegFile.io.i_iside_wait                    :=      false.B
+//  csrRegFile.io.i_jump                          :=      false.B
+//  csrRegFile.io.i_branch                        :=      false.B
+//  csrRegFile.io.i_branch_taken                  :=      false.B
+//  csrRegFile.io.i_mem_load                      :=      false.B
+//  csrRegFile.io.i_mem_store                     :=      false.B
+//  csrRegFile.io.i_dside_wait                    :=      false.B
+//  csrRegFile.io.i_debug_mode                    :=      false.B
+//  csrRegFile.io.i_debug_cause                   :=      0.U
+//  csrRegFile.io.i_debug_csr_save                :=      false.B
+  // *********** ----------- INSTRUCTION FETCH (IF) STAGE ----------- ********* //
+  fetch.io.core_init_mtvec_i                    :=      !io.stall_core_i
+  fetch.io.core_stall_i                         :=      stall
+  // instruction memory bus connections(inputs)
+  fetch.io.core_instr_gnt_i                     :=      io.instr_gnt_i
+  fetch.io.core_instr_rvalid_i                  :=      io.instr_rvalid_i
+  fetch.io.core_instr_rdata_i                   :=      io.instr_rdata_i
+
+  // csr connections
+  fetch.io.csrRegFile_irq_pending_i             :=      decode.io.fetch_irq_pending_o
+  fetch.io.csrRegFile_csr_mstatus_mie_i         :=      decode.io.fetch_csr_mstatus_mie_o
+  fetch.io.csrRegFile_csr_mtvec_i               :=      decode.io.fetch_csr_mtvec_o
+  fetch.io.csrRegFile_csr_mepc_i                :=      decode.io.fetch_csr_mepc_o
+  fetch.io.decode_mret_inst_i                   :=      decode.io.fetch_mret_inst_o
+
+  fetch.io.decode_sb_imm_i                      :=      decode.io.sb_imm
+  fetch.io.decode_uj_imm_i                      :=      decode.io.uj_imm
+  fetch.io.decode_jalr_imm_i                    :=      decode.io.jalr_output
+  fetch.io.decode_ctrl_next_pc_sel_i            :=      decode.io.ctrl_next_pc_sel_out
+  fetch.io.decode_ctrl_out_branch_i             :=      decode.io.ctrl_Branch_out
+  fetch.io.decode_branchLogic_output_i          :=      decode.io.branchLogic_output
+  fetch.io.decode_hazardDetection_pc_i          :=      decode.io.hazardDetection_pc_out
+  fetch.io.decode_hazardDetection_inst_i        :=      decode.io.hazardDetection_inst_out
+  fetch.io.decode_hazardDetection_current_pc_i  :=      decode.io.hazardDetection_current_pc_out
+  fetch.io.decode_hazardDetection_pc_forward_i  :=      decode.io.hazardDetection_pc_forward
+  fetch.io.decode_hazardDetection_inst_forward_i:=      decode.io.hazardDetection_inst_forward
+
+
+  //instruction memory bus connections(outputs)
+  io.instr_req_o                                :=      fetch.io.core_instr_req_o
+  io.instr_addr_o                               :=      fetch.io.core_instr_addr_o
+  // *********** ----------- INSTRUCTION DECODE (ID) STAGE ----------- ********* //
+
+  decode.io.IF_ID_inst                          :=      fetch.io.decode_if_id_inst_o
+  decode.io.IF_ID_pc                            :=      fetch.io.decode_if_id_pc_o
+  decode.io.IF_ID_pc4                           :=      fetch.io.decode_if_id_pc4_o
+  decode.io.MEM_WB_ctrl_regWr                   :=      MEM_WB.io.ctrl_RegWr_out
+  decode.io.MEM_WB_ctrl_csrWen                  :=      MEM_WB.io.ctrl_CsrWen_out
+  decode.io.ID_EX_ctrl_csrWen                   :=      ID_EX.io.ctrl_CsrWen_out
+  decode.io.EX_MEM_ctrl_csrWen                  :=      EX_MEM.io.ctrl_CsrWen_out
+//  decode.io.MEM_WB_csrAddr                      :=      MEM_WB.io.csr_addr_out(11,0).asUInt()
+//  decode.io.ID_EX_ctrl_csrAddr                  :=      ID_EX.io.imm_out(11,0).asUInt()
+//  decode.io.EX_MEM_ctrl_csrAddr                 :=      EX_MEM.io.csr_addr_out(11,0).asUInt()
+  //decode.io.ID_EX_rs1_data                      :=      ID_EX.io.rs1_out
+  decode.io.MEM_WB_rd_sel                       :=      MEM_WB.io.rd_sel_out
+  decode.io.ID_EX_ctrl_MemRd                    :=      ID_EX.io.ctrl_MemRd_out
+  decode.io.ID_EX_rd_sel                        :=      ID_EX.io.rd_sel_out
+  decode.io.EX_MEM_rd_sel                       :=      EX_MEM.io.rd_sel_out
+  decode.io.EX_MEM_ctrl_MemRd                   :=      EX_MEM.io.ctrl_MemRd_out
+  decode.io.MEM_WB_ctrl_MemRd                   :=      MEM_WB.io.ctrl_MemRd_out
+  decode.io.writeback_write_data                :=      writeback.io.write_data   // rs1 data
+  decode.io.MEM_WB_csr_rdata_i                    :=      MEM_WB.io.csr_data_out    // csr data
+  decode.io.EX_MEM_csr_rdata_i                  :=      EX_MEM.io.csr_data_o
+  decode.io.ID_EX_csr_rdata_i                   :=      ID_EX.io.csr_data_o
+  decode.io.alu_output                          :=      execute.io.alu_output
+  decode.io.EX_MEM_alu_output                   :=      EX_MEM.io.alu_output
+  decode.io.MEM_WB_alu_output                   :=      MEM_WB.io.alu_output
+  decode.io.dmem_memOut                         :=      io.data_rdata_i
+  decode.io.dccm_rvalid_i                       :=      io.data_rvalid_i
+  decode.io.fetch_csr_save_cause_i              :=      fetch.io.csrRegFile_csr_save_cause_o
+  decode.io.fetch_exc_cause_i                   :=      fetch.io.csrRegFile_exc_cause_o
+  decode.io.fetch_csr_save_if                   :=      fetch.io.csrRegFile_csr_save_if_o
+  decode.io.fetch_csr_if_pc                     :=      fetch.io.csrRegFile_csr_if_pc_o
+  decode.io.fetch_csr_mtvec_init                :=      fetch.io.csrRegFile_csr_mtvec_init_o
+//  decode.io.MEM_WB_csr_op                       :=      MEM_WB.io.csr_op_out
+  decode.io.irq_external_i                      :=      io.irq_external_i
+  decode.io.ID_EX_ctrl_regWr                    :=      ID_EX.io.ctrl_RegWr_out
+  decode.io.EX_MEM_ctrl_regWr                   :=      EX_MEM.io.ctrl_RegWr_out
+
+  ID_EX.io.stall                                :=      stall
+  ID_EX.io.ctrl_MemWr_in                        :=      decode.io.ctrl_MemWr_out
+  ID_EX.io.ctrl_MemRd_in                        :=      decode.io.ctrl_MemRd_out
+  ID_EX.io.ctrl_Branch_in                       :=      decode.io.ctrl_Branch_out
+  ID_EX.io.ctrl_RegWr_in                        :=      decode.io.ctrl_RegWr_out
+  ID_EX.io.ctrl_CsrWen_in                       :=      decode.io.ctrl_CsrWen_out
+  ID_EX.io.ctrl_MemToReg_in                     :=      decode.io.ctrl_MemToReg_out
+  ID_EX.io.ctrl_AluOp_in                        :=      decode.io.ctrl_AluOp_out
+  ID_EX.io.ctrl_OpA_sel_in                      :=      decode.io.ctrl_OpA_sel_out
+  ID_EX.io.ctrl_OpB_sel_in                      :=      decode.io.ctrl_OpB_sel_out
+  ID_EX.io.ctrl_nextPc_sel_in                   :=      decode.io.ctrl_next_pc_sel_out
+
+  ID_EX.io.rs1_in                               :=      decode.io.rs1_out
+  ID_EX.io.rs2_in                               :=      decode.io.rs2_out
+  ID_EX.io.imm                                  :=      decode.io.imm_out
+//  ID_EX.io.csr_op_in                            :=      decode.io.csr_op_o
+  ID_EX.io.csr_data_i                           :=      decode.io.csr_rdata_o
+
+  ID_EX.io.pc_in                                :=      decode.io.pc_out
+  ID_EX.io.pc4_in                               :=      decode.io.pc4_out
+  ID_EX.io.func3_in                             :=      decode.io.func3_out
+  ID_EX.io.func7_in                             :=      decode.io.func7_out
+  ID_EX.io.inst_op_in                           :=      decode.io.inst_op_out
+  ID_EX.io.rd_sel_in                            :=      decode.io.rd_sel_out
+  ID_EX.io.rs1_sel_in                           :=      decode.io.rs1_sel_out
+  ID_EX.io.rs2_sel_in                           :=      decode.io.rs2_sel_out
+
+  decode.io.execute_regwrite                    :=      ID_EX.io.ctrl_RegWr_out
+  decode.io.mem_regwrite                        :=      EX_MEM.io.ctrl_RegWr_out
+  decode.io.wb_regwrite                         :=      MEM_WB.io.ctrl_RegWr_out
+
+
+  // *********** ----------- EXECUTION (EX) STAGE ----------- ********* //
+  execute.io.ID_EX_pc_out                       :=      ID_EX.io.pc_out
+  execute.io.EX_MEM_rd_sel                      :=      EX_MEM.io.rd_sel_out
+  execute.io.MEM_WB_rd_sel                      :=      MEM_WB.io.rd_sel_out
+  execute.io.ID_EX_rs1_sel                      :=      ID_EX.io.rs1_sel_out
+  execute.io.ID_EX_rs2_sel                      :=      ID_EX.io.rs2_sel_out
+  execute.io.EX_MEM_ctrl_RegWr                  :=      EX_MEM.io.ctrl_RegWr_out
+  execute.io.EX_MEM_ctrl_csrWen                 :=      EX_MEM.io.ctrl_CsrWen_out
+  execute.io.MEM_WB_ctrl_csrWen                 :=      MEM_WB.io.ctrl_CsrWen_out
+  execute.io.MEM_WB_ctrl_RegWr                  :=      MEM_WB.io.ctrl_RegWr_out
+  execute.io.ID_EX_ctrl_OpA_sel                 :=      ID_EX.io.ctrl_OpA_sel_out
+  execute.io.ID_EX_ctrl_OpB_sel                 :=      ID_EX.io.ctrl_OpB_sel_out
+  execute.io.ID_EX_pc4                          :=      ID_EX.io.pc4_out
+  execute.io.ID_EX_rs1                          :=      ID_EX.io.rs1_out
+  execute.io.ID_EX_rs2                          :=      ID_EX.io.rs2_out
+  execute.io.EX_MEM_alu_output                  :=      EX_MEM.io.alu_output
+  execute.io.EX_MEM_csr_rdata                   :=      EX_MEM.io.csr_data_o
+  execute.io.MEM_WB_csr_rdata                   :=      MEM_WB.io.csr_data_out
+  execute.io.writeback_write_data               :=      writeback.io.write_data
+  execute.io.ID_EX_imm                          :=      ID_EX.io.imm_out
+  execute.io.ID_EX_ctrl_AluOp                   :=      ID_EX.io.ctrl_AluOp_out
+  execute.io.ID_EX_func7                        :=      ID_EX.io.func7_out
+  execute.io.ID_EX_inst_op                      :=      ID_EX.io.inst_op_out
+  execute.io.ID_EX_func3                        :=      ID_EX.io.func3_out
+  execute.io.ID_EX_rd_sel                       :=      ID_EX.io.rd_sel_out
+  execute.io.ID_EX_ctrl_MemWr                   :=      ID_EX.io.ctrl_MemWr_out
+  execute.io.ID_EX_ctrl_MemRd                   :=      ID_EX.io.ctrl_MemRd_out
+  execute.io.ID_EX_ctrl_RegWr                   :=      ID_EX.io.ctrl_RegWr_out
+  execute.io.ID_EX_ctrl_CsrWen                  :=      ID_EX.io.ctrl_CsrWen_out
+  execute.io.ID_EX_ctrl_MemToReg                :=      ID_EX.io.ctrl_MemToReg_out
+//  execute.io.ID_EX_csr_op                       :=      ID_EX.io.csr_op_o
+  execute.io.ID_EX_csr_data                     :=      ID_EX.io.csr_data_o
+
+  EX_MEM.io.stall                               :=      stall
+  // Passing the ALU output to the EX/MEM pipeline register
+  EX_MEM.io.alu_in                              :=      execute.io.alu_output
+
+  // Passing the rd_sel value in the EX/MEM pipeline register
+  EX_MEM.io.rd_sel_in                           :=      execute.io.rd_sel_out
+  EX_MEM.io.rs2_sel_in                          :=      execute.io.rs2_sel_out
+  EX_MEM.io.rs2_in                              :=      execute.io.rs2_out
+  EX_MEM.io.EX_MEM_func3                        :=      execute.io.func3_out
+  EX_MEM.io.ctrl_CsrWen_in                      :=      execute.io.ctrl_CsrWe_out
+//  EX_MEM.io.csr_addr_in                         :=      execute.io.csr_addr_out
+//  EX_MEM.io.csr_op_in                           :=      execute.io.csr_op_o
+  EX_MEM.io.csr_data_i                          :=      execute.io.csr_data_o
+
+
+  // Passing the control signals to EX/MEM pipeline register and (memRead / memWrite control registers for stall detection unit)
+  EX_MEM.io.ctrl_MemWr_in                       :=      execute.io.ctrl_MemWr_out
+  EX_MEM.io.ctrl_MemRd_in                       :=      execute.io.ctrl_MemRd_out
+  EX_MEM.io.ctrl_RegWr_in                       :=      execute.io.ctrl_RegWr_out
+  EX_MEM.io.ctrl_MemToReg_in                    :=      execute.io.ctrl_MemToReg_out
+
+
+
+  // *********** ----------- MEMORY (MEM) STAGE ----------- ********* //
+
+  memory_stage.io.EX_MEM_alu_output             :=      EX_MEM.io.alu_output
+  memory_stage.io.EX_MEM_rd_sel                 :=      EX_MEM.io.rd_sel_out
+  memory_stage.io.EX_MEM_RegWr                  :=      EX_MEM.io.ctrl_RegWr_out
+  memory_stage.io.EX_MEM_CsrWe                  :=      EX_MEM.io.ctrl_CsrWen_out
+  memory_stage.io.EX_MEM_MemRd                  :=      EX_MEM.io.ctrl_MemRd_out
+  memory_stage.io.EX_MEM_MemToReg               :=      EX_MEM.io.ctrl_MemToReg_out
+  memory_stage.io.EX_MEM_MemWr                  :=      EX_MEM.io.ctrl_MemWr_out
+  memory_stage.io.EX_MEM_rs2                    :=      EX_MEM.io.rs2_out
+  memory_stage.io.func3                         :=      EX_MEM.io.EX_MEM_func3_out
+//  memory_stage.io.EX_MEM_csr_addr               :=      EX_MEM.io.csr_addr_out
+//  memory_stage.io.EX_MEM_csr_op                 :=      EX_MEM.io.csr_op_out
+  memory_stage.io.EX_MEM_csr_data               :=      EX_MEM.io.csr_data_o
+
+  memory_stage.io.data_gnt_i                    :=      io.data_gnt_i
+  memory_stage.io.data_rvalid_i                 :=      io.data_rvalid_i
+  memory_stage.io.data_rdata_i                  :=      io.data_rdata_i
+  io.data_req_o                                 :=      memory_stage.io.data_req_o
+  io.data_be_o                                  :=      memory_stage.io.data_be_o
+  io.data_we_o                                  :=      memory_stage.io.ctrl_MemWr_out
+  io.data_wdata_o                               :=      memory_stage.io.data_wdata_o
+  io.data_addr_o                                :=      memory_stage.io.memAddress
+
+
+  MEM_WB.io.stall                               :=      stall
+  MEM_WB.io.alu_in                              :=      memory_stage.io.alu_output
+  // not passing data memory data into MEM/WB register since it's output itself is registered
+  MEM_WB.io.dmem_data_in                        :=      memory_stage.io.data_out
+  MEM_WB.io.rd_sel_in                           :=      memory_stage.io.rd_sel_out
+
+  MEM_WB.io.ctrl_RegWr_in                       :=      memory_stage.io.ctrl_RegWr_out
+  MEM_WB.io.ctrl_CsrWen_in                      :=      memory_stage.io.ctrl_CsrWen_out
+  MEM_WB.io.ctrl_MemRd_in                       :=      memory_stage.io.ctrl_MemRd_out
+  MEM_WB.io.ctrl_MemToReg_in                    :=      memory_stage.io.ctrl_MemToReg_out
+//  MEM_WB.io.csr_addr_in                         :=      memory_stage.io.csr_addr_out
+//  MEM_WB.io.csr_op_in                           :=      memory_stage.io.csr_op_out
+  MEM_WB.io.csr_data_in                         :=      memory_stage.io.csr_data_out
+
+  // *********** ----------- WRITE BACK (WB) STAGE ----------- ********* //
+
+
+  writeback.io.MEM_WB_MemToReg                  :=      MEM_WB.io.ctrl_MemToReg_out
+  // directly passing the data memory result to the write back stage
+  // since it's output is already registered so we pass it directly.
+  //    writeback.io.MEM_WB_dataMem_data := memory_stage.io.data_out
+  writeback.io.MEM_WB_dataMem_data              :=      MEM_WB.io.dmem_data_out
+  writeback.io.MEM_WB_alu_output                :=      MEM_WB.io.alu_output
+
+
+  // Just for testing
+  io.reg_out                                    :=      writeback.io.write_data
+
+  io.reg_7                                      :=      decode.io.reg_7_out
+
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/CsrControlUnit.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/CsrControlUnit.scala
new file mode 100644
index 0000000..9bd1e67
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/CsrControlUnit.scala
@@ -0,0 +1,94 @@
+package main.scala.core
+import chisel3._
+
+class CsrControlUnit extends Module {
+  val io = IO(new Bundle {
+    val reg_wr_in_execute = Input(Bool())
+    val rd_sel_in_execute = Input(UInt(5.W))
+    val csr_wr_in_execute = Input(Bool())
+
+    val reg_wr_in_memory = Input(Bool())
+    val rd_sel_in_memory = Input(UInt(5.W))
+    val csr_wr_in_memory = Input(Bool())
+
+    val reg_wr_in_writeback = Input(Bool())
+    val rd_sel_in_writeback = Input(UInt(5.W))
+    val csr_wr_in_writeback = Input(Bool())
+
+    val rs1_sel_in_decode = Input(UInt(5.W))
+    val csr_inst_in_decode = Input(Bool())
+
+    // this indicates that the csr instruction in decode is of imm type and we do not need to forward
+    // the data since rs1 does not exist in this case.
+    val csr_imm_inst_in_decode = Input(Bool())
+
+    // this indicates load inst is present in execution stage. Since the CSR hazard unit would detect decode/execute
+    // dependency and forward alu output, this would be incorrect in case of a load instruction since the data
+    // wont be ready yet and alu output is used for the address calculation
+    val load_inst_in_execute = Input(Bool())
+
+    val load_inst_in_memory = Input(Bool())
+
+    // valid signal to indicate whether the data coming from load instruction is valid or not.
+    // if it is valid, only then forward data
+    // this is only important when load instruction is encountered
+    val dccm_rvalid_i = Input(Bool())
+    val forward_rs1 = Output(UInt(3.W))
+    val csr_op_en_o = Output(Bool())
+  })
+
+  io.forward_rs1 := 0.U
+  io.csr_op_en_o := false.B
+
+  val hazard_in_decode_execute = Wire(Bool())
+  val hazard_in_decode_memory = Wire(Bool())
+  val hazard_in_decode_writeback = Wire(Bool())
+
+  val csr_hazard_in_decode_execute = Wire(Bool())
+  val csr_hazard_in_decode_memory = Wire(Bool())
+  val csr_hazard_in_decode_writeback = Wire(Bool())
+
+  hazard_in_decode_execute   := Mux(io.reg_wr_in_execute && io.csr_inst_in_decode && ~io.csr_imm_inst_in_decode && io.rd_sel_in_execute =/= 0.U && ~io.csr_wr_in_execute && (io.rd_sel_in_execute === io.rs1_sel_in_decode), true.B, false.B)
+  hazard_in_decode_memory    := Mux(io.reg_wr_in_memory && io.csr_inst_in_decode && ~io.csr_imm_inst_in_decode && io.rd_sel_in_memory =/= 0.U  && ~hazard_in_decode_execute && ~io.csr_wr_in_memory && (io.rd_sel_in_memory === io.rs1_sel_in_decode), true.B, false.B)
+  hazard_in_decode_writeback := Mux(io.reg_wr_in_writeback && io.csr_inst_in_decode && ~io.csr_imm_inst_in_decode && io.rd_sel_in_writeback =/= 0.U && ~hazard_in_decode_execute && ~hazard_in_decode_memory && ~io.csr_wr_in_writeback&& (io.rd_sel_in_writeback === io.rs1_sel_in_decode), true.B, false.B)
+
+  csr_hazard_in_decode_execute := Mux(io.reg_wr_in_execute && io.csr_inst_in_decode && ~io.csr_imm_inst_in_decode && io.rd_sel_in_execute =/= 0.U && io.csr_wr_in_execute && (io.rd_sel_in_execute === io.rs1_sel_in_decode), true.B, false.B)
+  csr_hazard_in_decode_memory := Mux(io.reg_wr_in_memory && io.csr_inst_in_decode && ~io.csr_imm_inst_in_decode && io.rd_sel_in_memory =/= 0.U && io.csr_wr_in_memory && ~csr_hazard_in_decode_execute && (io.rd_sel_in_memory === io.rs1_sel_in_decode), true.B, false.B)
+  csr_hazard_in_decode_writeback := Mux(io.reg_wr_in_writeback && io.csr_inst_in_decode && ~io.csr_imm_inst_in_decode &&  io.rd_sel_in_writeback =/= 0.U && io.csr_wr_in_writeback && ~csr_hazard_in_decode_execute && ~csr_hazard_in_decode_memory && (io.rd_sel_in_writeback === io.rs1_sel_in_decode), true.B, false.B)
+  // hazard in decode/execute stage
+  when(hazard_in_decode_execute) {
+    io.forward_rs1 := "b001".U
+  }
+
+  // hazard in decode/memory stage
+  when(hazard_in_decode_memory) {
+    io.forward_rs1 := "b010".U
+  }
+
+  // hazard in decode/writeback stage
+  when(hazard_in_decode_writeback) {
+    io.forward_rs1 := "b011".U
+  }
+
+  when(csr_hazard_in_decode_execute) {
+    io.forward_rs1 := "b100".U
+  }
+
+  when(csr_hazard_in_decode_memory) {
+    io.forward_rs1 := "b101".U
+  }
+
+  when(csr_hazard_in_decode_writeback) {
+    io.forward_rs1 := "b110".U
+  }
+
+  when(io.csr_inst_in_decode) {
+    when(io.load_inst_in_memory && io.dccm_rvalid_i) {
+      io.csr_op_en_o := true.B
+    } .elsewhen(~io.load_inst_in_execute && ~io.load_inst_in_memory) {
+      io.csr_op_en_o := true.B
+    }
+  }
+
+
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/Decode.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
new file mode 100644
index 0000000..c7c34e5
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/Decode.scala
@@ -0,0 +1,439 @@
+package core
+
+import chisel3._
+import main.scala.core.CsrControlUnit
+import main.scala.core.csrs.CsrRegisterFile
+
+class Decode extends Module {
+  val io = IO(new Bundle {
+    //   val enable_M_extension = Input(UInt(1.W))
+    val irq_external_i = Input(Bool())
+    val IF_ID_inst = Input(UInt(32.W))
+    val IF_ID_pc = Input(SInt(32.W))
+    val IF_ID_pc4 = Input(SInt(32.W))
+    val MEM_WB_ctrl_regWr = Input(UInt(1.W))
+    val MEM_WB_ctrl_csrWen = Input(Bool())
+    val MEM_WB_rd_sel = Input(UInt(5.W))
+    val ID_EX_ctrl_MemRd = Input(UInt(1.W))
+    val ID_EX_ctrl_regWr = Input(Bool())
+    val ID_EX_ctrl_csrWen = Input(Bool())           // used by csr hazard unit for forwarding
+    val EX_MEM_ctrl_csrWen = Input(Bool())          // used by csr hazard unit for forwarding
+    //    val ID_EX_ctrl_csrAddr = Input(UInt(12.W))      // used by csr hazard unit for forwarding
+    //    val EX_MEM_ctrl_csrAddr = Input(UInt(12.W))     // used by csr hazard unit for forwarding
+    //val ID_EX_rs1_data = Input(SInt(32.W))          // used to forward rs1 data from ID/EX if csr hazard occurs
+    val ID_EX_rd_sel = Input(UInt(5.W))
+    val EX_MEM_rd_sel = Input(UInt(5.W))
+    val EX_MEM_ctrl_MemRd = Input(UInt(1.W))
+    val EX_MEM_ctrl_regWr = Input(Bool())
+    val MEM_WB_ctrl_MemRd = Input(UInt(1.W))
+    val alu_output = Input(SInt(32.W))
+    val EX_MEM_alu_output = Input(SInt(32.W))
+    val MEM_WB_alu_output = Input(SInt(32.W))
+    val dmem_memOut = Input(SInt(32.W))
+    val dccm_rvalid_i = Input(Bool())
+    val writeback_write_data = Input(SInt(32.W)) // rs1 data coming from write back
+    //    val MEM_WB_csrAddr = Input(UInt(12.W))
+    //    val MEM_WB_csr_op = Input(UInt(2.W))
+    val MEM_WB_csr_rdata_i = Input(UInt(32.W)) // csr data coming from MEM_WB
+    val EX_MEM_csr_rdata_i = Input(UInt(32.W))
+    val ID_EX_csr_rdata_i = Input(UInt(32.W))
+
+    val fetch_csr_mtvec_init = Input(Bool())
+    val fetch_csr_if_pc = Input(UInt(32.W))
+    val fetch_csr_save_if = Input(Bool())
+    val fetch_exc_cause_i = Input(UInt(6.W))
+    val fetch_csr_save_cause_i = Input(Bool())
+    val execute_regwrite = Input(UInt(1.W))
+    val mem_regwrite = Input(UInt(1.W))
+    val wb_regwrite = Input(UInt(1.W))
+
+    //val stall = Input(UInt(1.W))
+
+    val pc_out = Output(SInt(32.W))
+    val pc4_out = Output(SInt(32.W))
+    val inst_op_out = Output(UInt(32.W))
+    val func3_out = Output(UInt(3.W))
+    val func7_out = Output(UInt(7.W))
+    val rd_sel_out = Output(UInt(5.W))
+    val rs1_sel_out = Output(UInt(5.W))
+    val rs2_sel_out = Output(UInt(5.W))
+    val rs1_out = Output(SInt(32.W))
+    val rs2_out = Output(SInt(32.W))
+    val csr_rdata_o = Output(UInt(32.W))
+    val imm_out = Output(SInt(32.W))
+    val sb_imm = Output(SInt(32.W))
+    val uj_imm = Output(SInt(32.W))
+    val jalr_output = Output(SInt(32.W))
+    val branchLogic_output = Output(UInt(1.W))
+    val hazardDetection_pc_out = Output(SInt(32.W))
+    val hazardDetection_inst_out = Output(UInt(32.W))
+    val hazardDetection_current_pc_out = Output(SInt(32.W))
+    val hazardDetection_pc_forward = Output(UInt(1.W))
+    val hazardDetection_inst_forward = Output(UInt(1.W))
+    val ctrl_MemWr_out = Output(UInt(1.W))
+    val ctrl_MemRd_out = Output(UInt(1.W))
+    val ctrl_Branch_out = Output(UInt(1.W))
+    val ctrl_RegWr_out = Output(UInt(1.W))
+    val ctrl_CsrWen_out = Output(Bool())
+    val ctrl_MemToReg_out = Output(UInt(1.W))
+    val ctrl_AluOp_out = Output(UInt(4.W))
+    val ctrl_OpA_sel_out = Output(UInt(2.W))
+    val ctrl_OpB_sel_out = Output(UInt(1.W))
+    val ctrl_next_pc_sel_out = Output(UInt(2.W))
+    val reg_7_out = Output(SInt(32.W))
+    //val mret_inst_o = Output(Bool())
+    //val csr_op_o = Output(UInt(2.W))
+    //val fwd_csr_o = Output(Bool())
+    val fetch_irq_pending_o = Output(Bool())
+    val fetch_csr_mstatus_mie_o = Output(Bool())
+    val fetch_csr_mtvec_o = Output(UInt(32.W))
+    val fetch_csr_mepc_o = Output(UInt(32.W))
+    val fetch_mret_inst_o = Output(Bool())
+    //  val M_extension_enabled = Output(UInt(1.W))
+  })
+
+  val hazardDetection = Module(new HazardDetection())
+  val control = Module(new Control())
+  val decodeForwardUnit = Module(new DecodeForwardUnit())
+  val branchLogic = Module(new BranchLogic())
+  val reg_file = Module(new RegisterFile())
+  val imm_generation = Module(new ImmediateGeneration())
+  val structuralDetector = Module(new StructuralDetector())
+  val jalr = Module(new Jalr())
+  val csrRegFile = Module(new CsrRegisterFile())
+  val csrControlUnit = Module(new CsrControlUnit())
+
+
+  val imm_out = Wire(SInt(32.W))
+  val mret_inst = Wire(Bool())
+  val csr_wdata = Wire(UInt(32.W))
+  // detecting MRET instruction
+  mret_inst := Mux(io.IF_ID_inst(6, 0) === "h73".U && io.IF_ID_inst(14, 12) === "b000".U && io.IF_ID_inst(31, 20) === "h302".U(12.W), true.B, false.B)
+
+  // CSR Register file
+  csrRegFile.io.i_hart_id := 0.U
+  csrRegFile.io.i_boot_addr := 0.U
+  csrRegFile.io.i_csr_mtvec_init := io.fetch_csr_mtvec_init
+  csrRegFile.io.i_csr_access := control.io.csr_we_o   // used for checking illegal instructions in csr register file
+  csrRegFile.io.i_csr_wdata := csr_wdata // data read from rs1 register (May need to resolve hazards if rs1 is not yet written with updated value from the instruction in pipe
+  csrRegFile.io.i_csr_op := control.io.csr_op_o
+  csrRegFile.io.i_csr_op_en := csrControlUnit.io.csr_op_en_o // enabling write/set/clear  operation when csr instruction in decode stage
+  csrRegFile.io.i_csr_addr := io.IF_ID_inst(31, 20) // reading the imm value to use as csr address
+  csrRegFile.io.i_irq_software := false.B
+  csrRegFile.io.i_irq_timer := false.B
+  csrRegFile.io.i_irq_external := io.irq_external_i
+  csrRegFile.io.i_nmi_mode := false.B
+  csrRegFile.io.i_pc_if := io.fetch_csr_if_pc
+  csrRegFile.io.i_pc_id := 0.U
+  csrRegFile.io.i_pc_wb := 0.U
+  csrRegFile.io.i_csr_save_if := io.fetch_csr_save_if
+  csrRegFile.io.i_csr_save_id := false.B
+  csrRegFile.io.i_csr_save_wb := false.B
+  csrRegFile.io.i_csr_restore_mret := mret_inst
+  csrRegFile.io.i_csr_restore_dret := false.B
+  csrRegFile.io.i_csr_mcause := io.fetch_exc_cause_i
+  csrRegFile.io.i_csr_save_cause := io.fetch_csr_save_cause_i
+  csrRegFile.io.i_csr_mtval := 0.U
+  csrRegFile.io.i_instr_ret := false.B
+  csrRegFile.io.i_iside_wait := false.B
+  csrRegFile.io.i_jump := false.B
+  csrRegFile.io.i_branch := false.B
+  csrRegFile.io.i_branch_taken := false.B
+  csrRegFile.io.i_mem_load := false.B
+  csrRegFile.io.i_mem_store := false.B
+  csrRegFile.io.i_dside_wait := false.B
+  csrRegFile.io.i_debug_mode := false.B
+  csrRegFile.io.i_debug_cause := 0.U
+  csrRegFile.io.i_debug_csr_save := false.B
+
+  io.fetch_irq_pending_o := csrRegFile.io.o_irq_pending
+  io.fetch_csr_mstatus_mie_o := csrRegFile.io.o_csr_mstatus_mie
+  io.fetch_csr_mtvec_o := csrRegFile.io.o_csr_mtvec
+  io.fetch_csr_mepc_o := csrRegFile.io.o_csr_mepc
+  io.fetch_mret_inst_o := mret_inst
+
+  // Initialize Csr Hazard Unit
+  csrControlUnit.io.reg_wr_in_execute := io.ID_EX_ctrl_regWr
+  csrControlUnit.io.rd_sel_in_execute := io.ID_EX_rd_sel
+  csrControlUnit.io.reg_wr_in_memory := io.EX_MEM_ctrl_regWr
+  csrControlUnit.io.rd_sel_in_memory := io.EX_MEM_rd_sel
+  csrControlUnit.io.reg_wr_in_writeback := io.MEM_WB_ctrl_regWr
+  csrControlUnit.io.rd_sel_in_writeback := io.MEM_WB_rd_sel
+  csrControlUnit.io.rs1_sel_in_decode := io.IF_ID_inst(19, 15)
+  csrControlUnit.io.csr_inst_in_decode := control.io.csr_we_o
+  csrControlUnit.io.load_inst_in_execute := io.ID_EX_ctrl_MemRd
+  csrControlUnit.io.load_inst_in_memory := io.EX_MEM_ctrl_MemRd
+  csrControlUnit.io.dccm_rvalid_i := io.dccm_rvalid_i
+  csrControlUnit.io.csr_wr_in_execute := io.ID_EX_ctrl_csrWen
+  csrControlUnit.io.csr_wr_in_memory := io.EX_MEM_ctrl_csrWen
+  csrControlUnit.io.csr_wr_in_writeback := io.MEM_WB_ctrl_csrWen
+  csrControlUnit.io.csr_imm_inst_in_decode := control.io.csr_imm_type
+
+
+  // Initialize Hazard Detection unit
+  hazardDetection.io.IF_ID_INST := io.IF_ID_inst
+  hazardDetection.io.ID_EX_MEMREAD := io.ID_EX_ctrl_MemRd
+  hazardDetection.io.ID_EX_REGRD := io.ID_EX_rd_sel
+  hazardDetection.io.pc_in := io.IF_ID_pc4
+  hazardDetection.io.current_pc := io.IF_ID_pc
+  hazardDetection.io.IF_ID_MEMREAD := control.io.out_memRead
+
+  // Sending hazard detection outputs for Fetch
+  io.hazardDetection_pc_out := hazardDetection.io.pc_out
+  io.hazardDetection_current_pc_out := hazardDetection.io.current_pc_out
+  io.hazardDetection_pc_forward := hazardDetection.io.pc_forward
+  io.hazardDetection_inst_out := hazardDetection.io.inst_out
+  io.hazardDetection_inst_forward := hazardDetection.io.inst_forward
+
+  // Initialize Control Unit
+  control.io.in_opcode := io.IF_ID_inst(6, 0)
+  // control.io.enable_M_extension := io.enable_M_extension // M extension
+  control.io.func7 := io.IF_ID_inst(31, 25)
+  control.io.func3 := io.IF_ID_inst(14, 12)
+
+  // Initialize Decode Forward Unit
+  decodeForwardUnit.io.ID_EX_REGRD := io.ID_EX_rd_sel
+  decodeForwardUnit.io.ID_EX_MEMRD := io.ID_EX_ctrl_MemRd
+  decodeForwardUnit.io.EX_MEM_REGRD := io.EX_MEM_rd_sel
+  decodeForwardUnit.io.MEM_WB_REGRD := io.MEM_WB_rd_sel
+  decodeForwardUnit.io.EX_MEM_MEMRD := io.EX_MEM_ctrl_MemRd
+  decodeForwardUnit.io.MEM_WB_MEMRD := io.MEM_WB_ctrl_MemRd
+  decodeForwardUnit.io.rs1_sel := io.IF_ID_inst(19, 15)
+  decodeForwardUnit.io.rs2_sel := io.IF_ID_inst(24, 20)
+  decodeForwardUnit.io.ctrl_branch := control.io.out_branch
+
+  decodeForwardUnit.io.execute_regwrite := io.execute_regwrite
+  decodeForwardUnit.io.mem_regwrite := io.mem_regwrite
+  decodeForwardUnit.io.wb_regwrite := io.wb_regwrite
+
+  branchLogic.io.in_func3 := io.IF_ID_inst(14, 12)
+
+  // FOR REGISTER RS1 in BRANCH LOGIC UNIT and JALR UNIT
+
+  // These forwarding values come only when the Control's branch pin is high which means SB-Type
+  // instruction is in the decode stage so we don't need to forward any values to the JALR unit
+  // Hence for all these conditions we wire JALR unit with register file's output by default.
+  when(decodeForwardUnit.io.forward_rs1 === "b0000".U) {
+    // No hazard just use register file data
+    branchLogic.io.in_rs1 := reg_file.io.rs1
+    jalr.io.input_a := reg_file.io.rs1
+  }.elsewhen(decodeForwardUnit.io.forward_rs1 === "b0001".U) {
+    // hazard in alu stage forward data from alu output
+    branchLogic.io.in_rs1 := io.alu_output
+    jalr.io.input_a := reg_file.io.rs1
+  }.elsewhen(decodeForwardUnit.io.forward_rs1 === "b0010".U) {
+    // hazard in EX/MEM stage forward data from EX/MEM.alu_output
+    branchLogic.io.in_rs1 := io.EX_MEM_alu_output
+    jalr.io.input_a := reg_file.io.rs1
+  }.elsewhen(decodeForwardUnit.io.forward_rs1 === "b0011".U) {
+    // hazard in MEM/WB stage forward data from register file write data which will have correct data from the MEM/WB mux
+    branchLogic.io.in_rs1 := reg_file.io.writeData
+    jalr.io.input_a := reg_file.io.rs1
+  }.elsewhen(decodeForwardUnit.io.forward_rs1 === "b0100".U) {
+    // hazard in EX/MEM stage and load type instruction so forwarding from data memory data output instead of EX/MEM.alu_output
+    branchLogic.io.in_rs1 := io.dmem_memOut
+    jalr.io.input_a := reg_file.io.rs1
+  }.elsewhen(decodeForwardUnit.io.forward_rs1 === "b0101".U) {
+    // hazard in MEM/WB stage and load type instruction so forwarding from register file write data which will have the correct output from the mux
+    branchLogic.io.in_rs1 := reg_file.io.writeData
+    jalr.io.input_a := reg_file.io.rs1
+  }
+
+    // These forwarding values come only when the Control's branch pin is low which means JALR
+    // instruction maybe in the decode stage so we don't need to forward any values to the Branch Logic unit
+    // Hence for all these conditions we wire Branch Logic unit with register file's output by default.
+
+    .elsewhen(decodeForwardUnit.io.forward_rs1 === "b0110".U) {
+      // hazard in alu stage forward data from alu output
+      jalr.io.input_a := io.alu_output
+      branchLogic.io.in_rs1 := reg_file.io.rs1
+    }.elsewhen(decodeForwardUnit.io.forward_rs1 === "b0111".U) {
+    // hazard in EX/MEM stage forward data from EX/MEM.alu_output
+    jalr.io.input_a := io.EX_MEM_alu_output
+    branchLogic.io.in_rs1 := reg_file.io.rs1
+  }.elsewhen(decodeForwardUnit.io.forward_rs1 === "b1000".U) {
+    // hazard in MEM/WB stage forward data from register file write data which will have correct data from the MEM/WB mux
+    jalr.io.input_a := reg_file.io.writeData
+    branchLogic.io.in_rs1 := reg_file.io.rs1
+  }.elsewhen(decodeForwardUnit.io.forward_rs1 === "b1001".U) {
+    // hazard in EX/MEM stage and load type instruction so forwarding from data memory data output instead of EX/MEM.alu_output
+    jalr.io.input_a := io.dmem_memOut
+    branchLogic.io.in_rs1 := reg_file.io.rs1
+  }.elsewhen(decodeForwardUnit.io.forward_rs1 === "b1010".U) {
+    // hazard in MEM/WB stage and load type instruction so forwarding from register file write data which will have the correct output from the mux
+    jalr.io.input_a := reg_file.io.writeData
+    branchLogic.io.in_rs1 := reg_file.io.rs1
+  }
+    .otherwise {
+      branchLogic.io.in_rs1 := reg_file.io.rs1
+      jalr.io.input_a := reg_file.io.rs1
+    }
+
+
+  // FOR REGISTER RS2 in BRANCH LOGIC UNIT
+  when(decodeForwardUnit.io.forward_rs2 === "b0000".U) {
+    // No hazard just use register file data
+    branchLogic.io.in_rs2 := reg_file.io.rs2
+  }.elsewhen(decodeForwardUnit.io.forward_rs2 === "b0001".U) {
+    // hazard in alu stage forward data from alu output
+    branchLogic.io.in_rs2 := io.alu_output
+  }.elsewhen(decodeForwardUnit.io.forward_rs2 === "b0010".U) {
+    // hazard in EX/MEM stage forward data from EX/MEM.alu_output
+    branchLogic.io.in_rs2 := io.EX_MEM_alu_output
+  }.elsewhen(decodeForwardUnit.io.forward_rs2 === "b0011".U) {
+    // hazard in MEM/WB stage forward data from register file write data which will have correct data from the MEM/WB mux
+    branchLogic.io.in_rs2 := reg_file.io.writeData
+  }.elsewhen(decodeForwardUnit.io.forward_rs2 === "b0100".U) {
+    // hazard in EX/MEM stage and load type instruction so forwarding from data memory data output instead of EX/MEM.alu_output
+    branchLogic.io.in_rs2 := io.dmem_memOut
+  }.elsewhen(decodeForwardUnit.io.forward_rs2 === "b0101".U) {
+    // hazard in MEM/WB stage and load type instruction so forwarding from register file write data which will have the correct output from the mux
+    branchLogic.io.in_rs2 := reg_file.io.writeData
+  }
+    .otherwise {
+      branchLogic.io.in_rs2 := reg_file.io.rs2
+    }
+
+  jalr.io.input_b := imm_generation.io.i_imm
+
+  // Sending the branch logic unit output for Fetch
+  io.branchLogic_output := branchLogic.io.output
+
+  // The Mux after the Control module which selects the control inputs of
+  // the ID/EX Pipeline register either from the Control or default 0 values
+  // for stalling the pipeline one clock cycle.
+  when(hazardDetection.io.ctrl_forward === "b1".U) {
+    setControlPinsToZero()
+  }.otherwise {
+    sendDefaultControlPins()
+  }
+
+
+  // Initialize Register File
+  reg_file.io.rs1_sel := io.IF_ID_inst(19, 15)
+  reg_file.io.rs2_sel := io.IF_ID_inst(24, 20)
+  reg_file.io.regWrite := io.MEM_WB_ctrl_regWr
+  reg_file.io.rd_sel := io.MEM_WB_rd_sel
+  reg_file.io.writeData := Mux(io.MEM_WB_ctrl_csrWen, io.MEM_WB_csr_rdata_i.asSInt(), io.writeback_write_data)
+
+
+  // Initialize Immediate Generation
+  imm_generation.io.instruction := io.IF_ID_inst
+  imm_generation.io.pc := io.IF_ID_pc
+
+  // Sending immediate generation outputs for Fetch
+  io.sb_imm := imm_generation.io.sb_imm
+  io.uj_imm := imm_generation.io.uj_imm
+  io.jalr_output := jalr.io.output
+
+  // Initialize Structural Hazard Detector
+  structuralDetector.io.rs1_sel := io.IF_ID_inst(19, 15)
+  structuralDetector.io.rs2_sel := io.IF_ID_inst(24, 20)
+  structuralDetector.io.MEM_WB_REGRD := io.MEM_WB_rd_sel
+  structuralDetector.io.MEM_WB_regWr := io.MEM_WB_ctrl_regWr
+  structuralDetector.io.inst_op_in := io.IF_ID_inst(6, 0)
+
+  // FOR RS1
+  when(structuralDetector.io.fwd_rs1 === 1.U) {
+    // additionally checking if the instruction is lui or not. We should not pass out
+    // any value from the rs1 if lui is currently being decoded since it does not have
+    // an rs1 field in it's encoding
+    io.rs1_out := Mux(io.IF_ID_inst(6, 0) =/= "b0110111".U, reg_file.io.writeData, 0.S)
+  }.otherwise {
+    io.rs1_out := Mux(io.IF_ID_inst(6, 0) =/= "b0110111".U, reg_file.io.rs1, 0.S)
+  }
+
+  // FOR RS2
+  when(structuralDetector.io.fwd_rs2 === 1.U) {
+    // additionally checking if the instruction is lui or not. We should not pass out
+    // any value from the rs2 if lui is currently being decoded since it does not have
+    // an rs2 field in it's encoding
+    io.rs2_out := Mux(io.IF_ID_inst(6, 0) =/= "b0110111".U, reg_file.io.writeData, 0.S)
+  }.otherwise {
+    io.rs2_out := Mux(io.IF_ID_inst(6, 0) =/= "b0110111".U, reg_file.io.rs2, 0.S)
+  }
+
+  when(control.io.out_extend_sel === "b00".U) {
+    // I-Type instruction
+    imm_out := imm_generation.io.i_imm
+  }.elsewhen(control.io.out_extend_sel === "b01".U) {
+    // S-Type instruction
+    imm_out := imm_generation.io.s_imm
+  }.elsewhen(control.io.out_extend_sel === "b10".U) {
+    // U-Type instruction
+    imm_out := imm_generation.io.u_imm
+  }.otherwise {
+    imm_out := 0.S(32.W)
+  }
+
+  io.pc_out := io.IF_ID_pc
+  io.pc4_out := io.IF_ID_pc4
+  io.inst_op_out := io.IF_ID_inst(6, 0) // used by the forward unit to see if instruction is eligible for data hazards
+  io.func3_out := io.IF_ID_inst(14, 12)
+  io.func7_out := io.IF_ID_inst(31, 25)
+  io.rd_sel_out := io.IF_ID_inst(11, 7)
+  io.rs1_sel_out := io.IF_ID_inst(19, 15)
+  io.rs2_sel_out := io.IF_ID_inst(24, 20)
+
+  //  io.csr_op_o := control.io.csr_op_o
+
+  def setControlPinsToZero(): Unit = {
+    io.ctrl_MemWr_out := 0.U
+    io.ctrl_MemRd_out := 0.U
+    io.ctrl_Branch_out := 0.U
+    io.ctrl_RegWr_out := 0.U
+    io.ctrl_CsrWen_out := false.B
+    io.ctrl_MemToReg_out := 0.U
+    io.ctrl_AluOp_out := 0.U
+    io.ctrl_OpA_sel_out := 0.U
+    io.ctrl_OpB_sel_out := 0.U
+    io.ctrl_next_pc_sel_out := 0.U
+    //   io.M_extension_enabled := 0.U
+  }
+
+  def sendDefaultControlPins(): Unit = {
+    io.ctrl_MemWr_out := control.io.out_memWrite
+    io.ctrl_MemRd_out := control.io.out_memRead
+    io.ctrl_Branch_out := control.io.out_branch
+    io.ctrl_RegWr_out := control.io.out_regWrite
+    io.ctrl_CsrWen_out := control.io.csr_we_o
+    io.ctrl_MemToReg_out := control.io.out_memToReg
+    io.ctrl_AluOp_out := control.io.out_aluOp
+    io.ctrl_OpA_sel_out := control.io.out_operand_a_sel
+    io.ctrl_OpB_sel_out := control.io.out_operand_b_sel
+    io.ctrl_next_pc_sel_out := control.io.out_next_pc_sel
+    //   io.M_extension_enabled := control.io.M_extension_enabled
+  }
+
+  io.reg_7_out := reg_file.io.reg_7
+
+  io.imm_out := imm_out
+
+  when(control.io.csr_imm_type === 1.U) {
+    csr_wdata := io.IF_ID_inst(19,15)   // selecting the imm encoded inside the rs1 field and writing to csr reg file
+  } .otherwise {
+    when(csrControlUnit.io.forward_rs1 === 1.U) {
+      csr_wdata := io.alu_output.asUInt()
+    }.elsewhen(csrControlUnit.io.forward_rs1 === 2.U) {
+      // hazard in memory stage. If load instruction in memory stage then forward data read from memory
+      // else forward alu output data from EX/MEM pipeline register
+      csr_wdata := Mux(io.EX_MEM_ctrl_MemRd === 1.U, io.dmem_memOut.asUInt(), io.EX_MEM_alu_output.asUInt())
+    }.elsewhen(csrControlUnit.io.forward_rs1 === 3.U) {
+      csr_wdata := io.writeback_write_data.asUInt()
+    }.elsewhen(csrControlUnit.io.forward_rs1 === 4.U) {
+      // csr hazard in excute stage
+      csr_wdata := io.ID_EX_csr_rdata_i
+    }.elsewhen(csrControlUnit.io.forward_rs1 === 5.U) {
+      // csr hazard in memory stage
+      csr_wdata := io.EX_MEM_csr_rdata_i
+    }.elsewhen(csrControlUnit.io.forward_rs1 === 6.U) {
+      csr_wdata := io.MEM_WB_csr_rdata_i
+    }.otherwise {
+      csr_wdata := reg_file.io.rs1.asUInt()
+    }
+  }
+
+
+  io.csr_rdata_o := csrRegFile.io.o_csr_rdata
+
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/DecodeForwardUnit.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/DecodeForwardUnit.scala
new file mode 100644
index 0000000..9724c5f
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/DecodeForwardUnit.scala
@@ -0,0 +1,191 @@
+package core
+
+import chisel3._
+
+class DecodeForwardUnit extends Module {
+  val io = IO(new Bundle {
+    val ID_EX_REGRD = Input(UInt(5.W))
+    val ID_EX_MEMRD = Input(UInt(1.W))
+    val EX_MEM_REGRD = Input(UInt(5.W))
+    val EX_MEM_MEMRD = Input(UInt(1.W))
+    val MEM_WB_REGRD = Input(UInt(5.W))
+    val MEM_WB_MEMRD = Input(UInt(1.W))
+    val execute_regwrite = Input(UInt(1.W))
+    val mem_regwrite = Input(UInt(1.W))
+    val wb_regwrite = Input(UInt(1.W))
+    val rs1_sel = Input(UInt(5.W))
+    val rs2_sel = Input(UInt(5.W))
+    val ctrl_branch = Input(UInt(1.W))
+    val forward_rs1 = Output(UInt(4.W))
+    val forward_rs2 = Output(UInt(4.W))
+  })
+
+    io.forward_rs1 := "b0000".U
+    io.forward_rs2 := "b0000".U
+
+
+    when(io.ctrl_branch === 1.U) {
+      // ALU Hazard
+      when(io.ID_EX_REGRD =/= "b00000".U && io.ID_EX_MEMRD =/= 1.U && (io.ID_EX_REGRD === io.rs1_sel) && (io.ID_EX_REGRD === io.rs2_sel)) {
+        io.forward_rs1 := "b0001".U
+        io.forward_rs2 := "b0001".U
+      } .elsewhen(io.ID_EX_REGRD =/= "b00000".U && io.ID_EX_MEMRD =/= 1.U && (io.ID_EX_REGRD === io.rs1_sel)) {
+        io.forward_rs1 := "b0001".U
+      } .elsewhen(io.ID_EX_REGRD =/= "b00000".U && io.ID_EX_MEMRD =/= 1.U && (io.ID_EX_REGRD === io.rs2_sel)) {
+        io.forward_rs2 := "b0001".U
+      }
+
+      // EX/MEM Hazard
+      when(io.EX_MEM_REGRD =/= "b00000".U && io.EX_MEM_MEMRD =/= 1.U &&
+        ~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel) && (io.ID_EX_REGRD === io.rs2_sel)) &&
+        (io.EX_MEM_REGRD === io.rs1_sel) && (io.EX_MEM_REGRD === io.rs2_sel)) {
+
+        io.forward_rs1 := "b0010".U
+        io.forward_rs2 := "b0010".U
+
+      } .elsewhen(io.EX_MEM_REGRD =/= "b00000".U && io.EX_MEM_MEMRD =/= 1.U &&
+        ~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs2_sel)) &&
+        (io.EX_MEM_REGRD === io.rs2_sel)) {
+
+        io.forward_rs2 := "b0010".U
+
+      } .elsewhen(io.EX_MEM_REGRD =/= "b00000".U && io.EX_MEM_MEMRD =/= 1.U &&
+        ~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel)) &&
+        (io.EX_MEM_REGRD === io.rs1_sel)) {
+
+        io.forward_rs1 := "b0010".U
+
+      } .elsewhen(io.EX_MEM_REGRD =/= "b00000".U && io.EX_MEM_MEMRD === 1.U &&
+        ~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel) && (io.ID_EX_REGRD === io.rs2_sel)) &&
+        (io.EX_MEM_REGRD === io.rs1_sel) && (io.EX_MEM_REGRD === io.rs2_sel)) {
+        // FOR Load instructions
+        io.forward_rs1 := "b0100".U
+        io.forward_rs2 := "b0100".U
+
+      } .elsewhen(io.EX_MEM_REGRD =/= "b00000".U && io.EX_MEM_MEMRD === 1.U &&
+        ~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs2_sel)) &&
+        (io.EX_MEM_REGRD === io.rs2_sel)) {
+
+        io.forward_rs2 := "b0100".U
+
+      } .elsewhen(io.ctrl_branch === 1.U && io.EX_MEM_REGRD =/= "b00000".U && io.EX_MEM_MEMRD === 1.U &&
+        ~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel)) &&
+        (io.EX_MEM_REGRD === io.rs1_sel)) {
+
+        io.forward_rs1 := "b0100".U
+
+      }
+
+      // MEM/WB Hazard
+      when(io.MEM_WB_REGRD =/= "b00000".U && io.MEM_WB_MEMRD =/= 1.U &&
+        // IF NOT ALU HAZARD
+        ~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel) && (io.ID_EX_REGRD === io.rs2_sel)) &&
+        // IF NOT EX/MEM HAZARD
+        ~((io.EX_MEM_REGRD =/= "b00000".U) && (io.EX_MEM_REGRD === io.rs1_sel) && (io.EX_MEM_REGRD === io.rs2_sel)) &&
+        (io.MEM_WB_REGRD === io.rs1_sel) && (io.MEM_WB_REGRD === io.rs2_sel)) {
+
+        io.forward_rs1 := "b0011".U
+        io.forward_rs2 := "b0011".U
+
+      }
+        .elsewhen(io.MEM_WB_REGRD =/= "b00000".U && io.MEM_WB_MEMRD =/= 1.U &&
+          // IF NOT ALU HAZARD
+          ~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs2_sel)) &&
+          // IF NOT EX/MEM HAZARD
+          ~((io.EX_MEM_REGRD =/= "b00000".U) && (io.EX_MEM_REGRD === io.rs2_sel)) &&
+          (io.MEM_WB_REGRD === io.rs2_sel)) {
+
+          io.forward_rs2 := "b0011".U
+
+        }
+        .elsewhen(io.MEM_WB_REGRD =/= "b00000".U && io.MEM_WB_MEMRD =/= 1.U &&
+          // IF NOT ALU HAZARD
+          ~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel)) &&
+          // IF NOT EX/MEM HAZARD
+          ~((io.EX_MEM_REGRD =/= "b00000".U) && (io.EX_MEM_REGRD === io.rs1_sel)) &&
+          (io.MEM_WB_REGRD === io.rs1_sel)) {
+
+          io.forward_rs1 := "b0011".U
+
+        } .elsewhen(io.MEM_WB_REGRD =/= "b00000".U && io.MEM_WB_MEMRD === 1.U &&
+        // IF NOT ALU HAZARD
+        ~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel) && (io.ID_EX_REGRD === io.rs2_sel)) &&
+        // IF NOT EX/MEM HAZARD
+        ~((io.EX_MEM_REGRD =/= "b00000".U) && (io.EX_MEM_REGRD === io.rs1_sel) && (io.EX_MEM_REGRD === io.rs2_sel)) &&
+        (io.MEM_WB_REGRD === io.rs1_sel) && (io.MEM_WB_REGRD === io.rs2_sel)) {
+        // FOR Load instructions
+        io.forward_rs1 := "b0101".U
+        io.forward_rs2 := "b0101".U
+
+      }
+        .elsewhen(io.MEM_WB_REGRD =/= "b00000".U && io.MEM_WB_MEMRD === 1.U &&
+          // IF NOT ALU HAZARD
+          ~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs2_sel)) &&
+          // IF NOT EX/MEM HAZARD
+          ~((io.EX_MEM_REGRD =/= "b00000".U) && (io.EX_MEM_REGRD === io.rs2_sel)) &&
+          (io.MEM_WB_REGRD === io.rs2_sel)) {
+
+          io.forward_rs2 := "b0101".U
+
+        }
+        .elsewhen(io.MEM_WB_REGRD =/= "b00000".U && io.MEM_WB_MEMRD === 1.U &&
+          // IF NOT ALU HAZARD
+          ~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel)) &&
+          // IF NOT EX/MEM HAZARD
+          ~((io.EX_MEM_REGRD =/= "b00000".U) && (io.EX_MEM_REGRD === io.rs1_sel))&&
+          (io.MEM_WB_REGRD === io.rs1_sel)) {
+
+          io.forward_rs1 := "b0101".U
+
+        }
+
+    }
+      // Forwarding for JALR unit
+      .elsewhen(io.ctrl_branch === 0.U) {
+        // ALU Hazard
+        when(io.execute_regwrite === 1.U && io.ID_EX_REGRD =/= "b00000".U && io.ID_EX_MEMRD =/= 1.U && (io.ID_EX_REGRD === io.rs1_sel)){
+          io.forward_rs1 := "b0110".U
+        }
+
+        // EX/MEM Hazard
+        when(io.mem_regwrite === 1.U && io.EX_MEM_REGRD =/= "b00000".U && io.EX_MEM_MEMRD =/= 1.U &&
+          ~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel)) &&
+          (io.EX_MEM_REGRD === io.rs1_sel)) {
+
+          io.forward_rs1 := "b0111".U
+
+        }
+          .elsewhen(io.mem_regwrite === 1.U && io.EX_MEM_REGRD =/= "b00000".U && io.EX_MEM_MEMRD === 1.U &&
+            ~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel)) &&
+            (io.EX_MEM_REGRD === io.rs1_sel)) {
+            // FOR Load instructions
+            io.forward_rs1 := "b1001".U
+
+        }
+
+
+        // MEM/WB Hazard
+        when(io.wb_regwrite === 1.U && io.MEM_WB_REGRD =/= "b00000".U && io.MEM_WB_MEMRD =/= 1.U &&
+          // IF NOT ALU HAZARD
+          ~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel)) &&
+          // IF NOT EX/MEM HAZARD
+          ~((io.EX_MEM_REGRD =/= "b00000".U) && (io.EX_MEM_REGRD === io.rs1_sel)) &&
+          (io.MEM_WB_REGRD === io.rs1_sel)) {
+
+          io.forward_rs1 := "b1000".U
+
+        }
+           .elsewhen(io.wb_regwrite === 1.U && io.MEM_WB_REGRD =/= "b00000".U && io.MEM_WB_MEMRD === 1.U &&
+          // IF NOT ALU HAZARD
+          ~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel)) &&
+          // IF NOT EX/MEM HAZARD
+          ~((io.EX_MEM_REGRD =/= "b00000".U) && (io.EX_MEM_REGRD === io.rs1_sel)) &&
+          (io.MEM_WB_REGRD === io.rs1_sel)) {
+          // FOR Load instructions
+          io.forward_rs1 := "b1010".U
+
+        }
+
+
+      }
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
new file mode 100644
index 0000000..b01c752
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/EX_MEM.scala
@@ -0,0 +1,95 @@
+package core
+
+import chisel3._
+
+class EX_MEM extends Module {
+    val io = IO(new Bundle {
+        val ctrl_MemWr_in = Input(UInt(1.W))
+        val ctrl_MemRd_in = Input(UInt(1.W))
+        val ctrl_RegWr_in = Input(UInt(1.W))
+        val ctrl_CsrWen_in = Input(Bool())
+        val ctrl_MemToReg_in = Input(UInt(1.W))
+        val rs2_in = Input(SInt(32.W))
+        val rd_sel_in = Input(UInt(5.W))
+        val rs2_sel_in = Input(UInt(5.W))
+        val alu_in = Input(SInt(32.W))
+        val EX_MEM_func3 = Input(UInt(3.W))
+//        val csr_addr_in = Input(SInt(32.W))
+//        val csr_op_in = Input(UInt(2.W))
+        val csr_data_i = Input(UInt(32.W))
+
+        val stall = Input(UInt(1.W))
+
+        val ctrl_MemWr_out = Output(UInt(1.W))
+        val ctrl_MemRd_out = Output(UInt(1.W))
+        val ctrl_RegWr_out = Output(UInt(1.W))
+        val ctrl_CsrWen_out = Output(Bool())
+        val ctrl_MemToReg_out = Output(UInt(1.W))
+        val rs2_out = Output(SInt(32.W))
+        val rd_sel_out = Output(UInt(5.W))
+        val rs2_sel_out = Output(UInt(5.W))
+        val alu_output = Output(SInt(32.W))
+        val EX_MEM_func3_out  = Output(UInt(3.W))
+//        val csr_addr_out = Output(SInt(32.W))
+//        val csr_op_out = Output(UInt(2.W))
+        val csr_data_o = Output(UInt(32.W))
+    })
+        val reg_memWr = RegInit(0.U(1.W))
+        val reg_memRd = RegInit(0.U(1.W))
+        val reg_regWr = RegInit(0.U(1.W))
+        val reg_csrWen = RegInit(false.B)
+        val reg_memToReg = RegInit(0.U(1.W))
+        val reg_rs2 = RegInit(0.S(32.W))
+        val reg_rd_sel = RegInit(0.U(5.W))
+        val reg_rs2_sel = RegInit(0.U(5.W))
+        val reg_alu_output = RegInit(0.S(32.W))
+        val reg_func3      = RegInit(0.U(3.W))
+//        val reg_csr_addr   = RegInit(0.S(32.W))
+//        val reg_csr_op = RegInit(0.U(2.W))
+        val reg_csr_data = RegInit(0.U(32.W))
+
+    when(io.stall =/= 1.U) {
+        reg_memWr := io.ctrl_MemWr_in
+        reg_memRd := io.ctrl_MemRd_in
+        reg_regWr := io.ctrl_RegWr_in
+        reg_csrWen := io.ctrl_CsrWen_in
+        reg_memToReg := io.ctrl_MemToReg_in
+        reg_rs2 := io.rs2_in
+        reg_rd_sel := io.rd_sel_in
+        reg_rs2_sel := io.rs2_sel_in
+        reg_alu_output := io.alu_in
+        reg_func3      := io.EX_MEM_func3
+//        reg_csr_addr    := io.csr_addr_in
+//        reg_csr_op := io.csr_op_in
+        reg_csr_data := io.csr_data_i
+
+    } .otherwise {
+        reg_memWr := reg_memWr
+        reg_memRd := reg_memRd
+        reg_regWr := reg_regWr
+        reg_csrWen := reg_csrWen
+        reg_memToReg := reg_memToReg
+        reg_rs2 := reg_rs2
+        reg_rd_sel := reg_rd_sel
+        reg_rs2_sel :=  reg_rs2_sel
+        reg_alu_output := reg_alu_output
+        reg_func3     := reg_func3
+//        reg_csr_addr := reg_csr_addr
+//        reg_csr_op := reg_csr_op
+        reg_csr_data := reg_csr_data
+    }
+
+    io.ctrl_MemWr_out := reg_memWr
+    io.ctrl_MemRd_out := reg_memRd
+    io.ctrl_RegWr_out := reg_regWr
+    io.ctrl_CsrWen_out := reg_csrWen
+    io.ctrl_MemToReg_out := reg_memToReg
+    io.rs2_out := reg_rs2
+    io.rd_sel_out := reg_rd_sel
+    io.rs2_sel_out := reg_rs2_sel
+    io.alu_output := reg_alu_output
+    io.EX_MEM_func3_out := reg_func3
+//    io.csr_addr_out := reg_csr_addr
+//    io.csr_op_out := reg_csr_op
+    io.csr_data_o := reg_csr_data
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/Execute.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/Execute.scala
new file mode 100644
index 0000000..eaf63de
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/Execute.scala
@@ -0,0 +1,169 @@
+package core
+
+import chisel3._
+
+class Execute extends Module {
+  val io = IO(new Bundle {
+    val EX_MEM_rd_sel = Input(UInt(5.W))
+    val MEM_WB_rd_sel = Input(UInt(5.W))
+    val ID_EX_rs1_sel = Input(UInt(5.W))
+    val ID_EX_rs2_sel = Input(UInt(5.W))
+    val EX_MEM_ctrl_RegWr = Input(UInt(1.W))
+    val EX_MEM_ctrl_csrWen = Input(Bool())    // used to detect if csr instruction in memory stage
+    val MEM_WB_ctrl_csrWen = Input(Bool())    // used to detect if csr instruction in writeback stage
+    val MEM_WB_ctrl_RegWr = Input(UInt(1.W))
+    val ID_EX_ctrl_OpA_sel = Input(UInt(2.W))
+    val ID_EX_ctrl_OpB_sel = Input(UInt(1.W))
+    val ID_EX_pc4 = Input(SInt(32.W))
+    val ID_EX_pc_out = Input(SInt(32.W))
+    val ID_EX_rs1 = Input(SInt(32.W))
+    val ID_EX_rs2 = Input(SInt(32.W))
+    val ID_EX_csr_data = Input(UInt(32.W))
+    val EX_MEM_alu_output = Input(SInt(32.W))
+    val EX_MEM_csr_rdata = Input(UInt(32.W))  // used to forward csr data if instruction is dependent on csr inst in memory stage
+    val MEM_WB_csr_rdata = Input(UInt(32.W))  // used to forward csr data if instruction is dependent on csr inst in write back stage
+    val writeback_write_data = Input(SInt(32.W))
+    val ID_EX_imm = Input(SInt(32.W))
+//    val ID_EX_csr_op = Input(UInt(2.W))
+    val ID_EX_ctrl_AluOp = Input(UInt(4.W))
+    val ID_EX_func7 = Input(UInt(7.W))
+    val ID_EX_inst_op = Input(UInt(7.W))
+    val ID_EX_func3 = Input(UInt(3.W))
+    val ID_EX_rd_sel = Input(UInt(5.W))
+    val ID_EX_ctrl_MemWr = Input(UInt(1.W))
+    val ID_EX_ctrl_MemRd = Input(UInt(1.W))
+    val ID_EX_ctrl_RegWr = Input(UInt(1.W))
+    val ID_EX_ctrl_CsrWen = Input(Bool())
+    val ID_EX_ctrl_MemToReg = Input(UInt(1.W))
+  //  val M_extension_enabled = Input(UInt(1.W))
+
+
+    val rs2_out = Output(SInt(32.W))
+    val alu_output = Output(SInt(32.W))
+    val rd_sel_out = Output(UInt(5.W))
+    val rs2_sel_out = Output(UInt(5.W))
+    val ctrl_MemWr_out = Output(UInt(1.W))
+    val ctrl_MemRd_out = Output(UInt(1.W))
+    val ctrl_RegWr_out = Output(UInt(1.W))
+    val ctrl_CsrWe_out = Output(Bool())
+    val ctrl_MemToReg_out = Output(UInt(1.W))
+    val func3_out        = Output(UInt(3.W))
+    val csr_addr_out = Output(SInt(32.W))
+//    val csr_op_o = Output(UInt(2.W))
+    val csr_data_o = Output(UInt(32.W))
+  })
+
+
+  val forwardUnit = Module(new ForwardUnit())
+  val alu = Module(new Alu())
+  val alu_control = Module(new AluControl())
+
+  // Initialize forward unit
+  forwardUnit.io.ID_EX_inst_op := io.ID_EX_inst_op
+  forwardUnit.io.EX_MEM_REGRD := io.EX_MEM_rd_sel
+  forwardUnit.io.MEM_WB_REGRD := io.MEM_WB_rd_sel
+  forwardUnit.io.ID_EX_REGRS1 := io.ID_EX_rs1_sel
+  forwardUnit.io.ID_EX_REGRS2 := io.ID_EX_rs2_sel
+  forwardUnit.io.EX_MEM_REGWR := io.EX_MEM_ctrl_RegWr
+  forwardUnit.io.MEM_WB_REGWR := io.MEM_WB_ctrl_RegWr
+
+  // Controlling Operand A for ALU
+  when (io.ID_EX_ctrl_OpA_sel === "b10".U) {
+    alu.io.oper_a := io.ID_EX_pc4
+  }
+  .elsewhen(io.ID_EX_ctrl_OpA_sel === "b01".U)
+   {
+      alu.io.oper_a := io.ID_EX_pc_out 
+   }
+ .otherwise {
+    when(forwardUnit.io.forward_a === "b00".U) {
+      alu.io.oper_a := io.ID_EX_rs1
+    } .elsewhen(forwardUnit.io.forward_a === "b01".U) {
+      alu.io.oper_a := Mux(io.EX_MEM_ctrl_csrWen, io.EX_MEM_csr_rdata.asSInt(), io.EX_MEM_alu_output)
+    } .elsewhen(forwardUnit.io.forward_a === "b10".U) {
+      alu.io.oper_a := Mux(io.MEM_WB_ctrl_csrWen, io.MEM_WB_csr_rdata.asSInt(), io.writeback_write_data)
+    } .otherwise {
+      alu.io.oper_a := io.ID_EX_rs1
+    }
+  }
+
+  // Controlling Operand B for ALU
+  when(io.ID_EX_ctrl_OpB_sel === "b1".U) {
+    alu.io.oper_b := io.ID_EX_imm
+    when(forwardUnit.io.forward_b === "b00".U) {
+      io.rs2_out := io.ID_EX_rs2
+    } .elsewhen(forwardUnit.io.forward_b === "b01".U) {
+      io.rs2_out := Mux(io.EX_MEM_ctrl_csrWen, io.EX_MEM_csr_rdata.asSInt(), io.EX_MEM_alu_output)
+    } .elsewhen(forwardUnit.io.forward_b === "b10".U) {
+      io.rs2_out := Mux(io.MEM_WB_ctrl_csrWen, io.MEM_WB_csr_rdata.asSInt(), io.writeback_write_data)
+    } .otherwise {
+      io.rs2_out := io.ID_EX_rs2
+    }
+
+
+  } .otherwise {
+    when(forwardUnit.io.forward_b === "b00".U) {
+      alu.io.oper_b := io.ID_EX_rs2
+      io.rs2_out := io.ID_EX_rs2
+    } .elsewhen(forwardUnit.io.forward_b === "b01".U) {
+      alu.io.oper_b := Mux(io.EX_MEM_ctrl_csrWen, io.EX_MEM_csr_rdata.asSInt(), io.EX_MEM_alu_output)
+      io.rs2_out := Mux(io.EX_MEM_ctrl_csrWen, io.EX_MEM_csr_rdata.asSInt(), io.EX_MEM_alu_output)
+    } .elsewhen(forwardUnit.io.forward_b === "b10".U) {
+      alu.io.oper_b := Mux(io.MEM_WB_ctrl_csrWen, io.MEM_WB_csr_rdata.asSInt(), io.writeback_write_data)
+      io.rs2_out := Mux(io.MEM_WB_ctrl_csrWen, io.MEM_WB_csr_rdata.asSInt(), io.writeback_write_data)
+    } .otherwise {
+      alu.io.oper_b := io.ID_EX_rs2
+      io.rs2_out := io.ID_EX_rs2
+    }
+  }
+
+  // Initializing Alu Control
+  alu_control.io.aluOp := io.ID_EX_ctrl_AluOp
+  alu_control.io.func7 := io.ID_EX_func7
+  alu_control.io.func3 := io.ID_EX_func3
+ // alu_control.io.M_extension := io.M_extension_enabled
+
+  // Connecting ALU Control output to ALU input
+  alu.io.aluCtrl := alu_control.io.output
+
+  // Passing the ALU output to the EX/MEM pipeline register
+  io.alu_output := alu.io.output
+
+  // Passing the rd_sel value in the EX/MEM pipeline register
+  io.rd_sel_out := io.ID_EX_rd_sel
+  io.rs2_sel_out := io.ID_EX_rs2_sel
+  io.func3_out := io.ID_EX_func3
+  // Passing the control signals to EX/MEM pipeline register
+  io.ctrl_MemWr_out := io.ID_EX_ctrl_MemWr
+  io.ctrl_MemRd_out := io.ID_EX_ctrl_MemRd
+  io.ctrl_RegWr_out := io.ID_EX_ctrl_RegWr
+  io.ctrl_CsrWe_out := io.ID_EX_ctrl_CsrWen
+  io.ctrl_MemToReg_out := io.ID_EX_ctrl_MemToReg
+  io.csr_addr_out := io.ID_EX_imm
+//  io.csr_op_o := io.ID_EX_csr_op
+  io.csr_data_o := io.ID_EX_csr_data
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
new file mode 100644
index 0000000..35dee9f
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/Fetch.scala
@@ -0,0 +1,212 @@
+package core
+
+import chisel3._
+import chisel3.util._
+import main.scala.core.csrs.{Exc_Cause}
+
+class Fetch extends Module {
+  val io = IO(new Bundle {
+    // ------------------------------------ //
+    // instruction memory interface(inputs) //
+    // ------------------------------------ //
+    
+    val core_instr_gnt_i                             =       Input(Bool())
+    val core_instr_rvalid_i                          =       Input(Bool())
+    val core_instr_rdata_i                           =       Input(UInt(32.W))
+
+    // ------------------------------------ //
+    // csr register file(inputs/outputs)    //
+    // ------------------------------------ //
+
+    val csrRegFile_irq_pending_i                     =       Input(Bool())
+    val csrRegFile_csr_mstatus_mie_i                 =       Input(Bool())
+    val csrRegFile_csr_mtvec_i                       =       Input(UInt(32.W))
+    val csrRegFile_csr_mtvec_init_o                  =       Output(Bool())
+    val csrRegFile_csr_save_cause_o                  =       Output(Bool())
+    val csrRegFile_csr_save_if_o                     =       Output(Bool())
+    val csrRegFile_csr_if_pc_o                       =       Output(UInt(32.W))
+    val csrRegFile_exc_cause_o                       =       Output(UInt(6.W))
+    val csrRegFile_csr_mepc_i                        =       Input(UInt(32.W))
+
+    val core_init_mtvec_i                            =       Input(Bool())
+
+    val decode_sb_imm_i                              =       Input(SInt(32.W))
+    val decode_uj_imm_i                              =       Input(SInt(32.W))
+    val decode_jalr_imm_i                            =       Input(SInt(32.W))
+    val decode_ctrl_next_pc_sel_i                    =       Input(UInt(2.W))
+    val decode_ctrl_out_branch_i                     =       Input(UInt(1.W))
+    val decode_branchLogic_output_i                  =       Input(UInt(1.W))
+    val decode_hazardDetection_pc_i                  =       Input(SInt(32.W))
+    val decode_hazardDetection_inst_i                =       Input(UInt(32.W))
+    val decode_hazardDetection_current_pc_i          =       Input(SInt(32.W))
+    val decode_hazardDetection_pc_forward_i          =       Input(UInt(1.W))
+    val decode_hazardDetection_inst_forward_i        =       Input(UInt(1.W))
+
+    // true when mret instruction decoded in decoded stage
+    val decode_mret_inst_i                           =       Input(Bool())
+
+    val core_stall_i                                 =       Input(Bool())
+
+    // ------------------------------------- //
+    // instruction memory interface(outputs) //
+    // ------------------------------------- //
+
+    val core_instr_addr_o                            =       Output(UInt(32.W))
+    val core_instr_req_o                             =       Output(Bool())
+
+    // ------------------------------------- //
+    //        decode stage (outputs)         //
+    // ------------------------------------- //
+
+    val decode_if_id_pc_o                            =       Output(SInt(32.W))
+    val decode_if_id_pc4_o                           =       Output(SInt(32.W))
+    val decode_if_id_inst_o                          =       Output(UInt(32.W))
+  })
+
+  //                      ____________________s???s???s???s
+  //                      ___________________s$$$$$$s..s..?..?..?
+  //                      __________________$$$$$$$$$$$$s..s.?..?
+  //                      ____________________$$$$$$$$$$$$$$s…?
+  //                      ______________ s$$$$$$(O)$$$$$$$$$$$$.?
+  //                      ____________ €$$$$$$$$$$$$$$$$$$$$s..?..s
+  //                      _____________s$$$$$$$$$$$$$$$$$$$$$$s..?
+  //                      _____________________s$$$$$$$$$$$$$$..s..?
+  //                      ______________________$$$$$$$$$$$$s..s..?
+  //                      ______________________$$$$$$$$$$$$.s.?.s.?
+  //                      _____________________$$$$$$$$$$$$$s..s….?
+  //                      ____________________$$$$$$$$$$$$$$s_??s.?
+  //                      ___________________$$$$$$$$$$$$$$$s.s….?
+  //                      _____s$$$$________$$$$$$$$$$$$$$$$$..s?
+  //                      ____$$$$$$$$_____$$$$$$$$$$$$$$$$$$s…s
+  //                      ____$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$_s_?__s$s
+  //                      ____$$__$$$$$$$$$$$$$$$$$$$$$$$$$$_____s$$$
+  //                      ____$$____$$$$$$$$$$$$$$$$$$$$$$s_____s$$$$s
+  //                      ___$$$$$$$$$$$$$$$$$$$$$$$$$$_$$_____s$$$$$$
+  //                      __$$$$$$$$$$$$$$$$$$$$$$$$$$$$_$____s$$$$$$$
+  //                      __$$$$__$$$$$$$$$$$$$$$$$$$$$$$____s$$$$$$$$
+  //                      ___$$$________$$$$$$$$$$$$$$$$$$___s$$$$$$$
+  //                      ____$$$s______$$$$$$$$$$$$$$$$$$$__s$$$$$$
+  //                      _____$$$_______$$$$$$$$$$$$$$$$$$$_s$$
+
+
+  val NOP = "b00000000000000000000000000010011".U(32.W) // NOP instruction
+
+  val pc = Module(new Pc())
+
+  // by default setting the save pc in fetch to false.
+  io.csrRegFile_csr_save_if_o := false.B
+  io.csrRegFile_csr_if_pc_o := 0.U
+  io.csrRegFile_csr_save_cause_o := false.B
+
+  // IF/ID registers
+  val if_id_pc_reg = Reg(SInt())
+  val if_id_pc4_reg = Reg(SInt())
+  val if_id_inst_reg = RegInit(NOP)
+
+  // checking if we have an interrupt to deal with
+  val handle_irq = io.csrRegFile_irq_pending_i && io.csrRegFile_csr_mstatus_mie_i
+
+  // if irq then stopping the fetch for getting new instruction because we need to jump to the trap handler
+  val halt_if = Wire(Bool())
+  halt_if := Mux(handle_irq, true.B, false.B)
+
+  // initializing the mtvec register
+  io.csrRegFile_csr_mtvec_init_o := Mux(io.core_init_mtvec_i, true.B, false.B)
+
+  // csr register file default outputs
+  io.csrRegFile_csr_save_if_o := false.B
+  io.csrRegFile_csr_save_cause_o := false.B
+  io.csrRegFile_exc_cause_o := Exc_Cause.EXC_CAUSE_INSN_ADDR_MISA
+  // Send the next pc value to the instruction memory
+  io.core_instr_addr_o := pc.io.in(13, 0).asUInt
+  // if device is ready to accept the request then send a valid signal to fetch from.
+  io.core_instr_req_o := Mux(io.core_instr_gnt_i, true.B, false.B)
+  // wait for valid signal to arrive indicating the fetched instruction is valid otherwise send NOP
+  val instr = Mux(io.core_instr_rvalid_i, io.core_instr_rdata_i, NOP)
+
+  when(!io.core_stall_i && !halt_if) {
+    // send the current pc value to the Decode stage
+    if_id_pc_reg := pc.io.out
+    // send the pc + 4 to the Decode stage
+    if_id_pc4_reg := pc.io.pc4
+  }
+
+  when(!io.core_stall_i && !halt_if) {
+    when(io.decode_hazardDetection_inst_forward_i === 1.U) {
+      if_id_inst_reg := io.decode_hazardDetection_inst_i
+      if_id_pc_reg := io.decode_hazardDetection_current_pc_i
+    }.otherwise {
+      // instead of sending the instruction data directly to the decode first see if
+      // the reset has been low for one cycle with the `started` val. If `started` is
+      // high it means the reset has not been low for one clock cycle so still send
+      // NOP instruction to the Decode otherwise send the received data from the ICCM.
+      //    inst_reg := Mux(started, NOP, io.instr_rdata_i)
+
+      if_id_inst_reg := instr
+
+    }
+  }
+
+
+  // Stopping the pc from updating since the pipeline has to be stalled. When the instruction is 0 and the next pc select
+  // is also 0 we have a condition where the PC needs to be stopped for UART. Used next pc select because there is
+  // a condition where the instruction is 0 but next pc select has some value for JALR instruction so the pc will not
+  // get updated.
+  //  when(io.inst_in === 0.U && io.ctrl_next_pc_sel === 0.U) {
+  //    pc.io.in := pc.io.out
+  //    //pc.io.stall := 1.U
+  //  } .otherwise {
+  when(!io.core_stall_i && !halt_if) {
+    when(io.decode_hazardDetection_pc_forward_i === 1.U) {
+      pc.io.in := io.decode_hazardDetection_pc_i
+    }.otherwise {
+      when(io.decode_ctrl_next_pc_sel_i === "b01".U) {
+        when(io.decode_branchLogic_output_i === 1.U && io.decode_ctrl_out_branch_i === 1.U) {
+          pc.io.in := io.decode_sb_imm_i
+          if_id_pc_reg := 0.S
+          if_id_pc4_reg := 0.S
+          if_id_inst_reg := NOP
+        }.otherwise {
+          pc.io.in := pc.io.pc4
+        }
+      }.elsewhen(io.decode_ctrl_next_pc_sel_i === "b10".U) {
+        pc.io.in := io.decode_uj_imm_i
+        if_id_pc_reg := 0.S
+        if_id_pc4_reg := 0.S
+        if_id_inst_reg := NOP
+      }.elsewhen(io.decode_ctrl_next_pc_sel_i === "b11".U) {
+        pc.io.in := io.decode_jalr_imm_i
+        if_id_pc_reg := 0.S
+        if_id_pc4_reg := 0.S
+        if_id_inst_reg := NOP
+      }.elsewhen(io.decode_mret_inst_i) {
+        pc.io.in := io.csrRegFile_csr_mepc_i.asSInt()
+        if_id_pc_reg := 0.S
+        if_id_pc4_reg := 0.S
+        if_id_inst_reg := NOP
+      }.otherwise {
+        pc.io.in := pc.io.pc4
+      }
+    }
+  }.elsewhen(!io.core_stall_i && halt_if) {
+    pc.io.in := Cat(io.csrRegFile_csr_mtvec_i(31, 8), 0.U(1.W), Exc_Cause.EXC_CAUSE_IRQ_EXTERNAL_M(4, 0), 0.U(2.W)).asSInt()
+    if_id_inst_reg := NOP // when halted pass NOP since we dont want to repeatedly send the current instruction as it will be executed twice
+    io.csrRegFile_csr_save_if_o := true.B
+    // Checking which pc to set in mepc. If the pc in had a branch instruction when interrupt came
+    // then save the calculated branch addres in mepc to return back to correct instruction after mret
+    // otherwise save pc's current value in mepc.
+    io.csrRegFile_csr_if_pc_o := Mux(io.decode_ctrl_next_pc_sel_i === "b01".U, io.decode_sb_imm_i.asUInt(),
+      Mux(io.decode_ctrl_next_pc_sel_i === "b10".U, io.decode_uj_imm_i.asUInt(),
+        Mux(io.decode_ctrl_next_pc_sel_i === "b11".U, io.decode_jalr_imm_i.asUInt(), pc.io.out.asUInt())))
+    io.csrRegFile_csr_save_cause_o := true.B
+    io.csrRegFile_exc_cause_o := Exc_Cause.EXC_CAUSE_IRQ_EXTERNAL_M
+  }
+    .otherwise {
+      pc.io.in := pc.io.out
+    }
+
+
+  io.decode_if_id_pc_o := if_id_pc_reg
+  io.decode_if_id_pc4_o := if_id_pc4_reg
+  io.decode_if_id_inst_o := if_id_inst_reg
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/Fetch_fifo.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/Fetch_fifo.scala
new file mode 100644
index 0000000..707e9d4
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/Fetch_fifo.scala
@@ -0,0 +1,208 @@
+import chisel3._
+import chisel3.util._
+//port chisel3.experimental._
+import java.awt.event.InputEvent
+import scala.util.matching.Regex
+import scala.collection.script.Reset
+//import chisel3.stage.ChiselStage
+
+
+class Fetch_fifo extends Module
+{
+  
+    val io = IO(new Bundle{
+        val clear_i = Input(Bool())
+ //     val rst_ni  = Input(Bool())
+
+        val in_valid_i = Input(Bool())
+        val in_addr_i  = Input(UInt(32.W))
+        val in_rdata_i = Input(UInt(32.W))
+        val in_err_i   = Input(Bool())
+        val out_ready_i= Input(Bool())
+
+        val busy_o      = Output(UInt(2.W))
+
+        val out_valid_o = Output(Bool())
+        val out_addr_o  = Output(UInt(32.W))
+        val out_addr_next_o = Output(UInt(32.W))
+        val out_rdata_o = Output(UInt(32.W))
+        val out_err_o   = Output(Bool())
+        val out_err_plus2 = Output(Bool())
+    }) 
+  
+    val NUM_REQS = 2
+    val DEPTH = NUM_REQS + 1
+
+    val rdata_d = Wire(Vec(3,UInt(32.W)))
+    val rdata_q = RegInit(VecInit(Seq.fill(3)(0.U(32.W))))
+
+    
+    val err_d   = Wire(Vec(DEPTH,Bool()))
+    val err_q   = RegInit(VecInit(Seq.fill(3)(0.U(1.W))))
+        
+  
+    val valid_d = Wire(Vec(DEPTH,Bool()))
+    val valid_q = RegInit(VecInit(Seq.fill(3)(0.U(1.W))))
+        
+    val lowest_free_entry = Wire(Vec(DEPTH,Bool()))
+    val valid_pushed, valid_popped = Wire(Vec(DEPTH,Bool()))
+
+    val entry_en = Wire(Vec(DEPTH,Bool()))
+
+    val pop_fifo = Wire(Bool())
+    val rdata, rdata_unaligned = Wire(UInt(32.W))
+    val err, err_unaligned, err_plus2 = Wire(Bool())
+    val valid, valid_unaligned = Wire(Bool())
+    val aligned_is_compressed, unaligned_is_compressed = Wire(Bool())
+    val addr_incr_two = Wire(Bool())
+    val instr_addr_next = Wire(UInt(32.W))
+    
+    val instr_addr_d = Wire(UInt(32.W))
+    val instr_addr_q = RegInit(0.U(32.W))
+
+    val instr_addr_en = Wire(Bool())
+    val unused_addr_in = Wire(Bool())
+
+    //***********Output Port***********//
+
+    rdata := Mux(valid_q(0).asBool(), rdata_q(0).asUInt, io.in_rdata_i)
+    err   := Mux(valid_q(0).asBool(), err_q(0).asBool(), io.in_err_i)
+    valid := (valid_q(0) | io.in_valid_i).asBool()
+
+    val rdq = Wire(UInt(16.W))
+    rdq := rdata_q(1).asUInt
+
+
+    rdata_unaligned := Mux(valid_q(1).asBool(), Cat(rdq.asUInt, rdata(31,16)), Cat(io.in_rdata_i(15,0), rdata(31,16)))
+
+    err_unaligned := Mux(valid_q(1).asBool(), ((err_q(1) & ~unaligned_is_compressed) | err_q(0)).asBool() , ((valid_q(0) & err_q(0)) | (io.in_err_i & (~valid_q(0) | ~unaligned_is_compressed))).asBool())
+
+    err_plus2 := Mux(valid_q(1).asBool(), (err_q(1) & ~err_q(1)).asBool(),( io.in_err_i & valid_q(0) & ~err_q(0)).asBool())
+
+    valid_unaligned := Mux(valid_q(1).asBool(), true.B , (valid_q(0) & io.in_valid_i).asBool())
+
+    unaligned_is_compressed := (rdata(17,16) =/= "b11".U) | err
+    aligned_is_compressed   := (rdata(1,0) =/= "b11".U) & ~err
+
+    //************* instruction aligner************//
+
+    when(io.out_addr_o(1).asBool()=== true.B)
+    {
+        io.out_rdata_o := rdata_unaligned
+        io.out_err_o   := err_unaligned
+        io.out_err_plus2 := err_plus2
+        when(unaligned_is_compressed === true.B)
+        {
+            io.out_valid_o := valid
+        }
+        .otherwise
+        {
+            io.out_valid_o := valid_unaligned
+        }
+    }
+    .otherwise
+    {
+        io.out_rdata_o := rdata
+        io.out_err_o   := err
+        io.out_err_plus2 := "b0".U
+        io.out_valid_o := valid
+    }
+    
+    //*************** instruuction address***********//
+
+    instr_addr_en := io.clear_i | (io.out_ready_i & io.out_valid_o)
+
+    addr_incr_two := Mux(instr_addr_q(1).asBool(), unaligned_is_compressed, aligned_is_compressed)
+
+    instr_addr_next:= instr_addr_q(31,1) + Cat("b0".U(29.W), ~addr_incr_two, addr_incr_two)
+
+    instr_addr_d := Mux(io.clear_i, io.in_addr_i(31,1), instr_addr_next)
+
+    when(instr_addr_en)
+    {
+        instr_addr_q := instr_addr_d.asUInt
+    }
+    .otherwise
+    {
+        instr_addr_q := DontCare
+    }
+
+    io.out_addr_next_o := Cat(instr_addr_next, "b1".U)
+    io.out_addr_o      := Cat(instr_addr_q, "b1".U)
+
+    unused_addr_in     := io.in_addr_i(0)
+
+    //************ Fifo status************//
+    val busy0 = Wire(UInt(1.W))
+    val busy1 = Wire(UInt(1.W))
+    busy0 := valid_q(1)
+    busy1 := valid_q(2)
+    io.busy_o := Cat(busy1,busy0)
+    
+    //****************Fifo Managemnet***********//
+
+    pop_fifo := io.out_ready_i & io.out_valid_o & (~aligned_is_compressed | io.out_addr_o(1))
+
+    for(i <- 0 to DEPTH-2)
+    {
+        when(i.asUInt === 0.U)
+        {
+            lowest_free_entry(i)  :=  ~valid_q(i).asBool()
+        }
+        .otherwise
+        {
+            lowest_free_entry(i)  := ~valid_q(i).asBool() & valid_q(0).asBool()
+        }
+
+        valid_pushed(i) := (io.in_valid_i & lowest_free_entry(i)) | valid_q(i)
+
+        valid_popped(i) := Mux(pop_fifo, valid_pushed(i+1), valid_pushed(i))
+
+        valid_d(i) := valid_popped(i) & ~io.clear_i
+
+        entry_en(i).asUInt:= (valid_pushed(i+1) & pop_fifo) | (io.in_valid_i & lowest_free_entry(i) & ~pop_fifo)
+        
+        rdata_d(i).asUInt := Mux(valid_q(i+1).asBool(), rdata_q(i+1).asUInt, io.in_rdata_i.asUInt)
+
+        err_d(i)    := Mux(valid_q(i+1).asBool(), err_q(i+1).asUInt, io.in_err_i.asUInt)
+    }
+
+    lowest_free_entry(DEPTH-1).asUInt := ~valid_q(DEPTH-1).asUInt & valid_q(DEPTH-2).asUInt
+    valid_pushed(DEPTH-1).asUInt      := (valid_q(DEPTH-1) | (io.in_valid_i & lowest_free_entry(DEPTH-1))).asBool()
+    valid_popped(DEPTH-1).asUInt      := Mux(pop_fifo, "b0".U, valid_pushed(DEPTH-1))
+    valid_d(DEPTH-1).asUInt           := valid_popped(DEPTH-1).asUInt & ~io.clear_i
+    entry_en(DEPTH-1).asUInt          := io.in_valid_i & lowest_free_entry(DEPTH-1)
+    rdata_d(DEPTH-1)                  := io.in_rdata_i
+    err_d(DEPTH-1).asUInt             := io.in_err_i
+
+
+    //*****************Fifo registers*****************//
+
+    when(reset.asBool())
+  {
+    valid_q := valid_d
+  }
+  .otherwise
+  {
+    valid_q := DontCare
+  }
+  
+    for(i <- 0 to DEPTH-2)
+    {
+        when(entry_en(i).asBool())
+        {
+            rdata_q(i) := rdata_d(i)
+            err_q(i)   := err_d(i)
+        }
+        .otherwise
+        {
+            rdata_q(i) := DontCare
+            err_q(i)   := DontCare
+        }
+    }
+    
+}
+
+
+
+//println((new ChiselStage).emitVerilog(new Fetch_fifo))
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/Foo.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/Foo.scala
new file mode 100644
index 0000000..3dc7892
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/Foo.scala
@@ -0,0 +1,15 @@
+package core
+
+import chisel3._
+import chisel3.util._
+//import chisel3.stage.ChiselStage
+
+
+class Foo extends Module {
+  val io = IO(new Bundle {
+    val in = Input(UInt(32.W))
+    val out = Output(UInt(32.W))
+  })
+
+  io.out := ShiftRegister(io.in, 3)
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/ForwardUnit.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/ForwardUnit.scala
new file mode 100644
index 0000000..8127ac9
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/ForwardUnit.scala
@@ -0,0 +1,53 @@
+package core
+
+import chisel3._
+
+class ForwardUnit extends Module {
+    val io = IO(new Bundle {
+        val EX_MEM_REGRD = Input(UInt(5.W))
+        val MEM_WB_REGRD = Input(UInt(5.W))
+        val ID_EX_REGRS1 = Input(UInt(5.W))
+        val ID_EX_REGRS2 = Input(UInt(5.W))
+        val ID_EX_inst_op = Input(UInt(7.W))
+        val EX_MEM_REGWR = Input(UInt(1.W))
+        val MEM_WB_REGWR = Input(UInt(1.W))
+        val forward_a    = Output(UInt(2.W))
+        val forward_b    = Output(UInt(2.W))
+    })
+    io.forward_a := "b00".U
+    io.forward_b := "b00".U
+
+    // EX HAZARD
+
+    // additional checking by opcode 0110111 because this is lui and it does not have any rs1, rs2 so we will not forward in that scenario
+    when(io.EX_MEM_REGWR === "b1".U && io.EX_MEM_REGRD =/= "b00000".U && (io.EX_MEM_REGRD === io.ID_EX_REGRS1) && (io.EX_MEM_REGRD === io.ID_EX_REGRS2) && io.ID_EX_inst_op =/= "b0110111".U) {
+        // if both the source register 1 and source register 2 are dependent on the destination
+        // register of previous instruction we forward the destination register value
+        // in both the operands of ALU for example: addi x2, x0, 2
+        //                                          add x2, x2, x2
+
+        io.forward_a := "b01".U
+        io.forward_b := "b01".U
+    } .elsewhen(io.EX_MEM_REGWR === "b1".U && io.EX_MEM_REGRD =/= "b00000".U && (io.EX_MEM_REGRD === io.ID_EX_REGRS2) && io.ID_EX_inst_op =/= "b0110111".U) {
+        io.forward_b := "b01".U
+        //io.forward_a := "b00".U
+    } .elsewhen(io.EX_MEM_REGWR === "b1".U && io.EX_MEM_REGRD =/= "b00000".U && (io.EX_MEM_REGRD === io.ID_EX_REGRS1) && io.ID_EX_inst_op =/= "b0110111".U) {
+        io.forward_a := "b01".U
+       // io.forward_b := "b00".U
+    }
+
+
+    // MEM HAZARD
+
+    when(io.MEM_WB_REGWR === "b1".U && io.MEM_WB_REGRD =/= "b00000".U && ~((io.EX_MEM_REGWR === "b1".U) && (io.EX_MEM_REGRD =/= "b00000".U) && (io.EX_MEM_REGRD === io.ID_EX_REGRS1) && (io.EX_MEM_REGRD === io.ID_EX_REGRS2)) && (io.MEM_WB_REGRD === io.ID_EX_REGRS1) && (io.MEM_WB_REGRD === io.ID_EX_REGRS2) && io.ID_EX_inst_op =/= "b0110111".U) {
+        io.forward_a := "b10".U
+        io.forward_b := "b10".U
+    } .elsewhen(io.MEM_WB_REGWR === "b1".U && io.MEM_WB_REGRD =/= "b00000".U && ~((io.EX_MEM_REGWR === "b1".U) && (io.EX_MEM_REGRD =/= "b00000".U) && (io.EX_MEM_REGRD === io.ID_EX_REGRS2)) && (io.MEM_WB_REGRD === io.ID_EX_REGRS2) && io.ID_EX_inst_op =/= "b0110111".U) {
+        io.forward_b := "b10".U
+        //io.forward_a := "b00".U
+    } .elsewhen(io.MEM_WB_REGWR === "b1".U && io.MEM_WB_REGRD =/= "b00000".U && ~((io.EX_MEM_REGWR === "b1".U) && (io.EX_MEM_REGRD =/= "b00000".U) && (io.EX_MEM_REGRD === io.ID_EX_REGRS1))  && (io.MEM_WB_REGRD === io.ID_EX_REGRS1) && io.ID_EX_inst_op =/= "b0110111".U) {
+        io.forward_a := "b10".U
+       // io.forward_b := "b00".U
+    }
+
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/ForwardUnitMem.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/ForwardUnitMem.scala
new file mode 100644
index 0000000..f1f620c
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/ForwardUnitMem.scala
@@ -0,0 +1,20 @@
+package core
+
+import chisel3._
+
+class ForwardUnitMem extends Module {
+  val io = IO(new Bundle {
+    val EX_MEM_RS2SEL = Input(UInt(5.W))
+    val MEM_WB_RDSEL = Input(UInt(5.W))
+    val EX_MEM_MEMWR = Input(UInt(1.W))
+    val MEM_WB_MEMRD = Input(UInt(1.W))
+    val forward = Output(UInt(1.W))
+  })
+
+  when(io.EX_MEM_MEMWR === "b1".U && io.MEM_WB_RDSEL =/= "b00000".U && io.MEM_WB_MEMRD === "b1".U && (io.EX_MEM_RS2SEL === io.MEM_WB_RDSEL)) {
+    io.forward := "b1".U
+  } .otherwise {
+    io.forward := "b0".U
+  }
+
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/HazardDetection.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/HazardDetection.scala
new file mode 100644
index 0000000..488bf3a
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/HazardDetection.scala
@@ -0,0 +1,65 @@
+package core
+
+import chisel3._
+
+class HazardDetection extends Module {
+  val io = IO(new Bundle {
+    val IF_ID_INST = Input(UInt(32.W))
+    val ID_EX_MEMREAD = Input(UInt(1.W))
+    val ID_EX_REGRD = Input(UInt(5.W))
+    val pc_in = Input(SInt(32.W))
+    val current_pc = Input(SInt(32.W))
+    val IF_ID_MEMREAD = Input(UInt(1.W))
+    val inst_forward = Output(UInt(1.W))
+    val pc_forward = Output(UInt(1.W))
+    val ctrl_forward = Output(UInt(1.W))
+    val inst_out = Output(UInt(32.W))
+    val pc_out = Output(SInt(32.W))
+    val current_pc_out = Output(SInt(32.W))
+  })
+  val rs1_sel = io.IF_ID_INST(19, 15)
+  val rs2_sel = io.IF_ID_INST(24, 20)
+  when(io.IF_ID_MEMREAD === "b1".U)
+  {
+      when(io.ID_EX_MEMREAD === "b1".U && (io.ID_EX_REGRD === rs1_sel))
+      {
+         createStall()
+      } 
+      .otherwise 
+      {
+         createNoStall()
+      }
+  }
+  .otherwise
+  {
+    when(io.ID_EX_MEMREAD === "b1".U && ((io.ID_EX_REGRD === rs1_sel) || (io.ID_EX_REGRD === rs2_sel)))
+     {
+        createStall()
+     } 
+     .otherwise 
+     {
+        createNoStall()
+     }
+  }
+  
+
+  def createStall(): Unit =
+  {
+      io.inst_forward := 1.U
+      io.pc_forward := 1.U
+      io.ctrl_forward := 1.U
+      io.inst_out := io.IF_ID_INST
+      io.pc_out := io.pc_in
+      io.current_pc_out := io.current_pc
+  }
+  def createNoStall(): Unit =
+  {
+    io.inst_forward := 0.U
+    io.pc_forward := 0.U
+    io.ctrl_forward := 0.U
+    io.inst_out := io.IF_ID_INST  // Doesn't matter if we pass the old instruction forward because it won't be selected by the mux
+    io.pc_out := io.pc_in         // Doesn't matter if we pass the old pc value forward because it won't be selected by the mux
+    io.current_pc_out := io.current_pc
+
+}
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
new file mode 100644
index 0000000..bbeaaa1
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/ID_EX.scala
@@ -0,0 +1,167 @@
+package core
+
+import chisel3._
+
+class ID_EX extends Module {
+    val io = IO(new Bundle {
+        val pc_in = Input(SInt(32.W))
+        val pc4_in = Input(SInt(32.W))
+        val rs1_sel_in = Input(UInt(5.W))
+        val rs2_sel_in = Input(UInt(5.W))
+        val rs1_in = Input(SInt(32.W))
+        val rs2_in = Input(SInt(32.W))
+        val imm = Input(SInt(32.W))
+        val rd_sel_in = Input(UInt(5.W))
+        val func3_in = Input(UInt(3.W))
+        val func7_in = Input(UInt(7.W))
+        val ctrl_MemWr_in = Input(UInt(1.W))
+        val ctrl_MemRd_in = Input(UInt(1.W))
+        val ctrl_Branch_in = Input(UInt(1.W))
+        val ctrl_CsrWen_in = Input(Bool())
+        val ctrl_RegWr_in = Input(UInt(1.W))
+        val ctrl_MemToReg_in = Input(UInt(1.W))
+        val ctrl_AluOp_in = Input(UInt(4.W))
+        val ctrl_OpA_sel_in = Input(UInt(2.W))
+        val ctrl_OpB_sel_in = Input(UInt(1.W))
+        val ctrl_nextPc_sel_in = Input(UInt(2.W))
+        val inst_op_in = Input(UInt(7.W))
+//        val csr_op_in = Input(UInt(2.W))
+        val csr_data_i = Input(UInt(32.W))
+      //  val M_extension_enabled_in = Input(UInt(1.W))
+
+        val stall = Input(UInt(1.W))
+
+        val pc_out = Output(SInt(32.W))
+        val pc4_out = Output(SInt(32.W))
+        val rs1_out = Output(SInt(32.W))
+        val rs2_out = Output(SInt(32.W))
+        val imm_out = Output(SInt(32.W))
+        val func3_out = Output(UInt(3.W))
+        val func7_out = Output(UInt(7.W))
+        val inst_op_out = Output(UInt(7.W))
+        val rd_sel_out = Output(UInt(5.W))
+        val rs1_sel_out = Output(UInt(5.W))
+        val rs2_sel_out = Output(UInt(5.W))
+        val ctrl_MemWr_out = Output(UInt(1.W))
+        val ctrl_MemRd_out = Output(UInt(1.W))
+        val ctrl_Branch_out = Output(UInt(1.W))
+        val ctrl_RegWr_out = Output(UInt(1.W))
+        val ctrl_CsrWen_out = Output(Bool())
+        val ctrl_MemToReg_out = Output(UInt(1.W))
+        val ctrl_AluOp_out = Output(UInt(4.W))
+        val ctrl_OpA_sel_out = Output(UInt(2.W))
+        val ctrl_OpB_sel_out = Output(UInt(1.W))
+        val ctrl_nextPc_sel_out = Output(UInt(2.W))
+//        val csr_op_o = Output(UInt(2.W))
+        val csr_data_o = Output(UInt(32.W))
+      //  val M_extension_enabled = Output(UInt(1.W))
+    })
+    val pc_reg = RegInit(0.S(32.W))
+    val pc4_reg = RegInit(0.S(32.W))
+    val rs1_reg = RegInit(0.S(32.W))
+    val rs2_reg = RegInit(0.S(32.W))
+    val imm_reg = RegInit(0.S(32.W))
+    val rd_sel_reg = RegInit(0.U(5.W))
+    val rs1_sel_reg = RegInit(0.U(5.W))
+    val rs2_sel_reg = RegInit(0.U(5.W))
+    val func3_reg = RegInit(0.U(3.W))
+    val func7_reg = RegInit(0.U(7.W))
+    val inst_op_reg = RegInit(0.U(7.W))
+//    val csr_op_reg = RegInit(0.U(2.W))
+    val csr_data_reg = RegInit(0.U(32.W))
+
+    val ctrl_MemWr_reg = RegInit(0.U(1.W))
+    val ctrl_MemRd_reg = RegInit(0.U(1.W))
+    val ctrl_Branch_reg = RegInit(0.U(1.W))
+    val ctrl_RegWr_reg = RegInit(0.U(1.W))
+    val ctrl_CsrWen_reg = RegInit(false.B)
+    val ctrl_MemToReg_reg = RegInit(0.U(1.W))
+    val ctrl_AluOp_reg = RegInit(0.U(4.W))
+    val ctrl_OpA_sel_reg = RegInit(0.U(2.W))
+    val ctrl_OpB_sel_reg = RegInit(0.U(1.W))
+    val ctrl_nextPc_sel_reg = RegInit(0.U(1.W))
+  //  val M_extension_reg     = RegInit(0.U(1.W))
+
+    when(io.stall =/= 1.U) {
+        pc_reg := io.pc_in
+        pc4_reg := io.pc4_in
+        rs1_reg := io.rs1_in
+        rs2_reg := io.rs2_in
+        imm_reg := io.imm
+        csr_data_reg := io.csr_data_i
+        rd_sel_reg := io.rd_sel_in
+        rs1_sel_reg := io.rs1_sel_in
+        rs2_sel_reg := io.rs2_sel_in
+        func3_reg := io.func3_in
+        func7_reg := io.func7_in
+        inst_op_reg := io.inst_op_in
+        // Storing Control state in the registers
+        ctrl_MemWr_reg := io.ctrl_MemWr_in
+        ctrl_MemRd_reg := io.ctrl_MemRd_in
+        ctrl_Branch_reg := io.ctrl_Branch_in
+        ctrl_RegWr_reg := io.ctrl_RegWr_in
+        ctrl_CsrWen_reg := io.ctrl_CsrWen_in
+        ctrl_MemToReg_reg := io.ctrl_MemToReg_in
+        ctrl_AluOp_reg := io.ctrl_AluOp_in
+        ctrl_OpA_sel_reg := io.ctrl_OpA_sel_in
+        ctrl_OpB_sel_reg := io.ctrl_OpB_sel_in
+        ctrl_nextPc_sel_reg := io.ctrl_nextPc_sel_in
+//        csr_op_reg := io.csr_op_in
+     //   M_extension_reg := io.M_extension_enabled_in
+
+
+        io.pc_out := pc_reg
+        io.pc4_out := pc4_reg
+        io.rs1_out := rs1_reg
+        io.rs2_out := rs2_reg
+        io.csr_data_o := csr_data_reg
+        io.imm_out := imm_reg
+        io.rd_sel_out := rd_sel_reg
+        io.rs1_sel_out := rs1_sel_reg
+        io.rs2_sel_out := rs2_sel_reg
+        io.func3_out := func3_reg
+        io.func7_out := func7_reg
+        io.inst_op_out := inst_op_reg
+
+        io.ctrl_MemWr_out := ctrl_MemWr_reg
+        io.ctrl_MemRd_out := ctrl_MemRd_reg
+        io.ctrl_Branch_out := ctrl_Branch_reg
+        io.ctrl_RegWr_out := ctrl_RegWr_reg
+        io.ctrl_CsrWen_out := ctrl_CsrWen_reg
+        io.ctrl_MemToReg_out := ctrl_MemToReg_reg
+        io.ctrl_AluOp_out := ctrl_AluOp_reg
+        io.ctrl_OpA_sel_out := ctrl_OpA_sel_reg
+        io.ctrl_OpB_sel_out := ctrl_OpB_sel_reg
+        io.ctrl_nextPc_sel_out := ctrl_nextPc_sel_reg
+//        io.csr_op_o := csr_op_reg
+    //     io.M_extension_enabled := M_extension_reg
+        
+   } .otherwise {
+        io.pc_out := pc_reg
+        io.pc4_out := pc4_reg
+        io.rs1_out := rs1_reg
+        io.rs2_out := rs2_reg
+        io.csr_data_o := csr_data_reg
+        io.imm_out := imm_reg
+        io.rd_sel_out := rd_sel_reg
+        io.rs1_sel_out := rs1_sel_reg
+        io.rs2_sel_out := rs2_sel_reg
+        io.func3_out := func3_reg
+        io.func7_out := func7_reg
+        io.inst_op_out := inst_op_reg
+//        io.csr_op_o := csr_op_reg
+
+        io.ctrl_MemWr_out := ctrl_MemWr_reg
+        io.ctrl_MemRd_out := ctrl_MemRd_reg
+        io.ctrl_Branch_out := ctrl_Branch_reg
+        io.ctrl_RegWr_out := ctrl_RegWr_reg
+        io.ctrl_CsrWen_out := ctrl_CsrWen_reg
+        io.ctrl_MemToReg_out := ctrl_MemToReg_reg
+        io.ctrl_AluOp_out := ctrl_AluOp_reg
+        io.ctrl_OpA_sel_out := ctrl_OpA_sel_reg
+        io.ctrl_OpB_sel_out := ctrl_OpB_sel_reg
+        io.ctrl_nextPc_sel_out := ctrl_nextPc_sel_reg
+        //io.M_extension_enabled := M_extension_reg
+    }
+
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/ImmediateGeneration.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/ImmediateGeneration.scala
new file mode 100644
index 0000000..ba505b8
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/ImmediateGeneration.scala
@@ -0,0 +1,62 @@
+package core
+
+import chisel3._
+import chisel3.util.Cat
+import chisel3.util.Fill
+
+class ImmediateGeneration extends Module {
+    val io = IO(new Bundle {
+        val instruction = Input(UInt(32.W))
+        val pc = Input(SInt(32.W))
+        val s_imm = Output(SInt(32.W))
+        val sb_imm = Output(SInt(32.W))
+        val u_imm = Output(SInt(32.W))
+        val uj_imm = Output(SInt(32.W))
+        val i_imm = Output(SInt(32.W))
+    })
+    // ----- Calculating S-Immediate ------ //
+
+    val s_lower_half = io.instruction(11,7)     // bits 7-11 from 32 bits
+    val s_upper_half = io.instruction(31,25)    // bits 25-31 from 32 bits
+    var s_imm_12 = Cat(s_upper_half, s_lower_half)    // merging immediates together to form 12 bits
+    val s_imm_32 = Cat(Fill(20, s_imm_12(11)), s_imm_12)   // sign extending 12 bits to 32 bits and merging the 12 bit immediate 
+    io.s_imm := s_imm_32.asSInt
+
+
+    // ----- Calculating SB-Immediate ------ //
+
+    val sb_lower_half = io.instruction(11,8)
+    val sb_upper_half = io.instruction(30, 25)
+    val sb_11thbit = io.instruction(7)
+    val sb_12thbit = io.instruction(31)
+    val sb_imm_13 = Cat(sb_12thbit, sb_11thbit, sb_upper_half, sb_lower_half, 0.S)
+    val sb_imm_32 = Cat(Fill(19, sb_imm_13(12)), sb_imm_13).asSInt
+    io.sb_imm := sb_imm_32 + io.pc
+
+
+    // ----- Calculating U-Immediate ------ //
+
+    val u_imm_20 = io.instruction(31,12)
+    var u_imm_32 = Cat(Fill(12, u_imm_20(19)), u_imm_20)
+    // val shift_const = 12.S
+    val u_imm_32_shifted = u_imm_32 << 12.U
+    io.u_imm := u_imm_32_shifted.asSInt
+
+
+    // ----- Calculating UJ-Immediate ----- //
+    
+    val uj_lower_half = io.instruction(30, 21)
+    val uj_11thbit = io.instruction(20)
+    val uj_upper_half = io.instruction(19, 12)
+    val uj_20thbit = io.instruction(31)
+    val uj_imm_21 = Cat(uj_20thbit, uj_upper_half, uj_11thbit, uj_lower_half, 0.S)
+    val uj_imm_32 = Cat(Fill(11, uj_imm_21(20)), uj_imm_21).asSInt
+    io.uj_imm := uj_imm_32 + io.pc
+
+
+    // ----- Calculating I-Immediate ----- //
+
+    val i_imm_12 = io.instruction(31, 20)
+    val i_imm_32 = Cat(Fill(20, i_imm_12(11)), i_imm_12)
+    io.i_imm := i_imm_32.asSInt
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/InstructionTypeDecode.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/InstructionTypeDecode.scala
new file mode 100644
index 0000000..98515f3
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/InstructionTypeDecode.scala
@@ -0,0 +1,97 @@
+package core
+
+import chisel3._
+
+class InstructionTypeDecode extends Module {
+    val io = IO(new Bundle {
+     //   val enable_M_extension = Input(UInt(1.W))
+        val func3 = Input(UInt(3.W))
+        val func7  = Input(UInt(7.W))
+        val opcode = Input(UInt(7.W))
+        val r_type = Output(UInt(1.W))
+        val load_type = Output(UInt(1.W))
+        val s_type = Output(UInt(1.W))
+        val sb_type = Output(UInt(1.W))
+        val i_type = Output(UInt(1.W))
+        val jalr_type = Output(UInt(1.W))
+        val jal_type = Output(UInt(1.W))
+        val lui_type = Output(UInt(1.W))
+        val Auipc    = Output(UInt(1.W))
+        val multiply = Output(UInt(1.W))
+        val csr_imm_type = Output(UInt(1.W))
+        val csr_type = Output(UInt(1.W))
+        val csr_op = Output(UInt(2.W))
+    })
+        default_signals()
+
+    when(io.opcode === "b0110011".U ) 
+    {
+        when(io.func7 === "b000001".U)
+        {
+          io.multiply := 1.U
+          io.r_type   := 0.U
+       }
+        .otherwise
+        {
+          io.r_type := 1.U
+        }
+    } 
+    .elsewhen(io.opcode === "b0000011".U) {
+        io.load_type := 1.U
+    } .elsewhen(io.opcode === "b0100011".U) {        
+        io.s_type := 1.U        
+    } .elsewhen(io.opcode === "b1100011".U) {        
+        io.sb_type := 1.U        
+    } .elsewhen(io.opcode === "b0010011".U) {        
+        io.i_type := 1.U        
+    } .elsewhen(io.opcode === "b1100111".U) {
+        io.jalr_type := 1.U
+    } .elsewhen(io.opcode === "b1101111".U) {
+        io.jal_type := 1.U
+    } .elsewhen(io.opcode === "b0110111".U) {
+        io.lui_type := 1.U
+    }
+     .elsewhen(io.opcode === "b0010111".U) {
+        io.Auipc := 1.U
+    } .elsewhen(io.opcode === "b1110011".U && io.func3 === "b001".U) {
+        io.csr_type := 1.U
+        io.csr_op := "b01".U
+    } .elsewhen(io.opcode === "b1110011".U && io.func3 === "b010".U) {
+        io.csr_type := 1.U
+        io.csr_op := "b10".U
+    } .elsewhen(io.opcode === "b1110011".U && io.func3 === "b011".U) {
+        io.csr_type := 1.U
+        io.csr_op := "b11".U
+    } .elsewhen(io.opcode === "b1110011".U && io.func3 === "b101".U) {
+        io.csr_imm_type := 1.U
+        io.csr_op := "b01".U
+    } .elsewhen(io.opcode === "b1110011".U && io.func3 === "b110".U) {
+        io.csr_imm_type := 1.U
+        io.csr_op := "b10".U
+    } .elsewhen(io.opcode === "b1110011".U && io.func3 === "b111".U) {
+        io.csr_imm_type := 1.U
+        io.csr_op := "b11".U
+    }
+     .otherwise 
+     {
+        default_signals()
+    }
+
+    def default_signals(): Unit = 
+    {
+        io.r_type := 0.U
+        io.load_type := 0.U
+        io.s_type := 0.U
+        io.sb_type := 0.U
+        io.i_type := 0.U
+        io.jalr_type := 0.U
+        io.jal_type := 0.U
+        io.lui_type := 0.U
+        io.Auipc    := 0.U
+        io.multiply := 0.U
+        io.csr_type := 0.U
+        io.csr_imm_type := 0.U
+        io.csr_op := 0.U
+    }
+
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/Jalr.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/Jalr.scala
new file mode 100644
index 0000000..6988bf0
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/Jalr.scala
@@ -0,0 +1,15 @@
+package core
+
+import chisel3._
+
+class Jalr extends Module {
+    val io = IO(new Bundle {
+            val input_a = Input(SInt(32.W))
+            val input_b = Input(SInt(32.W))
+            val output = Output(SInt(32.W))
+    })
+
+    val sum = io.input_a + io.input_b
+    io.output := sum & 4294967294L.S 
+
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/Load_unit.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/Load_unit.scala
new file mode 100644
index 0000000..10dfd92
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/Load_unit.scala
@@ -0,0 +1,158 @@
+package core
+import chisel3._
+import chisel3.util.Cat
+import chisel3.util.Fill
+class Load_unit extends Module {
+    val io=IO(new Bundle{
+        val func3 = Input(UInt(3.W))
+        val en = Input(Bool())
+        val data_offset = Input(UInt(2.W))
+        val memData  = Input(SInt(32.W))
+        val LoadData = Output(SInt(32.W))
+})
+    val lb = io.memData(7,0)
+    val lh = io.memData(15,0)
+    val zero = 0.U
+
+    /** Visualize memory as follows
+     *      11          10        9         8  -> address
+     * | d[31:24] | d[23:16] | d[15:8] | d[7:0] |
+     *      7           6         5         4  -> address
+     * | d[31:24] | d[23:16] | d[15:8] | d[7:0] |
+     *      3           2         1         0  -> address
+     * | d[31:24] | d[23:16] | d[15:8] | d[7:0] |  */
+
+    when(io.en) {
+        when(io.func3 === "b000".U) {
+            // load byte
+            when(io.data_offset === "b00".U) {
+                // addressing memory with 0,4,8...
+                io.LoadData := Cat(Fill(24,io.memData(7)),io.memData(7,0)).asSInt
+            } .elsewhen(io.data_offset === "b01".U) {
+                // addressing memory with 1,5,9...
+                io.LoadData := Cat(Fill(24, io.memData(15)),io.memData(15,8)).asSInt()
+            } .elsewhen(io.data_offset === "b10".U) {
+                // addressing memory with 2,6,10...
+                io.LoadData := Cat(Fill(24, io.memData(23)),io.memData(23,16)).asSInt()
+            } .elsewhen(io.data_offset === "b11".U) {
+                // addressing memory with 3,7,11...
+                io.LoadData := Cat(Fill(24, io.memData(31)),io.memData(31,24)).asSInt()
+            } .otherwise {
+                // this condition would never occur but using to avoid Chisel generating VOID errors
+                io.LoadData := DontCare
+            }
+        } .elsewhen(io.func3 === "b001".U) {
+            // load halfword
+            when(io.data_offset === "b00".U) {
+                // addressing memory with 0,4,8...
+                io.LoadData := Cat(Fill(16,io.memData(15)),io.memData(15,0)).asSInt
+            } .elsewhen(io.data_offset === "b01".U) {
+                // addressing memory with 1,5,9...
+                io.LoadData := Cat(Fill(16, io.memData(23)),io.memData(23,8)).asSInt()
+            } .elsewhen(io.data_offset === "b10".U) {
+                // addressing memory with 2,6,10...
+                io.LoadData := Cat(Fill(16, io.memData(31)),io.memData(31,16)).asSInt()
+            } .elsewhen(io.data_offset === "b11".U) {
+                // addressing memory with 3,7,11...
+                /** xxxxxxxxxxx ADDRESS MIS-ALIGNMENT ALERT xxxxxxxxx */
+                // TODO: Stop such misaligned addresses from the software ide.
+                // this is misaligned access because we want to read two bytes and addressing
+                // the memory in this location gives us just a byte. Right now we don't handle
+                // such mis-alignments and just read the byte and sign extend it with 000s
+                // to ignore the other byte that must have been read from the next memory row.
+                io.LoadData := Cat(Fill(24, 0.U),io.memData(31,24)).asSInt()
+            } .otherwise {
+                // this condition would never occur but using to avoid Chisel generating VOID errors
+                io.LoadData := DontCare
+            }
+        } .elsewhen(io.func3 === "b110".U) {
+            //  load word unsigned
+            /** TODO: Figure out whether this instruction is supported by the RISC-V Spec or not and then implement the functionality
+             *  The RISC-V Green Card shows this instruction as "lwu"
+             *  But cannot find it in the RISC-V spec and Venus does not support it as well */
+            io.LoadData := io.memData
+        } .elsewhen(io.func3 === "b100".U) {
+            // load byte unsigned (LBU)
+            when(io.data_offset === "b00".U) {
+                // addressing memory with 0,4,8...
+                io.LoadData := Cat(Fill(24,0.U),io.memData(7,0)).asSInt
+            } .elsewhen(io.data_offset === "b01".U) {
+                // addressing memory with 1,5,9...
+                io.LoadData := Cat(Fill(24, 0.U),io.memData(15,8)).asSInt()
+            } .elsewhen(io.data_offset === "b10".U) {
+                // addressing memory with 2,6,10...
+                io.LoadData := Cat(Fill(24, 0.U),io.memData(23,16)).asSInt()
+            } .elsewhen(io.data_offset === "b11".U) {
+                // addressing memory with 3,7,11...
+                io.LoadData := Cat(Fill(24, 0.U),io.memData(31,24)).asSInt()
+            } .otherwise {
+                // this condition would never occur but using to avoid Chisel generating VOID errors
+                io.LoadData := DontCare
+            }
+        } .elsewhen(io.func3 === "b101".U) {
+            // load halfword unsigned
+            when(io.data_offset === "b00".U) {
+                // addressing memory with 0,4,8...
+                io.LoadData := Cat(Fill(16, 0.U),io.memData(15,0)).asSInt
+            } .elsewhen(io.data_offset === "b01".U) {
+                // addressing memory with 1,5,9...
+                io.LoadData := Cat(Fill(16, 0.U),io.memData(23,8)).asSInt()
+            } .elsewhen(io.data_offset === "b10".U) {
+                // addressing memory with 2,6,10...
+                io.LoadData := Cat(Fill(16, 0.U),io.memData(31,16)).asSInt()
+            } .elsewhen(io.data_offset === "b11".U) {
+                // addressing memory with 3,7,11...
+                /** xxxxxxxxxxx ADDRESS MIS-ALIGNMENT ALERT xxxxxxxxx */
+                // TODO: Stop such misaligned addresses from the software ide.
+                // this is misaligned access because we want to read two bytes and addressing
+                // the memory in this location gives us just a byte. Right now we don't handle
+                // such mis-alignments and just read the byte and sign extend it with 000s
+                // to ignore the other byte that must have been read from the next memory row.
+                io.LoadData := Cat(Fill(24, 0.U),io.memData(31,24)).asSInt()
+            } .otherwise {
+                // this condition would never occur but using to avoid Chisel generating VOID errors
+                io.LoadData := DontCare
+            }
+        } .elsewhen(io.func3 === "b010".U) {
+            // load word
+            when(io.data_offset === "b00".U) {
+                // addressing memory with 0,4,8...
+                io.LoadData := io.memData(31,0).asSInt()
+            } .elsewhen(io.data_offset === "b01".U) {
+                // addressing memory with 1,5,9...
+                /** xxxxxxxxxxx ADDRESS MIS-ALIGNMENT ALERT xxxxxxxxx */
+                // TODO: Stop such misaligned addresses from the software ide.
+                // this is misaligned access because we want to read full word and addressing
+                // the memory in this location would at max give us three bytes and the fourth
+                // one would need to be read from the next memory row. Right now we don't handle
+                // such mis-alignments and just read the available three bytes with sign extending
+                // the 000s for the remaining fourth byte.
+                io.LoadData := Cat(Fill(8, 0.U),io.memData(31,8)).asSInt()
+            } .elsewhen(io.data_offset === "b10".U) {
+                // addressing memory with 2,6,10...
+                /** xxxxxxxxxxx ADDRESS MIS-ALIGNMENT ALERT xxxxxxxxx */
+                // TODO: Stop such misaligned addresses from the software ide.
+                // another misaligned access because now we have just two bytes available to be read.
+                // just reading the two bytes and sign extending the other two bytes with 000s.
+                io.LoadData := Cat(Fill(16, 0.U),io.memData(31,16)).asSInt()
+            } .elsewhen(io.data_offset === "b11".U) {
+                // addressing memory with 3,7,11...
+                /** xxxxxxxxxxx ADDRESS MIS-ALIGNMENT ALERT xxxxxxxxx */
+                // TODO: Stop such misaligned addresses from the software ide.
+                // another misaligned access because now we have just one byte available to be read.
+                // just reading the one byte and sign extending the other three bytes with 000s.
+                io.LoadData := Cat(Fill(24, 0.U), io.memData(31,24)).asSInt()
+            } .otherwise {
+                // this condition would never occur but using to avoid Chisel generating VOID errors
+                io.LoadData := DontCare
+            }
+        } .otherwise {
+            // unknown func3 bits
+            io.LoadData := DontCare
+        }
+    } .otherwise {
+        io.LoadData := DontCare
+    }
+
+    
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/MEM_WB.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/MEM_WB.scala
new file mode 100644
index 0000000..f31cd1a
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/MEM_WB.scala
@@ -0,0 +1,88 @@
+package core
+
+import chisel3._
+
+class MEM_WB extends Module {
+    val io = IO(new Bundle {
+        val ctrl_RegWr_in = Input(UInt(1.W))
+        val ctrl_CsrWen_in = Input(Bool())
+        val ctrl_MemToReg_in = Input(UInt(1.W))
+        val rd_sel_in = Input(UInt(5.W))
+        val ctrl_MemRd_in = Input(UInt(1.W))
+        val dmem_data_in = Input(SInt(32.W))
+        val alu_in = Input(SInt(32.W))
+//        val csr_addr_in = Input(SInt(32.W))
+//        val csr_op_in = Input(UInt(2.W))
+        val csr_data_in = Input(UInt(32.W))
+
+        val stall = Input(UInt(1.W))
+
+        val ctrl_RegWr_out = Output(UInt(1.W))
+        val ctrl_CsrWen_out = Output(Bool())
+        val ctrl_MemToReg_out = Output(UInt(1.W))
+        val ctrl_MemRd_out = Output(UInt(1.W))
+        val rd_sel_out = Output(UInt(5.W))
+        val dmem_data_out = Output(SInt(32.W))
+        val alu_output = Output(SInt(32.W))
+//        val csr_addr_out = Output(SInt(32.W))
+//        val csr_op_out = Output(UInt(2.W))
+        val csr_data_out = Output(UInt(32.W))
+    })
+
+    val reg_regWr = RegInit(0.U(1.W))
+
+    val reg_csrWen = RegInit(false.B)
+
+    val reg_memToReg = RegInit(0.U(1.W))
+
+    val reg_memRd = RegInit(0.U(1.W))
+
+    val reg_rdSel = RegInit(0.U(5.W))
+
+    val reg_dataMem_data = RegInit(0.S(32.W))
+
+    val reg_alu_output = RegInit(0.S(32.W))
+
+//    val reg_csr_addr = RegInit(0.S(32.W))
+
+//    val reg_csr_op = RegInit(0.U(2.W))
+
+    val reg_csr_data = RegInit(0.U(32.W))
+
+    when(io.stall =/= 1.U) {
+        reg_regWr := io.ctrl_RegWr_in
+        reg_csrWen := io.ctrl_CsrWen_in
+        reg_memToReg := io.ctrl_MemToReg_in
+        reg_memRd := io.ctrl_MemRd_in
+        reg_rdSel := io.rd_sel_in
+        reg_dataMem_data := io.dmem_data_in
+        reg_alu_output := io.alu_in
+//        reg_csr_addr := io.csr_addr_in
+//        reg_csr_op := io.csr_op_in
+        reg_csr_data := io.csr_data_in
+
+        io.ctrl_MemToReg_out := reg_memToReg
+        io.ctrl_RegWr_out := reg_regWr
+        io.ctrl_CsrWen_out := reg_csrWen
+        io.ctrl_MemRd_out := reg_memRd
+        io.rd_sel_out := reg_rdSel
+        io.dmem_data_out := reg_dataMem_data
+        io.alu_output := reg_alu_output
+//        io.csr_addr_out := reg_csr_addr
+//        io.csr_op_out := reg_csr_op
+        io.csr_data_out := reg_csr_data
+    } .otherwise {
+        io.ctrl_MemToReg_out := reg_memToReg
+        io.ctrl_RegWr_out := reg_regWr
+        io.ctrl_CsrWen_out := reg_csrWen
+        io.ctrl_MemRd_out := reg_memRd
+        io.rd_sel_out := reg_rdSel
+        io.dmem_data_out := reg_dataMem_data
+        io.alu_output := reg_alu_output
+//        io.csr_addr_out := reg_csr_addr
+//        io.csr_op_out := reg_csr_op
+        io.csr_data_out := reg_csr_data
+    }
+
+
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
new file mode 100644
index 0000000..24e870d
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/MemoryStage.scala
@@ -0,0 +1,297 @@
+package core
+
+import chisel3._
+import chisel3.util.Cat
+
+class MemoryStage extends Module {
+  val io = IO(new Bundle {
+    val EX_MEM_alu_output = Input(SInt(32.W))
+    val EX_MEM_rd_sel = Input(UInt(5.W))
+    val EX_MEM_RegWr = Input(UInt(1.W))
+    val EX_MEM_CsrWe = Input(Bool())
+    val EX_MEM_MemRd = Input(UInt(1.W))
+    val EX_MEM_MemToReg = Input(UInt(1.W))
+    val EX_MEM_MemWr = Input(UInt(1.W))
+    val EX_MEM_rs2 = Input(SInt(32.W))
+    val func3      = Input(UInt(3.W))
+//    val EX_MEM_csr_addr = Input(SInt(32.W))
+//    val EX_MEM_csr_op = Input(UInt(2.W))
+    val EX_MEM_csr_data = Input(UInt(32.W))
+
+    val data_gnt_i   = Input(Bool())
+    val data_rvalid_i= Input(Bool())
+    val data_rdata_i = Input(SInt(32.W))
+    val data_req_o   = Output(Bool())
+    val data_be_o  = Output(Vec(4, Bool()))
+    val ctrl_MemWr_out = Output(UInt(1.W)) // data_we_o
+    val data_wdata_o = Output(Vec(4, SInt(8.W))) // data_wdata_o
+    val memAddress = Output(SInt(32.W)) // data_addr_o
+    val data_out   = Output(SInt(32.W))
+
+
+    val alu_output = Output(SInt(32.W))
+    val rd_sel_out = Output(UInt(5.W))
+    val ctrl_RegWr_out = Output(UInt(1.W))
+    val ctrl_CsrWen_out = Output(Bool())
+    val ctrl_MemRd_out = Output(UInt(1.W))
+    val ctrl_MemToReg_out = Output(UInt(1.W))
+//    val csr_addr_out = Output(SInt(32.W))
+//    val csr_op_out = Output(UInt(2.W))
+    val csr_data_out = Output(UInt(32.W))
+
+    val stall = Output(Bool())
+  })
+
+  val load_unit = Module(new Load_unit())
+
+  val data_offset = io.EX_MEM_alu_output(1,0)
+  val data_wdata = Wire(Vec(4, SInt(8.W)))
+
+
+  // Stalling the pipeline as soon as we get a load or store instruction
+  // and the data received from memory is not valid.
+  // As soon as we get a valid data from memory we pull down the stall.
+
+  io.stall := (io.EX_MEM_MemWr === 1.U || io.EX_MEM_MemRd === 1.U) && !io.data_rvalid_i
+
+  /** |||||||||||||||||||||||||||||| INITIALIZING LOAD UNIT ||||||||||||||||||||||||||||||| */
+
+  /** ******************************************START****************************************************** */
+  load_unit.io.func3 := io.func3
+  load_unit.io.memData := io.data_rdata_i
+  load_unit.io.data_offset := data_offset
+  load_unit.io.en := false.B
+
+  /** ******************************************END****************************************************** */
+
+
+
+  /** |||||||||||||||||||||||||||||| SETTING MASK BITS FOR WRITE OPERATIONS ||||||||||||||||||||||||||||||| */
+
+  /** ******************************************START****************************************************** */
+
+  /** Visualize memory as follows
+   *      11          10        9         8  -> address
+   * | d[31:24] | d[23:16] | d[15:8] | d[7:0] |
+   *      7           6         5         4  -> address
+   * | d[31:24] | d[23:16] | d[15:8] | d[7:0] |
+   *      3           2         1         0  -> address
+   * | d[31:24] | d[23:16] | d[15:8] | d[7:0] |  */
+
+  when(io.func3 === "b010".U && io.EX_MEM_MemWr === 1.U) {
+    /** !!!!!!!!!!!!!!!!!!!! STORE WORD !!!!!!!!!!!!!!!!!!!! */
+    when(data_offset === "b00".U) {
+      // addressing 0,4,8... location of memory, enable all mask bits to write 32 bits data.
+      for(i <- 0 until 4) {
+        io.data_be_o(i) := true.B
+      }
+      // data_be_o -> 1111
+    } .elsewhen(data_offset === "b01".U) {
+      // addressing 1,5,9... location of memory, enable 3 MSB mask bits to write data, ignore the first byte location
+      io.data_be_o(0) := false.B
+      for(i <- 1 until 4) {
+        io.data_be_o(i) := true.B
+      }
+      // data_be_o -> 1110
+    } .elsewhen(data_offset === "b10".U) {
+      // addressing 2,6,10... location of memory, enable first and second bytes to write data. Ignore the first two bytes
+      for(i <- 0 until 2) {
+        io.data_be_o(i) := false.B
+      }
+      for(i <- 2 until 4) {
+        io.data_be_o(i) := true.B
+      }
+      // data_be_o -> 1100
+    } .elsewhen(data_offset === "b11".U) {
+      // addressing 3,7,11... location of memory, enable just 1 MSB bit to write data. Ignore 3 LSB bytes.
+      for(i <- 0 until 3) {
+        io.data_be_o(i) := false.B
+      }
+      io.data_be_o(3) := true.B
+      // data_be_o -> 1000
+    } .otherwise {
+      for(i <- 0 until 4) {
+        io.data_be_o(i) := true.B   // by default setting all bits of mask to 1.
+      }
+    }
+
+  } .elsewhen(io.func3 === "b001".U && io.EX_MEM_MemWr === 1.U) {
+    /** !!!!!!!!!!!!!!!!!!!! STORE HALF WORD !!!!!!!!!!!!!!!!!!!! */
+    when(data_offset === "b00".U) {
+      // addressing 0,4,8... location of memory, enable two LSB mask bits to write 16 bits data.
+      for(i <- 0 until 2) {
+        io.data_be_o(i) := true.B
+      }
+      for(i <- 2 until 4) {
+        io.data_be_o(i) := false.B
+      }
+      // data_be_o -> 0011
+    } .elsewhen(data_offset === "b01".U) {
+      // addressing 1,5,9... location of memory, enable 1st and 2nd MSB mask bits to write data, ignore the first and last byte location
+      io.data_be_o(0) := false.B
+      for(i <- 1 until 3) {
+        io.data_be_o(i) := true.B
+      }
+      io.data_be_o(3) := false.B
+      // data_be_o -> 0110
+    } .elsewhen(data_offset === "b10".U) {
+      // addressing 2,6,10... location of memory, enable 2 MSB mask bits to write data. Ignore the first two bytes
+      for(i <- 0 until 2) {
+        io.data_be_o(i) := false.B
+      }
+      for(i <- 2 until 4) {
+        io.data_be_o(i) := true.B
+      }
+      // data_be_o -> 1100
+    } .elsewhen(data_offset === "b11".U) {
+      // addressing 3,7,11... location of memory, enable just 1 MSB bit to write data. Ignore 3 LSB bytes.
+      for(i <- 0 until 3) {
+        io.data_be_o(i) := false.B
+      }
+      io.data_be_o(3) := true.B
+      // data_be_o -> 1000
+    } .otherwise {
+      for(i <- 0 until 4) {
+        io.data_be_o(i) := true.B   // by default setting all bits of mask to 1.
+      }
+    }
+  } .elsewhen(io.func3 === "b000".U && io.EX_MEM_MemWr === 1.U) {
+    /** !!!!!!!!!!!!!!!!!!!! STORE BYTE !!!!!!!!!!!!!!!!!!!! */
+    when(data_offset === "b00".U) {
+      // addressing 0,4,8... location of memory, enable zeroth LSB mask bit to write 8 bits data.
+      io.data_be_o(0) := true.B
+      for(i <- 1 until 4) {
+        io.data_be_o(i) := false.B
+      }
+      // data_be_o -> 0001
+    } .elsewhen(data_offset === "b01".U) {
+      // addressing 1,5,9... location of memory, enable 1st  mask bit to write 8 bits data, ignore the zeroth, second and last byte location
+      io.data_be_o(0) := false.B
+      io.data_be_o(1) := true.B
+      for(i <- 2 until 4) {
+        io.data_be_o(i) := false.B
+      }
+      // data_be_o -> 0010
+    } .elsewhen(data_offset === "b10".U) {
+      // addressing 2,6,10... location of memory, enable 2 MSB mask bits to write data. Ignore the first two bytes
+      for(i <- 0 until 2) {
+        io.data_be_o(i) := false.B
+      }
+      io.data_be_o(2) := true.B
+      io.data_be_o(3) := false.B
+      // data_be_o -> 0100
+    } .elsewhen(data_offset === "b11".U) {
+      // addressing 3,7,11... location of memory, enable just 1 MSB bit to write data. Ignore 3 LSB bytes.
+      for(i <- 0 until 3) {
+        io.data_be_o(i) := false.B
+      }
+      io.data_be_o(3) := true.B
+      // data_be_o -> 1000
+    } .otherwise {
+      for(i <- 0 until 4) {
+        io.data_be_o(i) := true.B   // by default setting all bits of mask to 1.
+      }
+    }
+  } .otherwise {
+    io.data_be_o := DontCare
+  }
+
+  /** ******************************************END****************************************************** */
+
+
+  /** |||||||||||||||||||||||||||| ALIGNING DATA TO BE WRITTEN INTO THE MEMORY |||||||||||||||||||||||||||| */
+
+  /** ******************************************START****************************************************** */
+
+  when(data_offset === "b00".U) {
+    data_wdata(0) := io.EX_MEM_rs2(7,0).asSInt()
+    data_wdata(1) := io.EX_MEM_rs2(15,8).asSInt()
+    data_wdata(2) := io.EX_MEM_rs2(23,16).asSInt()
+    data_wdata(3) := io.EX_MEM_rs2(31,24).asSInt()
+  } .elsewhen(data_offset === "b01".U) {
+    data_wdata(0) := io.EX_MEM_rs2(31,24).asSInt()
+    data_wdata(1) := io.EX_MEM_rs2(7,0).asSInt()
+    data_wdata(2) := io.EX_MEM_rs2(15,8).asSInt()
+    data_wdata(3) := io.EX_MEM_rs2(23,16).asSInt()
+  } .elsewhen(data_offset === "b10".U) {
+    data_wdata(0) := io.EX_MEM_rs2(31,24).asSInt()
+    data_wdata(1) := io.EX_MEM_rs2(23,16).asSInt()
+    data_wdata(2) := io.EX_MEM_rs2(7,0).asSInt()
+    data_wdata(3) := io.EX_MEM_rs2(15,8).asSInt()
+  } .elsewhen(data_offset === "b11".U) {
+    data_wdata(0) := io.EX_MEM_rs2(31,24).asSInt()
+    data_wdata(1) := io.EX_MEM_rs2(23,16).asSInt()
+    data_wdata(2) := io.EX_MEM_rs2(15,8).asSInt()
+    data_wdata(3) := io.EX_MEM_rs2(7,0).asSInt()
+  } .otherwise {
+    data_wdata(0) := io.EX_MEM_rs2(7,0).asSInt()
+    data_wdata(1) := io.EX_MEM_rs2(15,8).asSInt()
+    data_wdata(2) := io.EX_MEM_rs2(23,16).asSInt()
+    data_wdata(3) := io.EX_MEM_rs2(31,24).asSInt()
+  }
+
+  /** ******************************************END****************************************************** */
+
+
+  /** |||||||||||||||||||||||||||| GENERATING WRITE/READ REQUEST TO TILELINK |||||||||||||||||||||||||||| */
+
+  /** ******************************************START****************************************************** */
+
+  io.memAddress := io.EX_MEM_alu_output
+  when(io.data_gnt_i && (io.EX_MEM_MemWr===1.U))
+  {
+    io.data_req_o := true.B
+    //io.memAddress := io.EX_MEM_alu_output(13, 0).asSInt
+    io.data_wdata_o := data_wdata
+  } .elsewhen(io.data_gnt_i && (io.EX_MEM_MemRd === 1.U)) {
+    io.data_req_o := true.B
+    //io.memAddress := io.EX_MEM_alu_output(13, 0).asSInt
+    io.data_wdata_o := DontCare
+  } .otherwise
+    {
+      io.data_req_o := false.B
+      //io.memAddress := DontCare
+      io.data_wdata_o        := DontCare
+    }
+
+
+  /** ******************************************END****************************************************** */
+
+
+  /** |||||||||||||||||||||||||||| READING DATA FROM MEMORY IN NEXT CLOCK CYCLE |||||||||||||||||||||||||||| */
+
+  /** ******************************************START****************************************************** */
+  // TODO lh,lhu,lb,lbu working correctly for word-aligned addresses only, need to align it with un-aligned addresses as well
+  when(io.data_rvalid_i && io.EX_MEM_MemRd === 1.U)
+  {
+    load_unit.io.en := true.B   // enabling the load_unit to now read and sign extend the valid data
+//    io.data_out     := io.data_rdata_i
+    io.data_out     := load_unit.io.LoadData
+  }
+    .otherwise
+    {
+      io.data_out     := DontCare
+    }
+
+
+  /** ******************************************END****************************************************** */
+
+
+
+  /** |||||||||||||||||||||||||||| PASSING SIGNALS TO THE MEM/WB REGISTER |||||||||||||||||||||||||||| */
+
+  /** ******************************************START****************************************************** */
+  io.ctrl_MemWr_out := io.EX_MEM_MemWr
+  io.alu_output := io.EX_MEM_alu_output
+
+  io.rd_sel_out := io.EX_MEM_rd_sel
+  io.ctrl_RegWr_out := io.EX_MEM_RegWr
+  io.ctrl_CsrWen_out := io.EX_MEM_CsrWe
+  io.ctrl_MemRd_out := io.EX_MEM_MemRd
+  io.ctrl_MemToReg_out := io.EX_MEM_MemToReg
+//  io.csr_addr_out := io.EX_MEM_csr_addr
+//  io.csr_op_out := io.EX_MEM_csr_op
+  io.csr_data_out := io.EX_MEM_csr_data
+  /** ******************************************END****************************************************** */
+
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/Pc.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/Pc.scala
new file mode 100644
index 0000000..715973b
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/Pc.scala
@@ -0,0 +1,28 @@
+package core
+
+import chisel3._
+
+class Pc extends Module {
+    val io = IO(new Bundle {
+        val in = Input(SInt(32.W))
+        val out = Output(SInt(32.W))
+        val pc4 = Output(SInt(32.W))
+    })
+
+//    val reg = RegInit(256.S(32.W) - 4.S(32.W))
+val reg = RegInit(48.S(32.W) - 4.S(32.W))   // 44 -> 0x30 is base address of program memory
+    reg := io.in
+    io.pc4 := reg + 4.S
+    io.out := reg
+//    when(io.instr_gnt_i)
+//    {
+//      io.pc4 := reg + 4.S
+//    }
+//    .otherwise
+//    {
+//      io.pc4 := reg
+//
+//    }
+
+    
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/RegisterFile.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/RegisterFile.scala
new file mode 100644
index 0000000..0a53a51
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/RegisterFile.scala
@@ -0,0 +1,36 @@
+package core
+
+import chisel3._
+
+class RegisterFile extends Module {
+    val io = IO(new Bundle {
+        val regWrite = Input(UInt(1.W))
+        val rd_sel = Input(UInt(5.W))
+        val rs1_sel = Input(UInt(5.W))
+        val rs2_sel = Input(UInt(5.W))
+        val writeData = Input(SInt(32.W))
+
+      //  val stall = Input(UInt(1.W))
+
+        val rs1 = Output(SInt(32.W))
+        val rs2 = Output(SInt(32.W))
+        val reg_7 = Output(SInt(32.W))
+    })
+    
+    val registers = RegInit(VecInit(Seq.fill(32)(0.S(32.W))))
+
+    io.reg_7 := registers(7)
+    // val registers = Reg(Vec(32, SInt(32.W)))
+    registers(0) := 0.S
+    io.rs1 := registers(io.rs1_sel) 
+    io.rs2 := registers(io.rs2_sel) 
+    when(io.regWrite === 1.U /*&& io.stall =/= 1.U*/) {
+        when(io.rd_sel === "b00000".U) {
+            registers(io.rd_sel) := 0.S    
+        } .otherwise {
+            registers(io.rd_sel) := io.writeData
+        }
+        
+    }
+
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/Staller.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/Staller.scala
new file mode 100644
index 0000000..8b5b646
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/Staller.scala
@@ -0,0 +1,18 @@
+package core
+
+import chisel3._
+
+class Staller extends Module{
+  val io = IO(new Bundle {
+    val isUART = Input(UInt(1.W))
+    val isMMIO = Input(UInt(1.W))
+    val stall = Output(UInt(1.W))
+  })
+
+  when(reset.asBool() === false.B && (io.isUART === 1.U || io.isMMIO === 1.U)) {
+    io.stall := 1.U
+  } .otherwise {
+    io.stall := 0.U
+  }
+
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/Store_unit.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/Store_unit.scala
new file mode 100644
index 0000000..3fc09d7
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/Store_unit.scala
@@ -0,0 +1,31 @@
+package core
+import chisel3._
+import chisel3.util.Cat
+import chisel3.util.Fill
+class Store_unit extends Module
+{
+    val io=IO(new Bundle{
+        val func3 = Input(UInt(3.W))
+        val MemWrite= Input(UInt(1.W))
+        val Rs2  = Input(SInt(32.W))
+        val StoreData = Output(SInt(32.W))
+})
+
+        val sh = io.Rs2(15,0)
+        val sb = io.Rs2(7,0)
+        val zero = 0.U
+    when(io.func3 === "b001".U && io.MemWrite === 1.U)
+    {
+        io.StoreData := Cat(Fill(16,zero),sh).asSInt
+    }
+    .elsewhen(io.func3 === "b000".U && io.MemWrite === 1.U)
+    {
+         io.StoreData := Cat(Fill(24,zero),sb).asSInt
+    }
+    .otherwise
+    {
+         io.StoreData := io.Rs2
+    }
+    
+    
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/StructuralDetector.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/StructuralDetector.scala
new file mode 100644
index 0000000..2b5a6ec
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/StructuralDetector.scala
@@ -0,0 +1,43 @@
+package core
+
+import chisel3._
+
+
+
+class StructuralDetector extends Module {
+  val io = IO(new Bundle {
+    val rs1_sel = Input(UInt(5.W))
+    val rs2_sel = Input(UInt(5.W))
+    //val csr_addr_in_decode = Input(UInt(12.W))  // current instruction in decode stage csr addr
+    //val is_csr_inst_in_decode = Input(Bool())       // current instruction in decode stage is CSR instr
+    //val MEM_WB_csrAddr = Input(UInt(12.W))  // instruction in write back stage csr addr
+    val MEM_WB_regWr = Input(UInt(1.W))
+    //val MEM_WB_csrWen = Input(Bool())    // instruction in write back stage is CSR instr
+    val MEM_WB_REGRD = Input(UInt(5.W))
+    val inst_op_in = Input(UInt(7.W))
+    val fwd_rs1 = Output(UInt(1.W))
+    val fwd_rs2 = Output(UInt(1.W))
+  })
+/**
+ * TODO: Make handling for hazards in EX/MEM as well and ID/EX as well
+ *
+ * */
+
+  // additionaly checking for the lui opcode 0110111 since it does not have any rs1 or rs2 fields so no hazards can occur
+  when(io.MEM_WB_regWr === 1.U && io.MEM_WB_REGRD =/= "b00000".U &&  io.MEM_WB_REGRD === io.rs1_sel && io.inst_op_in =/= "b0110111".U) {
+    io.fwd_rs1 := 1.U
+  } .otherwise {
+    io.fwd_rs1 := 0.U
+  }
+
+  when(io.MEM_WB_regWr === 1.U && io.MEM_WB_REGRD =/= "b00000".U  && io.MEM_WB_REGRD === io.rs2_sel && io.inst_op_in =/= "b0110111".U) {
+    io.fwd_rs2 := 1.U
+  } .otherwise {
+    io.fwd_rs2 := 0.U
+  }
+
+//  when(io.MEM_WB_regWr === 1.U && io.MEM_WB_csrWen && io.is_csr_inst_in_decode && io.MEM_WB_csrAddr === io.csr_addr_in_decode) {
+//    io.fwd_csr := true.B
+//  }
+
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/WriteBack.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/WriteBack.scala
new file mode 100644
index 0000000..606f24e
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/WriteBack.scala
@@ -0,0 +1,19 @@
+package core
+
+import chisel3._
+
+class WriteBack extends Module {
+    val io = IO(new Bundle {
+        val MEM_WB_MemToReg = Input(UInt(1.W))
+        val MEM_WB_dataMem_data = Input(SInt(32.W))
+        val MEM_WB_alu_output = Input(SInt(32.W))
+        val write_data = Output(SInt(32.W))
+    })
+
+    when(io.MEM_WB_MemToReg === 1.U) {
+        io.write_data := io.MEM_WB_dataMem_data
+    } .otherwise {
+        io.write_data := io.MEM_WB_alu_output
+    }
+
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/BrqCounter.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/BrqCounter.scala
new file mode 100644
index 0000000..2bf4b05
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/BrqCounter.scala
@@ -0,0 +1,78 @@
+package main.scala.core.csrs
+
+import chisel3._
+import chisel3.util.Cat
+
+class BrqCounter(counterWidth: Int) extends Module
+{
+  val io = IO(new Bundle{
+    val i_counter_inc = Input(Bool())
+    val i_counterh_we = Input(Bool())
+    val i_counter_we  = Input(Bool())
+    val i_counter_val = Input(UInt(32.W))
+    val o_counter_val = Output(UInt(64.W))
+  })
+
+  val counter = Wire(UInt(64.W))
+  val counter_upd = Wire(UInt(counterWidth.W))
+  val counter_load = Wire(UInt(64.W))
+  val we  = Wire(Bool())
+  val counter_d = Wire(UInt(counterWidth.W))
+  val counter_msb = Wire(UInt(32.W))
+  val counter_lsb = Wire(UInt(32.W))
+  val cn_lsb      = Wire(UInt(counterWidth.W))
+  val cn_msb      = Wire(UInt(counterWidth.W))
+
+  // write
+  we           := io.i_counter_we | io.i_counterh_we
+  counter      := Cat(cn_msb, cn_lsb)
+  counter_load := Cat(counter_msb, counter_lsb)
+  counter_msb  := counter(63,32)
+  counter_lsb  := io.i_counter_val
+
+  when(io.i_counterh_we)
+  {
+    counter_msb := io.i_counter_val
+    counter_lsb  := counter(31,0)
+  }
+
+  // increment
+
+  counter_upd := counter(counterWidth - 1, 0) + Cat("b0".U((counterWidth-1).W), "b1".U)
+
+  // next value
+  when(we)
+  {
+    counter_d := counter_load(counterWidth-1,0).asUInt()
+  }
+    .elsewhen(io.i_counter_inc)
+    {
+      counter_d := counter_upd(counterWidth-1,0)
+    }
+    .otherwise
+    {
+      counter_d := counter(counterWidth-1,0)
+    }
+
+  val counter_q = RegInit(0.U(counterWidth.W))
+
+  counter_q := counter_d
+
+  if(counterWidth < 64)
+  {
+    val unused_counter_load = Wire(UInt((counterWidth + 32).W))
+
+    cn_lsb := counter_q
+    cn_msb := 0.U
+
+    unused_counter_load       := counter_load(63,counterWidth).asUInt()
+  }
+  else
+  {
+    counter := counter_q
+    cn_lsb := 0.U
+    cn_msb := 0.U
+  }
+  io.o_counter_val := counter
+
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrAddressMap.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrAddressMap.scala
new file mode 100644
index 0000000..a79f1d0
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrAddressMap.scala
@@ -0,0 +1,133 @@
+package main.scala.core.csrs
+import chisel3._
+
+object CsrAddressMap {
+  // machine information registers
+  val MVENDORID        = "hF11".U
+  val MARCHID          = "hF12".U
+  val MIMPID           = "hF13".U
+  val MHARTID          = "hF14".U
+
+  // Machine trap setup
+  val MSTATUS          = "h300".U
+  val MISA             = "h301".U
+  val MIE              = "h304".U
+  val MTVEC            = "h305".U
+
+  // Machine trap handling
+  val MSCRATCH         = "h340".U
+  val MEPC             = "h341".U
+  val MCAUSE           = "h342".U
+  val MTVAL            = "h343".U
+  val MIP              = "h344".U
+
+  // Debug trigger
+  val TSELECT          = "h7A0".U
+  val TDATA1           = "h7A1".U
+  val TDATA2           = "h7A2".U
+  val TDATA3           = "h7A3".U
+  val MCONTEXT         = "h7A8".U
+  val SCONTEXT         = "h7AA".U
+
+  // Debug/trace
+  val DCSR             = "h7b0".U
+  val DPC              = "h7b1".U
+
+  // Debug
+  val DSCRATCH0        = "h7b2".U // optional
+  val DSCRATCH1        = "h7b3".U // optional
+
+  // Machine Counter/Timers
+  val MCOUNTINHIBIT    = "h320".U
+  val MHPMEVENT3       = "h323".U
+  val MHPMEVENT4       = "h324".U
+  val MHPMEVENT5       = "h325".U
+  val MHPMEVENT6       = "h326".U
+  val MHPMEVENT7       = "h327".U
+  val MHPMEVENT8       = "h328".U
+  val MHPMEVENT9       = "h329".U
+  val MHPMEVENT10      = "h32A".U
+  val MHPMEVENT11      = "h32B".U
+  val MHPMEVENT12      = "h32C".U
+  val MHPMEVENT13      = "h32D".U
+  val MHPMEVENT14      = "h32E".U
+  val MHPMEVENT15      = "h32F".U
+  val MHPMEVENT16      = "h330".U
+  val MHPMEVENT17      = "h331".U
+  val MHPMEVENT18      = "h332".U
+  val MHPMEVENT19      = "h333".U
+  val MHPMEVENT20      = "h334".U
+  val MHPMEVENT21      = "h335".U
+  val MHPMEVENT22      = "h336".U
+  val MHPMEVENT23      = "h337".U
+  val MHPMEVENT24      = "h338".U
+  val MHPMEVENT25      = "h339".U
+  val MHPMEVENT26      = "h33A".U
+  val MHPMEVENT27      = "h33B".U
+  val MHPMEVENT28      = "h33C".U
+  val MHPMEVENT29      = "h33D".U
+  val MHPMEVENT30      = "h33E".U
+  val MHPMEVENT31      = "h33F".U
+  val MCYCLE           = "hB00".U
+  val MINSTRET         = "hB02".U
+  val MHPMCOUNTER3     = "hB03".U
+  val MHPMCOUNTER4     = "hB04".U
+  val MHPMCOUNTER5     = "hB05".U
+  val MHPMCOUNTER6     = "hB06".U
+  val MHPMCOUNTER7     = "hB07".U
+  val MHPMCOUNTER8     = "hB08".U
+  val MHPMCOUNTER9     = "hB09".U
+  val MHPMCOUNTER10    = "hB0A".U
+  val MHPMCOUNTER11    = "hB0B".U
+  val MHPMCOUNTER12    = "hB0C".U
+  val MHPMCOUNTER13    = "hB0D".U
+  val MHPMCOUNTER14    = "hB0E".U
+  val MHPMCOUNTER15    = "hB0F".U
+  val MHPMCOUNTER16    = "hB10".U
+  val MHPMCOUNTER17    = "hB11".U
+  val MHPMCOUNTER18    = "hB12".U
+  val MHPMCOUNTER19    = "hB13".U
+  val MHPMCOUNTER20    = "hB14".U
+  val MHPMCOUNTER21    = "hB15".U
+  val MHPMCOUNTER22    = "hB16".U
+  val MHPMCOUNTER23    = "hB17".U
+  val MHPMCOUNTER24    = "hB18".U
+  val MHPMCOUNTER25    = "hB19".U
+  val MHPMCOUNTER26    = "hB1A".U
+  val MHPMCOUNTER27    = "hB1B".U
+  val MHPMCOUNTER28    = "hB1C".U
+  val MHPMCOUNTER29    = "hB1D".U
+  val MHPMCOUNTER30    = "hB1E".U
+  val MHPMCOUNTER31    = "hB1F".U
+  val MCYCLEH          = "hB80".U
+  val MINSTRETH        = "hB82".U
+  val MHPMCOUNTER3H    = "hB83".U
+  val MHPMCOUNTER4H    = "hB84".U
+  val MHPMCOUNTER5H    = "hB85".U
+  val MHPMCOUNTER6H    = "hB86".U
+  val MHPMCOUNTER7H    = "hB87".U
+  val MHPMCOUNTER8H    = "hB88".U
+  val MHPMCOUNTER9H    = "hB89".U
+  val MHPMCOUNTER10H   = "hB8A".U
+  val MHPMCOUNTER11H   = "hB8B".U
+  val MHPMCOUNTER12H   = "hB8C".U
+  val MHPMCOUNTER13H   = "hB8D".U
+  val MHPMCOUNTER14H   = "hB8E".U
+  val MHPMCOUNTER15H   = "hB8F".U
+  val MHPMCOUNTER16H   = "hB90".U
+  val MHPMCOUNTER17H   = "hB91".U
+  val MHPMCOUNTER18H   = "hB92".U
+  val MHPMCOUNTER19H   = "hB93".U
+  val MHPMCOUNTER20H   = "hB94".U
+  val MHPMCOUNTER21H   = "hB95".U
+  val MHPMCOUNTER22H   = "hB96".U
+  val MHPMCOUNTER23H   = "hB97".U
+  val MHPMCOUNTER24H   = "hB98".U
+  val MHPMCOUNTER25H   = "hB99".U
+  val MHPMCOUNTER26H   = "hB9A".U
+  val MHPMCOUNTER27H   = "hB9B".U
+  val MHPMCOUNTER28H   = "hB9C".U
+  val MHPMCOUNTER29H   = "hB9D".U
+  val MHPMCOUNTER30H   = "hB9E".U
+  val MHPMCOUNTER31H   = "hB9F".U
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrBundles.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrBundles.scala
new file mode 100644
index 0000000..1179716
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrBundles.scala
@@ -0,0 +1,129 @@
+package main.scala.core.csrs
+import chisel3._
+import chisel3.experimental.ChiselEnum
+
+// interrupt requests
+// three type of interrupts are supported by this version of BURAQ-MINI.
+// 1) softeware interrupts
+// 2) timer interupts
+// 3) external interrupts
+// external interrupts are generated by all external device in curent implementation
+// there are two main external interrupt sources.
+// 1) GPIOs
+// 2) UART
+// and NMI at highest prioritySave
+class irqs_t extends Bundle{
+  // the wires declared here are in reverse order.
+  // Generally according to the structure of the MIE register,  _____________________
+  //                                                           | MEIE | MTIE | MSIE |
+  //                                                            --------------------
+  // the irq_software should come first,
+  // the irq_timer should come second,
+  // the irq_external should come last
+  // BUT, the asTypeOf(new irqs_t()) inverts this order (VERIFIED ON SCASTIE)
+  // i.e  if this bundle is given value 1.U,
+  // the LSB bit would be given to the last wire declared in this bundle
+  // this causes writing 1.U to the MSIE for enabling irq_software,
+  // to actually enable irq_external MEIE since it would be the last declared wire
+  // which would be wrong functionality, hence changing the order of the bundle
+  val irq_external        = Bool()
+  val irq_timer           = Bool()
+  val irq_software        = Bool()
+}
+
+// csr operations
+// 4 type of operations are performed on csrs
+// 1) Read: simple read operation e.g, reading "minstret" csr to check the no:of instructions executed
+// 2) Write: simple write operation e.g, writing to "mtimecmp" csr to set a timer event.
+// 3) Set: setting particular bits of the csrs e.g, writing to the "mstatus.mie" to enable interrupts globaly
+// 4) Clear: clearing particular bits of csrs.
+class csr_op_e extends Bundle{
+  val CSR_OP_READ        = "b00"
+  val CSR_OP_WRITE       = "b01"
+  val CSR_OP_SET         = "b10"
+  val CSR_OP_CLEAR       = "b11"
+}
+
+// bit fields of mstatus register
+// 1) mie: machine interrupt enable used to enable interrupts globally
+// 2) mpie:machine pervious interrupt enable. whenever a trap is encountered
+// the mpie field will be written with the value of mie and mie will be cleared
+// 3) mpp: machine privious priv 2 bit wide because we have 4 priv-levels
+// 4) mprv: memory privilege field used to modify priv-level at which loads and stores executes
+// usually used when memory protection is enabled or in secure embbeded enviornment.
+// 5) tw: time out wait supports intercepting the WFI(wait for interrupt) instruction
+
+class status_t extends Bundle{
+  // the wires declared here are in reverse order.
+  // Generally according to the structure of the MSTATUS register,
+  //
+  // ________________________________
+  // | TW | MPRV | MPP | MPIE | MIE |
+  // --------------------------------
+  //
+  // the mie should come first,
+  // the mpie should come second,
+  // the mpp should come third,
+  // the mprv should come fourth,
+  // the tw should come fifth,
+
+  // BUT, the asTypeOf(new mstatus_t()) inverts this order (VERIFIED ON SCASTIE)
+  // i.e  if this bundle is given value 1.U,
+  // the LSB bit would be given to the last wire declared in this bundle
+  // this causes writing 1.U to the MIE for enabling global interrupts,
+  // to actually enable timeout wait TW since it would be the last declared wire
+  // which would be wrong functionality, hence changing the order of the bundle
+  // BEFORE
+  //  val mie        = Bool()
+  //  val mpie       = Bool()
+  //  val mpp        = UInt(2.W)
+  //  val mprv       = Bool()
+  //  val tw         = Bool()
+  // NOW
+  val tw = Bool()
+  val mprv = Bool()
+  val mpp = UInt(2.W)
+  val mpie = Bool()
+  val mie = Bool()
+
+}
+
+// bit fields of "dcsr"
+// TODO: description to be provided after studying debug spec.
+class dcsr_t extends Bundle{
+  val xdebugver        = UInt(4.W)
+  val zero2            = UInt(12.W)
+  val ebreakm          = Bool()
+  val zero1            = Bool()
+  val ebreaks          = Bool()
+  val stepie           = Bool()
+  val stopcount        = Bool()
+  val stoptime         = Bool()
+  val cause            = Bool()
+  val zero0            = Bool()
+  val mprven           = Bool()
+  val nmip             = Bool()
+  val step             = Bool()
+  val prv              = Bool()
+}
+
+// all supported privilege levels supported by RISCV along with their specific codes.
+// current implementation only supports M-mode
+// which is the highest privilege mode if debug unit is not implemented.
+// these codes are also stored in mstatus.mpp and mstatus.hpp
+// to indicate the privous priv-level when handling an interrupt or exception
+// in particular priv-mode e.g, an interrupt is needed to be handled in MACHINE mode
+// but curent execution mode.
+object priv_lvl_e extends ChiselEnum{
+  val PRIV_LVL_U, PRIV_LVL_S, PRIV_LVL_H, PRIV_LVL_M = Value
+}
+
+// field specific to debug unit
+// TODO: description will be added after studying debug spec
+object x_debug_ver_e extends ChiselEnum{
+  val XDEBUGVER_NO, zero1, zero2, zero3,XDEBUGVER_STD,
+  zero4, zero5, zero6, zero7, zero8, zero9, zero10,
+  zero11, zero12,zero13, XDEBUGVER_NONSTD = Value // no external debug support
+  //   val XDEBUGVER_STD           = 4 // external debug according to RISC-V debug spec
+  //   val XDEBUGVER_NONSTD        = 15 // debug not conforming to RISC-V debug spec
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrExcCause.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrExcCause.scala
new file mode 100644
index 0000000..7ff3cc5
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrExcCause.scala
@@ -0,0 +1,14 @@
+package main.scala.core.csrs
+import chisel3._
+import chisel3.util._
+
+object Exc_Cause {
+  val EXC_CAUSE_IRQ_SOFTWARE_M            = Cat("b1".U(1.W), 3.U(5.W))
+  val EXC_CAUSE_IRQ_TIMER_M               = Cat("b1".U(1.W), 7.U(5.W))
+  val EXC_CAUSE_IRQ_EXTERNAL_M            = Cat("b1".U(1.W), 11.U(5.W))
+  val EXC_CAUSE_IRQ_NM                    = Cat("b1".U(1.W), 31.U(5.W)) //== EXC_CAUSE_IRQ_FAST_15
+  val EXC_CAUSE_INSN_ADDR_MISA            = Cat("b0".U(1.W), 0.U(5.W))
+  val EXC_CAUSE_ILLEGAL_INSN              = Cat("b0".U(1.W), 2.U(5.W))
+  val EXC_CAUSE_BREAKPOINT                = Cat("b0".U(1.W), 3.U(5.W))
+  val EXC_CAUSE_ECALL_MMODE               = Cat("b0".U(1.W), 11.U(5.W))
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrPrimitive.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrPrimitive.scala
new file mode 100644
index 0000000..d53d8b7
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrPrimitive.scala
@@ -0,0 +1,33 @@
+package main.scala.core.csrs
+import chisel3._
+
+class CsrPrimitive(width: Int, ShadowCopy: Boolean, ResetValue: Int) extends Module
+{
+  val io = IO(new Bundle{
+    val i_wrdata  = Input(UInt(width.W))
+    val i_wr_en   = Input(Bool())
+    val o_rd_data = Output(UInt(width.W))
+    val o_rd_error= Output(Bool())
+  })
+
+  val rdata_q = RegInit(ResetValue.U(width.W))
+  when(io.i_wr_en)
+  {
+    rdata_q := io.i_wrdata
+  }
+  io.o_rd_data := rdata_q
+
+  if(ShadowCopy == true)
+  {
+    val shadow_q = RegInit(~ResetValue.U(width.W))
+    when(io.i_wr_en)
+    {
+      shadow_q := ~io.i_wrdata
+    }
+    io.o_rd_error := rdata_q =/= ~shadow_q
+  }
+  else
+  {
+    io.o_rd_error := "b0".U
+  }
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrRegFields.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrRegFields.scala
new file mode 100644
index 0000000..54dc3c9
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrRegFields.scala
@@ -0,0 +1,22 @@
+package main.scala.core.csrs
+import chisel3._
+
+object MSTAT_BITS{
+  val MIE      = 3
+  val MPIE     = 7
+  val MPP_LOW  = 11
+  val MPP_HIGH = 12
+  val MPRV     = 17
+  val TW       = 21
+}
+
+// machine interrupt enable/pening bits
+// X notation is used because both registers mie and mip have
+// same bits for interrupt enable/pending
+object MIX_BITS{
+  val MSIX      = 3
+  val MTIX      = 7
+  val MEIX      = 11
+  //  val M FIX_LOW  = 16
+  //  val MFIX_HIGH = 30
+}
diff --git a/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrRegisterFile.scala b/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrRegisterFile.scala
new file mode 100644
index 0000000..251c843
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/main/scala/core/csrs/CsrRegisterFile.scala
@@ -0,0 +1,897 @@
+package main.scala.core.csrs
+import chisel3._
+import chisel3.util.Cat
+
+class CsrRegisterFile extends Module {
+  val io = IO(new Bundle{
+
+    // HART ID
+    val i_hart_id               = Input(UInt(32.W))
+    // privilege modes
+    val o_priv_mode_id          = Output(UInt(2.W))
+    val o_priv_mode_if          = Output(UInt(2.W))
+    val o_priv_mode_lsu         = Output(UInt(2.W))
+    val o_csr_mstatus_tw        = Output(Bool())
+
+    // mtvec
+    val o_csr_mtvec             = Output(UInt(32.W))
+    val i_csr_mtvec_init        = Input(Bool())
+    val i_boot_addr             = Input(UInt(32.W))
+
+    // interface to registers
+    val i_csr_access            = Input(Bool())
+    val i_csr_addr              = Input(UInt(12.W))
+    val i_csr_wdata             = Input(UInt(32.W))
+    val i_csr_op                = Input(UInt(2.W))
+    val i_csr_op_en             = Input(Bool())
+    val o_csr_rdata             = Output(UInt(32.W))
+
+    // interrupts
+    val i_irq_software          = Input(Bool())
+    val i_irq_timer             = Input(Bool())
+    val i_irq_external          = Input(Bool())
+    val i_nmi_mode              = Input(Bool())
+    val o_irq_pending           = Output(Bool())
+    val o_irqs                  = Output(UInt(3.W))
+    val o_csr_mstatus_mie       = Output(Bool())
+    val o_csr_mepc              = Output(UInt(32.W))
+
+    // debug
+    val i_debug_mode            = Input(Bool())
+    val i_debug_cause           = Input(UInt(5.W))
+    val i_debug_csr_save        = Input(Bool())
+    val o_csr_depc              = Output(UInt(32.W))
+    val o_debug_single_step     = Output(Bool())
+    val o_debug_ebreakm         = Output(Bool())
+    val o_trigger_match         = Output(Bool())
+
+    // TODO: current implementation is 5 stage pipeline so Save
+    // pc of EX and MEM stage is to be added here
+    val i_pc_if                 = Input(UInt(32.W))
+    val i_pc_id                 = Input(UInt(32.W))
+    val i_pc_wb                 = Input(UInt(32.W))
+
+    // exception save/restore
+    val i_csr_save_if           = Input(Bool())
+    val i_csr_save_id           = Input(Bool())
+    val i_csr_save_wb           = Input(Bool())
+    val i_csr_restore_mret      = Input(Bool())
+    val i_csr_restore_dret      = Input(Bool())
+    val i_csr_save_cause        = Input(Bool())
+    val i_csr_mcause            = Input(UInt(6.W))
+    val i_csr_mtval             = Input(UInt(32.W))
+    val o_illegal_csr_insn      = Output(Bool())
+
+    // performance counters
+    val i_instr_ret             = Input(Bool()) // instruction completed decode stage
+    val i_iside_wait            = Input(Bool()) // core waiting for iside
+    val i_dside_wait            = Input(Bool()) // waiting for data memory
+    val i_jump                  = Input(Bool()) // jump instruction detected
+    val i_branch                = Input(Bool()) // branch instruction detected
+    val i_branch_taken          = Input(Bool()) // branch condition becomes true
+    val i_mem_load              = Input(Bool()) // load from memory
+    val i_mem_store             = Input(Bool()) // store to memory
+
+
+  })
+
+  val irq    = new irqs_t()
+  val csr_op = new csr_op_e()
+  val st     = new status_t()
+  val dct    = new dcsr_t()
+
+  val DbgTriggerEn: Int = 0
+  val DbgHwBreakNum: Int = 1
+
+
+  val MISA_VALUE = Wire(UInt(32.W))
+  // | A-atomic   | C-compressed | D-double precision | E-RV32E    | F-single precision | I-RV32I/64I/128I |
+  // | extension  | extension    | floating point     | base ISA   | floating point     | base ISA         |
+  MISA_VALUE:=((0.U << 1)  | (0.U << 2)   | (0.U << 3)         | (0.U << 4) | (0.U << 5)         | (1.U << 8)
+    //  | M-multiply | N-user level | S-supervisor mode  | U-user mode| X-non standard     | M-XLEN           |
+    //  | & divide   | interrupts   | implemented        | implemented| extensions         | ISA width        |
+    |(1.U << 12) | (0.U << 13)  | (0.U << 18)        | (0.U << 20)| (0.U << 23)        | (1.U << 30))
+
+  // insterrupt and exception control signals
+  val exception_pc = Wire(UInt(32.W))
+
+  // csr regs
+  val priv_lvl_d = Wire(UInt(2.W))
+  val priv_lvl_q = RegInit("b11".U(2.W))
+
+  val mstatus_q              = dontTouch(WireInit(0.U.asTypeOf(new status_t())))
+  val mstatus_d              = dontTouch(WireInit(0.U.asTypeOf(new status_t())))
+  val mstatus_en             = dontTouch(Wire(Bool()))
+  val mie_q                  = dontTouch(WireInit(0.U.asTypeOf(new irqs_t())))
+  val mie_d                  = dontTouch(WireInit(0.U.asTypeOf(new irqs_t())))
+  val mie_en                 = dontTouch(Wire(Bool()))
+  val mscratch_q             = dontTouch(Wire(UInt(32.W)))
+  val mscratch_en            = dontTouch(Wire(Bool()))
+  val mepc_q                 = dontTouch(Wire(UInt(32.W)))
+  val mepc_d                 = dontTouch(Wire(UInt(32.W)))
+  val mepc_en                = dontTouch(Wire(Bool()))
+  val mcause_q, mcause_d     = dontTouch(Wire(UInt(6.W)))
+  val mcause_en              = dontTouch(Wire(Bool()))
+  val mtval_q, mtval_d       = dontTouch(Wire(UInt(32.W)))
+  val mtval_en               = dontTouch(Wire(Bool()))
+  val mtvec_q, mtvec_d       = dontTouch(Wire(UInt(32.W)))
+  val mtvec_en               = dontTouch(Wire(Bool()))
+  val mip                    = dontTouch(WireInit(0.U.asTypeOf(new irqs_t())))
+  val dcsr_d, dcsr_q         = dontTouch(WireInit(0.U.asTypeOf(new dcsr_t())))
+  val dcsr_en                = dontTouch(Wire(Bool()))
+  val depc_q, depc_d         = dontTouch(Wire(UInt(32.W)))
+  val depc_en                = dontTouch(Wire(Bool()))
+  val dscratch0_q            = dontTouch(Wire(UInt(32.W)))
+  val dscratch1_q            = dontTouch(Wire(UInt(32.W)))
+  val dscratch0_en           = dontTouch(Wire(Bool()))
+  val dscratch1_en           = dontTouch(Wire(Bool()))
+
+
+  // hardware performance monitor signals
+  val mcountinhibit          = dontTouch(Wire(UInt(32.W)))
+  val mcountinhibit_d        = dontTouch(Wire(UInt(13.W)))
+  val mcountinhibit_q        = dontTouch(RegInit(0.U(13.W)))
+  //  val mcountinhibit_en       = Wire(Bool())
+
+  // machine event/performance counters
+  val mhpmcounter            = dontTouch(RegInit(VecInit(Seq.fill(32)(0.U(64.W)))))
+  val mhpmcounter_we         = dontTouch(Wire(UInt(32.W)))
+  val mcountinhibit_we       = dontTouch(Wire(Bool()))
+  val mhpmcounterh_we        = dontTouch(Wire(UInt(32.W)))
+  val mhpmcounter_incr       = dontTouch(Wire(UInt(32.W)))
+  val mhpmevent              = dontTouch(RegInit(VecInit(Seq.fill(32)(0.U(32.W)))))
+  val mhpmcounter_idx        = dontTouch(Wire(UInt(5.W)))
+
+
+  // debug/trigger registers
+  val tselect_rdata          = Wire(UInt(32.W))
+  val tmatch_control_rdata   = Wire(UInt(32.W))
+  val tmatch_value_rdata     = Wire(UInt(32.W))
+
+  // CSR update logicSave
+  val csr_wdata_int          = Wire(UInt(32.W))
+  val csr_rdata_int          = Wire(UInt(32.W))
+  val csr_we_int             = dontTouch(Wire(Bool()))
+  val csr_wreq               = Wire(Bool())
+
+  // access violation signals
+  val illegal_csr            = Wire(Bool())
+  val illegal_csr_priv       = Wire(Bool())
+  val illegal_csr_write      = Wire(Bool())
+
+  val unused_boot_addr       = Wire(UInt(8.W))
+  val unused_csr_addr        = Wire(UInt(3.W))
+
+  unused_boot_addr   := io.i_boot_addr(7,0)
+
+  // CSR reg //
+
+  val csr_addr       = Wire(UInt(12.W))
+  val dcsr_wire      = WireInit(0.U.asTypeOf(new dcsr_t()))
+
+  csr_addr  := io.i_csr_addr
+
+  unused_csr_addr := csr_addr(7,5)
+  mhpmcounter_idx := csr_addr(4,0)
+
+  mstatus_en := "b0".U
+  mstatus_d.mie  := mstatus_q.mie
+  mstatus_d.mpie := mstatus_q.mpie
+  mstatus_d.mpp  := mstatus_q.mpp
+  mstatus_d.mprv := mstatus_q.mprv
+  mstatus_d.tw   := mstatus_q.tw
+  mscratch_en:= "b0".U
+  mie_en     := "b0".U
+  mepc_en    := "b0".U
+  mcause_en  := "b0".U
+  mtval_en   := "b0".U
+  depc_en    := "b0".U
+  dscratch0_en := "b0".U
+  dscratch1_en := "b0".U
+  dcsr_en    := "b0".U
+  mcountinhibit_we := "b0".U
+  mhpmcounter_we   := 0.U
+  mhpmcounterh_we  := 0.U
+
+  // The standard RISC-V ISA sets aside a 12-bit encoding space (csr[11:0]) for up to 4,096 CSRs.
+  // By convention, the upper 4 bits of the CSR address (csr[11:8]) are used to encode the read and
+  // write accessibility of the CSRs according to privilege level. The top two bits
+  // (csr[11:10]) indicate whether the register is read/write (00, 01, or 10) or read-only (11). The next
+  // two bits (csr[9:8]) encode the lowest privilege level that can access the CSR.
+  illegal_csr_priv := (io.i_csr_addr(9,8) > priv_lvl_q.asUInt)
+
+  illegal_csr_write := ((io.i_csr_addr(11,10) === "b11".U) & csr_wreq)
+
+  io.o_illegal_csr_insn  := (io.i_csr_access & (illegal_csr | illegal_csr_priv | illegal_csr_write))
+
+
+  mip.irq_software  := io.i_irq_software
+  mip.irq_external  := io.i_irq_external
+  mip.irq_timer     := io.i_irq_timer
+
+  // CSR read logic
+
+  csr_rdata_int := "b0".U
+  illegal_csr   := "b0".U
+
+
+  when(io.i_csr_addr === CsrAddressMap.MHARTID)
+  {
+    // hardware thread ID
+    csr_rdata_int := io.i_hart_id.asUInt
+  }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.MSTATUS)
+    {
+      // mstatus register contains interrupt enable bits
+      csr_rdata_int := Cat("b0".U(10.W),mstatus_q.tw, "b0".U(3.W),
+        mstatus_q.mprv, "b0".U(4.W),mstatus_q.mpp,
+        "b0".U(3.W),mstatus_q.mpie ,"b0".U(3.W),
+        mstatus_q.mie,"b0".U(3.W))
+    }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.MISA)
+    {
+      // machine ISA register valueSave
+      csr_rdata_int := MISA_VALUE.asUInt
+    }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.MIE)
+    {
+      // machine interrupt enable bits
+      csr_rdata_int := Cat("b0".U(20.W),mie_q.irq_external,
+        "b0".U(3.W), mie_q.irq_timer,
+        "b0".U(3.W), mie_q.irq_software,
+        "b0".U(3.W))
+    }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.MSCRATCH)
+    {
+      // machine scratch register for holding a temporary GPR value
+      // when trap is enountered
+      csr_rdata_int := mscratch_q.asUInt
+    }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.MTVEC)
+    {
+      // machine trap vector register holds the base address of
+      // trap handlers and mode of trap handling either it is direct mode
+      // or vectored mode. in vector mode all interrupts or exceptions trap to stoptime
+      // different ISR's while in direct mode there will be a single trap handler for all.
+      // lower 2 bits of mtvec regiInsightsster specify the mode of operation.
+      csr_rdata_int := mtvec_q.asUInt
+    }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.MEPC)
+    {
+      // machine exception PC. when an interrupt or exception is encountered MEPC holds the
+      // address of the instruction from where the execution will resume after trap handling.
+      csr_rdata_int := mepc_q.asUInt
+    }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.MCAUSE)
+    {
+      // here the msb[mcause(5)] bit indicates that he cause is exception [mcause(5) = 0]
+      // or it is an interrupt [mcause(5) =PRIV_LVL_M 1]. and lower 5 bits [mcause(4,0)] are for all
+      // supported interrupts and exceptions codes.
+      csr_rdata_int := Cat(mcause_q(5), "b0".U(26.W), mcause_q(4,0)).asUInt
+    }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.MTVAL)
+    {
+      // machine trap value register, holds the instruction or address of the instruction that causes an interrupt or exception.
+      csr_rdata_int := mtval_q.asUInt
+    }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.MIP)
+    {
+      // machine insterrupt pending bits
+      csr_rdata_int := Cat("b0".U(20.W),mip.irq_external,
+        "b0".U(3.W), mip.irq_timer,
+        "b0".U(3.W), mip.irq_software,
+        "b0".U(3.W))
+    }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.DCSR)
+    {
+      csr_rdata_int := dcsr_q.asUInt
+      illegal_csr   := ~io.i_debug_mode
+    }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.DPC)
+    {
+      csr_rdata_int := depc_q.asUInt
+      illegal_csr   := ~io.i_debug_mode
+    }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.DSCRATCH0)
+    {
+      csr_rdata_int := dscratch0_q.asUInt
+    }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.DSCRATCH1)
+    {
+      csr_rdata_int := dscratch1_q.asUInt
+      illegal_csr   := ~io.i_debug_mode
+    }
+    // machine counters/timers
+    .elsewhen(io.i_csr_addr === CsrAddressMap.MCOUNTINHIBIT)
+    {
+      // machine counter inhibit ir decides which counter will increment on an event
+      csr_rdata_int := mcountinhibit.asUInt
+    }
+    .elsewhen((io.i_csr_addr === CsrAddressMap.MHPMEVENT3) | (io.i_csr_addr === CsrAddressMap.MHPMEVENT4) | (io.i_csr_addr === CsrAddressMap.MHPMEVENT5) | (io.i_csr_addr === CsrAddressMap.MHPMEVENT6) |
+      (io.i_csr_addr === CsrAddressMap.MHPMEVENT7) | (io.i_csr_addr === CsrAddressMap.MHPMEVENT8) | (io.i_csr_addr === CsrAddressMap.MHPMEVENT9) | (io.i_csr_addr === CsrAddressMap.MHPMEVENT10)|
+      (io.i_csr_addr === CsrAddressMap.MHPMEVENT11)| (io.i_csr_addr === CsrAddressMap.MHPMEVENT12)| (io.i_csr_addr === CsrAddressMap.MHPMEVENT13)| (io.i_csr_addr === CsrAddressMap.MHPMEVENT14)|
+      (io.i_csr_addr === CsrAddressMap.MHPMEVENT15)| (io.i_csr_addr === CsrAddressMap.MHPMEVENT16)| (io.i_csr_addr === CsrAddressMap.MHPMEVENT17)| (io.i_csr_addr === CsrAddressMap.MHPMEVENT18)|
+      (io.i_csr_addr === CsrAddressMap.MHPMEVENT19)| (io.i_csr_addr === CsrAddressMap.MHPMEVENT20)| (io.i_csr_addr === CsrAddressMap.MHPMEVENT21)| (io.i_csr_addr === CsrAddressMap.MHPMEVENT22)|
+      (io.i_csr_addr === CsrAddressMap.MHPMEVENT23)| (io.i_csr_addr === CsrAddressMap.MHPMEVENT24)| (io.i_csr_addr === CsrAddressMap.MHPMEVENT25)| (io.i_csr_addr === CsrAddressMap.MHPMEVENT26)|
+      (io.i_csr_addr === CsrAddressMap.MHPMEVENT27)| (io.i_csr_addr === CsrAddressMap.MHPMEVENT28)| (io.i_csr_addr === CsrAddressMap.MHPMEVENT29)| (io.i_csr_addr === CsrAddressMap.MHPMEVENT30)|
+      (io.i_csr_addr === CsrAddressMap.MHPMEVENT31))
+    {
+      csr_rdata_int := mhpmevent(mhpmcounter_idx.asUInt)
+    }
+    .elsewhen((io.i_csr_addr === CsrAddressMap.MCYCLE)       | (io.i_csr_addr === CsrAddressMap.MINSTRET)     | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER3) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER4) |
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER5) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER6) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER7) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER8) |
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER9) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER10)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER11)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER12)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER13)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER14)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER15)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER16)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER17)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER18)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER19)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER20)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER21)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER22)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER23)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER24)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER25)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER26)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER27)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER28)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER29)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER30)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER31))
+    {
+      val lsb = Wire(UInt(64.W))
+      lsb := mhpmcounter(mhpmcounter_idx.asUInt)
+      csr_rdata_int := lsb(31,0)
+    }
+    .elsewhen((io.i_csr_addr === CsrAddressMap.MCYCLEH)       | (io.i_csr_addr === CsrAddressMap.MINSTRETH)     | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER3H) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER4H) |
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER5H) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER6H) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER7H) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER8H) |
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER9H) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER10H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER11H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER12H)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER13H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER14H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER15H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER16H)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER17H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER18H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER19H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER20H)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER21H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER22H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER23H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER24H)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER25H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER26H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER27H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER28H)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER29H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER30H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER31H))
+    {
+      val msb = Wire(UInt(64.W))
+      msb := mhpmcounter(mhpmcounter_idx.asUInt)
+      csr_rdata_int := msb(63,32)
+    }
+    // debug triggers
+    .elsewhen(io.i_csr_addr === CsrAddressMap.TSELECT)
+    {
+      csr_rdata_int := tselect_rdata.asUInt
+      illegal_csr   := ~(DbgTriggerEn.asUInt)
+    }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.TDATA1)
+    {
+      csr_rdata_int := tmatch_control_rdata.asUInt
+      illegal_csr   := ~(DbgTriggerEn.asUInt)
+    }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.TDATA2)
+    {
+      csr_rdata_int := tmatch_value_rdata.asUInt
+      illegal_csr   := ~(DbgTriggerEn.asUInt)
+    }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.TDATA3)
+    {
+      csr_rdata_int := 0.U
+      illegal_csr   := ~(DbgTriggerEn.asUInt)
+    }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.MCONTEXT)
+    {
+      csr_rdata_int := 0.U
+    }
+    .elsewhen(io.i_csr_addr === CsrAddressMap.SCONTEXT)
+    {
+      csr_rdata_int := 0.U
+      illegal_csr   := ~(DbgTriggerEn.asUInt)
+    }
+    .otherwise
+    {
+      csr_rdata_int := 0.U
+      illegal_csr   := "b1".U
+    }
+
+
+
+
+  /////////////////////
+  // CSR write logic //
+  /////////////////////
+
+  // stores the PC of next instruction
+  val mstat_priv = dontTouch(Wire(Bool()))
+  mstat_priv :=  (mstatus_d.mpp.asUInt =/= priv_lvl_e.PRIV_LVL_M.asUInt) && (mstatus_d.mpp.asUInt =/= priv_lvl_e.PRIV_LVL_U.asUInt)
+  csr_we_int := csr_wreq & ~io.o_illegal_csr_insn
+  //when(csr_we_int === "b1".U)
+  // {
+  // mtatus interrupt enable bits
+  when(csr_we_int & (io.i_csr_addr === CsrAddressMap.MSTATUS))
+  {
+    mstatus_en := "b1".U
+    mstatus_d.mie  := csr_wdata_int(MSTAT_BITS.MIE)
+    mstatus_d.mpie := csr_wdata_int(MSTAT_BITS.MPIE)
+    mstatus_d.mpp  := csr_wdata_int(MSTAT_BITS.MPP_HIGH, MSTAT_BITS.MPP_LOW)
+    mstatus_d.tw   := csr_wdata_int(MSTAT_BITS.TW)
+    when((mstatus_q.mpp.asUInt =/= priv_lvl_e.PRIV_LVL_M.asUInt) && (mstatus_q.mpp.asUInt =/= priv_lvl_e.PRIV_LVL_U.asUInt))
+    {
+      mstatus_d.mpp := priv_lvl_e.PRIV_LVL_M.asUInt
+    }
+  }
+    // interrupt enable
+    .elsewhen(csr_we_int & (io.i_csr_addr === CsrAddressMap.MIE))
+    {
+      mie_en := "b1".U
+    }
+    .elsewhen(csr_we_int & (io.i_csr_addr === CsrAddressMap.MSCRATCH))
+    {
+      mscratch_en := "b1".U
+    }
+    .elsewhen(csr_we_int & (io.i_csr_addr === CsrAddressMap.MEPC))
+    {
+      mepc_en := "b1".U
+    }
+    .elsewhen(csr_we_int & (io.i_csr_addr === CsrAddressMap.MCAUSE))
+    {
+      mcause_en := "b1".U
+    }
+    .elsewhen(csr_we_int & (io.i_csr_addr === CsrAddressMap.MTVAL))
+    {
+      mtval_en := "b1".U
+    }
+    .elsewhen(csr_we_int & (io.i_csr_addr === CsrAddressMap.MTVEC))
+    {
+      mtvec_en := "b1".U
+    }
+    .elsewhen(csr_we_int & (io.i_csr_addr === CsrAddressMap.DCSR))
+    {
+      dcsr_d := csr_wdata_int.asTypeOf(new dcsr_t())
+      dcsr_wire.xdebugver  := x_debug_ver_e.XDEBUGVER_STD.asUInt
+      dcsr_d.xdebugver := dcsr_wire.xdebugver
+      // chnage to priv_lvl_m if software writes an unsupported value
+      when((dcsr_d.prv =/=  priv_lvl_e.PRIV_LVL_M.asUInt) & (dcsr_d.prv =/=  priv_lvl_e.PRIV_LVL_U.asUInt))
+      {
+        dcsr_d.prv := priv_lvl_e.PRIV_LVL_M.asUInt
+      }
+      // read-only for sw
+      dcsr_d.cause := dcsr_q.cause
+
+      // currently not supported
+      dcsr_d.nmip      := "b0".U
+      dcsr_d.mprven    := "b0".U
+      dcsr_d.stopcount := "b0".U
+      dcsr_d.stoptime  := "b0".U
+    }
+    .elsewhen(csr_we_int & (io.i_csr_addr === CsrAddressMap.DSCRATCH0))
+    {
+      dscratch0_en := "b1".U
+    }
+    .elsewhen(csr_we_int & (io.i_csr_addr === CsrAddressMap.DSCRATCH1))
+    {
+      dscratch1_en := "b1".U
+    }
+    .elsewhen(csr_we_int & (io.i_csr_addr === CsrAddressMap.MCOUNTINHIBIT))
+    {
+      mcountinhibit_we := "b1".U
+    }
+    .elsewhen(csr_we_int & ((io.i_csr_addr === CsrAddressMap.MCYCLE)       | (io.i_csr_addr === CsrAddressMap.MINSTRET)     | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER3) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER4) |
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER5) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER6) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER7) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER8) |
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER9) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER10)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER11)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER12)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER13)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER14)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER15)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER16)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER17)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER18)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER19)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER20)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER21)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER22)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER23)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER24)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER25)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER26)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER27)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER28)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER29)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER30)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER31)))
+    {
+      mhpmcounter_we := "b1".U << mhpmcounter_idx
+    }
+    .elsewhen(csr_we_int & ((io.i_csr_addr === CsrAddressMap.MCYCLEH)       | (io.i_csr_addr === CsrAddressMap.MINSTRETH)     | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER3H) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER4H) |
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER5H) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER6H) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER7H) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER8H) |
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER9H) | (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER10H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER11H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER12H)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER13H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER14H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER15H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER16H)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER17H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER18H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER19H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER20H)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER21H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER22H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER23H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER24H)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER25H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER26H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER27H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER28H)|
+      (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER29H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER30H)| (io.i_csr_addr === CsrAddressMap.MHPMCOUNTER31H)))
+    {
+      mhpmcounterh_we := "b1".U << mhpmcounter_idx
+    }
+  priv_lvl_d := priv_lvl_q.asUInt
+
+
+  mepc_d     := Cat(csr_wdata_int(31,1), "b0".U)
+  mcause_d   := Cat(csr_wdata_int(31), csr_wdata_int(4,0))
+  mtval_d    := csr_wdata_int
+  mtvec_en   := io.i_csr_mtvec_init
+
+  // mode set to vector mode and base address is 256 byte aligned
+  mtvec_d    := Mux(io.i_csr_mtvec_init, Cat(io.i_boot_addr(31,8),
+    "b0".U(6.W), "b01".U), Cat(csr_wdata_int(31,8),
+    "b0".U(6.W), "b01".U))
+
+  dcsr_d     := dcsr_q
+  depc_d     := Cat(csr_wdata_int(31,1), "b0".U)
+
+
+  exception_pc := io.i_pc_id
+
+
+  // exception gets priority over the other writes
+  when(io.i_csr_save_cause === "b1".U)
+  {
+    when(io.i_csr_save_if === "b1".U)
+    {
+      exception_pc := io.i_pc_if
+    }
+      .elsewhen(io.i_csr_save_id === "b1".U)
+      {
+        exception_pc := io.i_pc_id
+      }
+      .elsewhen(io.i_csr_save_wb === "b1".U)
+      {
+        exception_pc := io.i_pc_wb
+      }
+    // incase of any exception switch to debug mode
+    priv_lvl_d := priv_lvl_e.PRIV_LVL_M.asUInt
+
+    when(io.i_debug_csr_save)
+    {
+      // all instrrupts are masked
+      // do not update epc, tval and  status
+      dcsr_d.prv    := priv_lvl_q.asUInt
+      dcsr_d.cause  := io.i_debug_cause
+      dcsr_en      := "b1".U
+      depc_d       := exception_pc
+      depc_en      := "b1".U
+    }
+      .elsewhen(~io.i_debug_mode)
+      {
+        // in debug mode exceptions do not update any register that
+        // includes cause , epc, tval and mstatus
+        mtval_en       := "b1".U
+        mtval_d        := io.i_csr_mtval
+        mstatus_en     := "b1".U
+        mstatus_d.mie  := "b0".U // disable interrupts
+        // save the current state
+        mstatus_d.mpie := mstatus_q.mie
+        mstatus_d.mpp  := priv_lvl_q.asUInt
+        mstatus_d.mprv := "b0".U
+        mstatus_d.tw   := "b0".U
+        mepc_en        := "b1".U
+        mepc_d         := exception_pc
+        mcause_en      := "b1".U
+        mcause_d       := io.i_csr_mcause
+      }
+
+  } // end save_cause
+
+    when(io.i_csr_restore_dret) // DRET
+    {
+      priv_lvl_d.asUInt := dcsr_q.prv
+    }
+    when(io.i_csr_restore_mret) // MRET
+    {
+      priv_lvl_d.asUInt  := mstatus_q.mpp
+      mstatus_en     := "b1".U
+      mstatus_d.mie  := mstatus_q.mpie
+      mstatus_d.mpie := "b1".U
+      mstatus_d.mpp  := priv_lvl_e.PRIV_LVL_M.asUInt
+    }
+  // updating current priv-level
+
+  when(reset.asBool())
+  {
+    priv_lvl_q  := priv_lvl_e.PRIV_LVL_M.asUInt
+  }
+    .otherwise
+    {
+      priv_lvl_q.asUInt  := priv_lvl_d
+    }
+
+  // send current priv-level to decoder
+  io.o_priv_mode_id := priv_lvl_q.asUInt
+
+  // new instruction fetches nedds to acount for updates to priv_level_q this cycle
+
+  io.o_priv_mode_if := priv_lvl_d.asUInt
+
+  // load/store instructions must factor in MPRV for PMP checking
+  // NOTE: PMP is not implemented in current design so condition will always false
+
+  io.o_priv_mode_lsu  := Mux(mstatus_q.mprv, mstatus_q.mpp, priv_lvl_q.asUInt)
+
+  /////////////////////////
+  // CSR operation logic //
+  /////////////////////////
+
+  // switch(io.i_csr_op.asUInt)
+  // {
+  when(io.i_csr_op === csr_op.CSR_OP_WRITE.U)
+  {
+    csr_wdata_int := io.i_csr_wdata
+  }
+    .elsewhen(io.i_csr_op === csr_op.CSR_OP_SET.U)
+    {
+      csr_wdata_int := io.i_csr_wdata | io.o_csr_rdata
+    }
+    .elsewhen(io.i_csr_op === csr_op.CSR_OP_CLEAR.U)
+    {
+      csr_wdata_int := ~io.i_csr_wdata & io.o_csr_rdata
+    }
+    .elsewhen(io.i_csr_op === csr_op.CSR_OP_READ.U)
+    {
+      csr_wdata_int := io.i_csr_wdata
+    }
+    .otherwise
+    {
+      csr_wdata_int := io.i_csr_wdata
+    }
+
+  csr_wreq  := io.i_csr_op_en & ((io.i_csr_op === csr_op.CSR_OP_WRITE.U) | (io.i_csr_op === csr_op.CSR_OP_SET.U) | (io.i_csr_op === csr_op.CSR_OP_CLEAR.U))
+
+  // only write CSRs during one clock cycle
+
+
+  io.o_csr_rdata := csr_rdata_int.asUInt
+
+  // directly output some csrs
+  io.o_csr_mepc  := mepc_q
+  io.o_csr_depc  := depc_q
+  io.o_csr_mtvec := mtvec_q
+  io.o_csr_mstatus_mie := mstatus_q.mie
+  io.o_csr_mstatus_tw  := mstatus_q.tw
+  io.o_debug_single_step := dcsr_q.step
+  io.o_debug_ebreakm     := dcsr_q.ebreakm
+
+  // Qualify incoming interrupt requests in mip CSR with mie CSR for controller and to re-enable
+  // clock upon WFI (must be purely combinational).
+  io.o_irqs := Cat(Mux((mip.irq_external && mie_q.irq_external) === true.B, 1.U(1.W), 0.U(1.W)), Mux((mip.irq_timer && mie_q.irq_timer) === true.B, 1.U(1.W), 0.U(1.W)), Mux((mip.irq_software && mie_q.irq_software) === true.B, 1.U(1.W), 0.U(1.W)))
+  io.o_irq_pending := (io.o_irqs).orR
+
+  //////////////////////////Save
+  // CSR instantisaaation //
+  //////////////////////////
+
+  // MSTATUS
+  // val error = Wire(Bool())
+  val MSTATUS_RST_VAL = 0x0d  // this makes mie -> 1, mpie -> 0, mpp -> 11(M mode), tw -> 0
+
+  val PRIM_MSTATUS = Module(new CsrPrimitive(st.getWidth, false, MSTATUS_RST_VAL))
+  PRIM_MSTATUS.io.i_wrdata := mstatus_d.asUInt
+  PRIM_MSTATUS.io.i_wr_en   := mstatus_en
+  mstatus_q       := PRIM_MSTATUS.io.o_rd_data.asTypeOf(new status_t())
+
+  // MEPC
+  val PRIM_MEPC = Module(new CsrPrimitive(32, false, 0))
+  PRIM_MEPC.io.i_wrdata := mepc_d
+  PRIM_MEPC.io.i_wr_en   := mepc_en
+  mepc_q                 := PRIM_MEPC.io.o_rd_data
+
+
+  // MIE
+  mie_d.irq_software  := csr_wdata_int(MIX_BITS.MSIX)
+  mie_d.irq_timer     := csr_wdata_int(MIX_BITS.MTIX)
+  mie_d.irq_external  := csr_wdata_int(MIX_BITS.MEIX)
+
+  val PRIM_MIE = Module(new CsrPrimitive(3, false, 4))
+  PRIM_MIE.io.i_wrdata := mie_d.asUInt
+  PRIM_MIE.io.i_wr_en   := mie_en
+  mie_q  := PRIM_MIE.io.o_rd_data.asTypeOf(new irqs_t())
+
+
+  // MSCRATCH
+  val PRIM_MSCRATCH = Module(new CsrPrimitive(32, false, 0))
+  PRIM_MSCRATCH.io.i_wrdata := csr_wdata_int
+  PRIM_MSCRATCH.io.i_wr_en   := mscratch_en
+  mscratch_q                 := PRIM_MSCRATCH.io.o_rd_data
+
+
+  // MCAUSE
+  val PRIM_MCAUSE = Module(new CsrPrimitive(6, false, 0))
+  PRIM_MCAUSE.io.i_wrdata := mcause_d
+  PRIM_MCAUSE.io.i_wr_en   := mcause_en
+  mcause_q                 := PRIM_MCAUSE.io.o_rd_data
+
+  // MTVAL
+  val PRIM_MTVAL = Module(new CsrPrimitive(32, false, 0))
+  PRIM_MTVAL.io.i_wrdata := mtval_d
+  PRIM_MTVAL.io.i_wr_en   := mtval_en
+  mtval_q                 := PRIM_MTVAL.io.o_rd_data
+
+
+  // MTVEC
+  val PRIM_MTVEC = Module(new CsrPrimitive(32, false, 1))
+  PRIM_MTVEC.io.i_wrdata := mtvec_d
+  PRIM_MTVEC.io.i_wr_en   := mtvec_en
+  mtvec_q                 := PRIM_MTVEC.io.o_rd_data
+
+
+
+  // DCSR
+
+  // val DCSR_RST_VALUE = Cat((dct.xdebugver.XDEBUGVER_STD), (dct.xdebugver.DBG_CAUSE_NONE), (dct.PRIV_LVL_M),0)
+  val PRIM_DCSR = Module(new CsrPrimitive(dct.getWidth, false, 0))
+  PRIM_DCSR.io.i_wrdata := dcsr_d.asUInt
+  PRIM_DCSR.io.i_wr_en   := dcsr_en
+  dcsr_q                 := PRIM_DCSR.io.o_rd_data.asTypeOf(new dcsr_t())
+
+
+  // DEPC
+  val PRIM_DEPC = Module(new CsrPrimitive(32,false, 0))
+  PRIM_DEPC.io.i_wrdata := depc_d
+  PRIM_DEPC.io.i_wr_en   := depc_en
+  depc_q                 := PRIM_DEPC.io.o_rd_data
+
+  // DSCRATCH
+  val PRIM_DSCRATCH0 = Module(new CsrPrimitive(32, false, 0))
+  PRIM_DSCRATCH0.io.i_wrdata := csr_wdata_int
+  PRIM_DSCRATCH0.io.i_wr_en   := dscratch0_en
+  dscratch0_q                 := PRIM_DSCRATCH0.io.o_rd_data
+
+
+  // DSCRATCH1
+  val PRIM_DSCRATCH1 = Module(new CsrPrimitive(32, false, 0))
+  PRIM_DSCRATCH1.io.i_wrdata := csr_wdata_int
+  PRIM_DSCRATCH1.io.i_wr_en   := dscratch1_en
+  dscratch1_q                 := PRIM_DSCRATCH1.io.o_rd_data
+
+
+  //////////////////////////
+  // Performance Monitors //
+  //////////////////////////
+
+  // update enbale signals
+
+  when(mcountinhibit_we)
+  {
+    // bit 1 must be zero
+    mcountinhibit_d := Cat(csr_wdata_int(12,2), "b1".U, csr_wdata_int(0))
+  }
+    .otherwise
+    {
+      mcountinhibit_d := mcountinhibit_q
+    }
+  // event selection
+  for(i <- 10  until 32)
+  {
+    mhpmcounter_incr := "b0".U << i
+  }
+
+  // active counters
+  mhpmcounter_incr  := "b1".U << 0       // mcycle
+  mhpmcounter_incr  := "b0".U << 1           // reserved
+  mhpmcounter_incr  := io.i_instr_ret << 2   // minstret
+  mhpmcounter_incr  := io.i_dside_wait<< 3  // cycles waiting for data memory
+  mhpmcounter_incr  := io.i_iside_wait<< 4   // cycles waiting for instruction fetch
+  mhpmcounter_incr  := io.i_mem_load  << 5   // number of loads
+  mhpmcounter_incr  := io.i_mem_store << 6   // number of stores
+  mhpmcounter_incr  := io.i_jump      << 7   // number of jumps
+  mhpmcounter_incr  := io.i_branch    << 8   // number of branches
+  mhpmcounter_incr  := io.i_branch_taken << 9// number od taken branches
+
+  // active
+
+  for(i <- 0 until 32)
+  {
+    mhpmevent(i) := 0.U
+    mhpmevent(i) := "b1".U << i
+  }
+
+  // deacvtivate
+  mhpmevent(1) := 0.U
+
+  for(i <- 13 until 32)
+  {
+    mhpmevent(i) := 0.U
+  }
+
+  // MCYCLE
+  val COUNT_MCYCLE = Module(new BrqCounter(64))
+  COUNT_MCYCLE.io.i_counter_inc := mhpmcounter_incr(0) & ~mcountinhibit(0)
+  COUNT_MCYCLE.io.i_counterh_we := mhpmcounterh_we(0)
+  COUNT_MCYCLE.io.i_counter_we  := mhpmcounter_we(0)
+  COUNT_MCYCLE.io.i_counter_val := csr_wdata_int
+  mhpmcounter(0)                := COUNT_MCYCLE.io.o_counter_val
+
+  // MINSTRET
+  val COUNT_MINSTRET = Module(new BrqCounter(64))
+  COUNT_MINSTRET.io.i_counter_inc := mhpmcounter_incr(2) & ~mcountinhibit(2)
+  COUNT_MINSTRET.io.i_counterh_we := mhpmcounterh_we(2)
+  COUNT_MINSTRET.io.i_counter_we  := mhpmcounter_we(2)
+  COUNT_MINSTRET.io.i_counter_val := csr_wdata_int
+  mhpmcounter(2)                  := COUNT_MINSTRET.io.o_counter_val
+
+  // reserved
+  mhpmcounter(1) := 0.U
+  val MHPMCounterNum: Int = 10
+  for(cnt <- 0 until 10)
+  {
+    val MCOUNTER = Module(new BrqCounter(40))
+
+    MCOUNTER.io.i_counter_inc := mhpmcounter_incr(cnt+3) & ~mcountinhibit(cnt + 3)
+    MCOUNTER.io.i_counterh_we := mhpmcounterh_we(cnt+ 3)
+    MCOUNTER.io.i_counter_we  := mhpmcounter_we(cnt + 3)
+    MCOUNTER.io.i_counter_val := csr_wdata_int
+    mhpmcounter(cnt + 3)      := MCOUNTER.io.o_counter_val
+  }
+
+  if(MHPMCounterNum < 29)
+  {
+    val unused_mhpmcounter_we = dontTouch(Wire(UInt((29-MHPMCounterNum).W)))
+    val unused_mhpmcounterh_we= Wire(UInt((29-MHPMCounterNum).W))
+    val unused_mhpmcounter_incr= Wire(UInt((29-MHPMCounterNum).W))
+
+    mcountinhibit := Cat("b1".U((29-MHPMCounterNum).W), mcountinhibit_q)
+
+    unused_mhpmcounter_we  := mhpmcounter_we(31,MHPMCounterNum+3)
+    unused_mhpmcounterh_we := mhpmcounterh_we(31,MHPMCounterNum+3)
+    unused_mhpmcounter_incr:= mhpmcounter_incr(31,MHPMCounterNum+3)
+  }
+  else
+  {
+    mcountinhibit := mcountinhibit_q
+  }
+
+  mcountinhibit_q := mcountinhibit_d
+  /////////////////////////////
+  // Debug trigger registers //
+  /////////////////////////////
+
+  if(DbgTriggerEn == 1)
+  {
+    val DbgHwNumLen = 1 //DbgHwBreakNum > 1 ? log2Ceil(DbgHwBreakNum): 1
+
+    val tselect_d, tselect_q = Wire(UInt(DbgHwNumLen.W))
+    val tmatch_control_d     = Wire(Bool())
+    val tmatch_control_q     = Wire(UInt(DbgHwBreakNum.W))
+    val tmatch_value_d       = Wire(UInt(32.W))
+    val tmatch_value_q       = Wire(UInt(32.W))
+
+    // write enable
+
+    val tselect_we        = Wire(Bool())
+    val tmatch_control_we = Wire(UInt(DbgHwBreakNum.W))
+    val tmatch_value_we   = Wire(UInt(DbgHwBreakNum.W))
+
+    // trigger comparison result
+
+    val trigger_match  = Wire(UInt(DbgHwBreakNum.W))
+
+    // write select
+
+    tselect_we := csr_we_int & io.i_debug_mode & (io.i_csr_addr.asUInt === CsrAddressMap.TSELECT)
+
+    tmatch_control_we := csr_we_int & io.i_debug_mode & (io.i_csr_addr.asUInt === CsrAddressMap.TDATA1)
+    tmatch_value_we   := csr_we_int & io.i_debug_mode & (io.i_csr_addr.asUInt === CsrAddressMap.TDATA2)
+
+    // Debug interface tests the available number of triggers by writing and reading the trigger
+    // select register. Only allow changes to the register if it is within the supported region.
+
+    tselect_d := Mux(csr_wdata_int < DbgHwBreakNum.asUInt, csr_wdata_int(DbgTriggerEn), (DbgHwBreakNum-1).asUInt)
+
+    tmatch_control_d := csr_wdata_int(2)
+    tmatch_value_d   := csr_wdata_int(31,0)
+
+    // Registers
+    val PRIM_TSELECT = Module(new CsrPrimitive(DbgHwNumLen, false, 0))
+    PRIM_TSELECT.io.i_wrdata := tselect_d
+    PRIM_TSELECT.io.i_wr_en   := tselect_we
+    tselect_q                 := PRIM_TSELECT.io.o_rd_data
+
+    val PRIM_TM_CONTROL = Module(new CsrPrimitive(1,false,0))
+    PRIM_TM_CONTROL.io.i_wrdata := tmatch_value_d
+    PRIM_TM_CONTROL.io.i_wr_en   := tmatch_value_we
+    tmatch_value_q               := PRIM_TM_CONTROL.io.o_rd_data
+
+    // Assign read data
+    // TSELECT - number of supported triggers defined by parameter DbgHwBreakNum
+    tselect_rdata := Cat(0.U, tselect_q)
+    // TDATA0 - only support simple address matching
+
+    tmatch_control_rdata := Cat("b2".U(2.W), "b1".U, "b0".U(6.W), "b0".U, "b0".U, "b0".U, "b00".U, "b1".U(4.W), "b0".U, "b0".U(4.W), "b1".U, "b0".U, "b0".U, "b1".U, tmatch_control_q(1), "b0".U, "b0".U)
+
+    // TDATA1 - address match value only
+
+    tmatch_value_rdata := tmatch_value_q(1)
+    // Breakpoint matching
+    // We match against the next address, as the breakpoint must be taken before execution
+    trigger_match := tmatch_control_q & (io.i_pc_if === tmatch_value_q)
+
+    io.o_trigger_match := trigger_match.orR
+  }
+  else
+  {
+    tselect_rdata        := 0.U
+    tmatch_control_rdata := 0.U
+    tmatch_value_rdata   := 0.U
+    io.o_trigger_match   := 0.U
+  }
+}
diff --git a/chisel/Buraq-mini/RV32i/src/test/resources/in.wav b/chisel/Buraq-mini/RV32i/src/test/resources/in.wav
new file mode 100644
index 0000000..d105d00
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/test/resources/in.wav
Binary files differ
diff --git a/chisel/Buraq-mini/RV32i/src/test/scala/core/AluControlTests.scala b/chisel/Buraq-mini/RV32i/src/test/scala/core/AluControlTests.scala
new file mode 100644
index 0000000..3538192
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/test/scala/core/AluControlTests.scala
@@ -0,0 +1,11 @@
+package core
+
+import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
+
+class AluControlTests(c: AluControl) extends PeekPokeTester(c) {
+    poke(c.io.aluOp, 2)
+    poke(c.io.func3, 7)
+    poke(c.io.func7, 0)
+    step(1)
+    expect(c.io.output, 23)
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/test/scala/core/AluTests.scala b/chisel/Buraq-mini/RV32i/src/test/scala/core/AluTests.scala
new file mode 100644
index 0000000..8a0fa1c
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/test/scala/core/AluTests.scala
@@ -0,0 +1,12 @@
+package core
+
+import chisel3.iotesters.PeekPokeTester
+
+class AluTests(c: Alu) extends PeekPokeTester(c) {
+    poke(c.io.oper_a, -3)
+    poke(c.io.oper_b, -1)
+    poke(c.io.aluCtrl, 0)
+    step(1)
+    expect(c.io.output, -4)
+ //   expect(c.io.branch, 0)
+}
\ No newline at end of file
diff --git a/chisel/Buraq-mini/RV32i/src/test/scala/core/BranchLogicTests.scala b/chisel/Buraq-mini/RV32i/src/test/scala/core/BranchLogicTests.scala
new file mode 100644
index 0000000..d6feb0b
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/test/scala/core/BranchLogicTests.scala
@@ -0,0 +1,10 @@
+package core
+import chisel3.iotesters.PeekPokeTester
+
+class BranchLogicTests(c: BranchLogic) extends PeekPokeTester(c) {
+  poke(c.io.in_rs1, -2)
+  poke(c.io.in_rs2, -5)
+  poke(c.io.in_func3, 4)
+  step(1)
+  expect(c.io.output, 0)
+}
diff --git a/chisel/Buraq-mini/RV32i/src/test/scala/core/ControlDecodeTests.scala b/chisel/Buraq-mini/RV32i/src/test/scala/core/ControlDecodeTests.scala
new file mode 100644
index 0000000..59cf284
--- /dev/null
+++ b/chisel/Buraq-mini/RV32i/src/test/scala/core/ControlDecodeTests.scala