|author||hadirkhan10 <firstname.lastname@example.org>||Tue Dec 15 06:44:43 2020 +0000|
|committer||hadirkhan10 <email@example.com>||Tue Dec 15 06:44:43 2020 +0000|
Merge branch 'master' of https://github.com/hadirkhan10/ibtida-soc
An Soc designed to be included inside the Caravel, a template SoC for Google SKY130 free shuttles.
ابتدا means the start of something. This is a minimal SoC built around a RISC-V based 5 stage pipelined core Buraq-Mini. Both the SoC and the core are made from scratch using CHISEL HDL. The CHISEL source code as well as the emitted verilog are provided in the relvant folders. It is still Work In Progress (WIP). The current SoC architecture is given below.
Chisel source code is available here:
chisel/ ├── Buraq-Mini (core source) │ │–– RV32i │ └── src │–– TileLink (bus source) │ └── src └── src (SoC source)
The emitted verilog is present here:
verilog/ ├── rtl │ ├──ibtida-soc │ │ └── Ibtida_top_dffram_cv.v
The synthesized netlist is present here:
verilog/ ├── gl │ └── Ibtida_top_dffram_cv.v
The hardened macros are placed here:
def/ └── Ibtida_top_dffram_cv.def.gz
lef/ └── Ibtida_top_dffram_cv.lef
gds/ └── Ibtida_top_dffram_cv.gds.gz
:heavy_check_mark: Change the repo name to integrate “caravel_”.
:heavy_check_mark: Update the project with the caravel mpw-one-a branch.
:heavy_check_mark: Update the openlane with the mpw-one-a branch.
:heavy_check_mark: Verify the synthesized netlist.
:heavy_check_mark: Harden the design macro with 0 drc/lvs violations.
:x: Harden the user project wrapper with 0 drc/lvs violations.
:heavy_check_mark: On-board the user project to Caravel.
:x: Pass all the pre-checks.
:x: Update the request to “Submitter Confirmed”.
Main contributors are: