Merge pull request #8 from ax3ghazy/new_dimensions

Merging recent changes that include changes to dimensions, LVS clean chip_io, initial routing for caravel, Makefile, etc.
tree: 31b828b9f9333b2fc86ffcb7e7bce25cc7d2cc78
  1. LICENSE
  2. Makefile
  3. README.md
  4. def/
  5. doc/
  6. gds/
  7. info.yaml
  8. lef/
  9. macros/
  10. mag/
  11. openlane/
  12. scripts/
  13. spi/
  14. verilog/
README.md

CIIC Harness

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware that can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC can be found here

Mega Project Area

This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.