blob: 315893bcf17c63f6e82b60f2641c72ab64ec64bc [file] [log] [blame]
module Rx(
input clock,
input reset,
input [15:0] io_CLK_PER_BIT,
input io_rxd,
output io_valid,
output [7:0] io_data
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
reg [2:0] stateReg; // @[Rx.scala 19:25]
reg [7:0] clockCount; // @[Rx.scala 21:27]
reg [3:0] bitIndex; // @[Rx.scala 22:25]
reg validReg; // @[Rx.scala 23:25]
reg _T; // @[Rx.scala 25:30]
reg rxReg; // @[Rx.scala 25:22]
reg [7:0] shiftReg; // @[Rx.scala 26:25]
wire _T_1 = 3'h0 == stateReg; // @[Conditional.scala 37:30]
wire _T_2 = ~io_rxd; // @[Rx.scala 34:19]
wire _T_3 = 3'h1 == stateReg; // @[Conditional.scala 37:30]
wire [31:0] CLCK_PER_BIT = {{16'd0}, io_CLK_PER_BIT}; // @[Rx.scala 15:36 Rx.scala 16:16]
wire [31:0] _T_5 = CLCK_PER_BIT - 32'h1; // @[Rx.scala 42:42]
wire [31:0] _T_6 = _T_5 / 32'h2; // @[Rx.scala 42:49]
wire [31:0] _GEN_34 = {{24'd0}, clockCount}; // @[Rx.scala 42:23]
wire _T_7 = _GEN_34 == _T_6; // @[Rx.scala 42:23]
wire [7:0] _T_10 = clockCount + 8'h1; // @[Rx.scala 50:34]
wire _T_11 = 3'h2 == stateReg; // @[Conditional.scala 37:30]
wire _T_14 = _GEN_34 < _T_5; // @[Rx.scala 56:23]
wire [7:0] _T_18 = {rxReg,shiftReg[7:1]}; // @[Cat.scala 29:58]
wire _T_19 = bitIndex < 4'h7; // @[Rx.scala 64:23]
wire [3:0] _T_21 = bitIndex + 4'h1; // @[Rx.scala 65:32]
wire _T_22 = 3'h3 == stateReg; // @[Conditional.scala 37:30]
wire _T_28 = 3'h4 == stateReg; // @[Conditional.scala 37:30]
assign io_valid = validReg; // @[Rx.scala 93:12]
assign io_data = shiftReg; // @[Rx.scala 91:11]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
stateReg = _RAND_0[2:0];
_RAND_1 = {1{`RANDOM}};
clockCount = _RAND_1[7:0];
_RAND_2 = {1{`RANDOM}};
bitIndex = _RAND_2[3:0];
_RAND_3 = {1{`RANDOM}};
validReg = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
_T = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
rxReg = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
shiftReg = _RAND_6[7:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
stateReg <= 3'h0;
end else if (_T_1) begin
if (_T_2) begin
stateReg <= 3'h1;
end else begin
stateReg <= 3'h0;
end
end else if (_T_3) begin
if (_T_7) begin
if (_T_2) begin
stateReg <= 3'h2;
end else begin
stateReg <= 3'h0;
end
end else begin
stateReg <= 3'h1;
end
end else if (_T_11) begin
if (_T_14) begin
stateReg <= 3'h2;
end else if (_T_19) begin
stateReg <= 3'h2;
end else begin
stateReg <= 3'h3;
end
end else if (_T_22) begin
if (_T_14) begin
stateReg <= 3'h3;
end else begin
stateReg <= 3'h4;
end
end else if (_T_28) begin
stateReg <= 3'h0;
end
if (reset) begin
clockCount <= 8'h0;
end else if (_T_1) begin
clockCount <= 8'h0;
end else if (_T_3) begin
if (_T_7) begin
if (_T_2) begin
clockCount <= 8'h0;
end
end else begin
clockCount <= _T_10;
end
end else if (_T_11) begin
if (_T_14) begin
clockCount <= _T_10;
end else begin
clockCount <= 8'h0;
end
end else if (_T_22) begin
if (_T_14) begin
clockCount <= _T_10;
end else begin
clockCount <= 8'h0;
end
end
if (reset) begin
bitIndex <= 4'h0;
end else if (_T_1) begin
bitIndex <= 4'h0;
end else if (!(_T_3)) begin
if (_T_11) begin
if (!(_T_14)) begin
if (_T_19) begin
bitIndex <= _T_21;
end else begin
bitIndex <= 4'h0;
end
end
end
end
if (reset) begin
validReg <= 1'h0;
end else if (_T_1) begin
validReg <= 1'h0;
end else if (!(_T_3)) begin
if (!(_T_11)) begin
if (_T_22) begin
if (!(_T_14)) begin
validReg <= 1'h1;
end
end else if (_T_28) begin
validReg <= 1'h0;
end
end
end
_T <= reset | io_rxd;
rxReg <= reset | _T;
if (reset) begin
shiftReg <= 8'h41;
end else if (!(_T_1)) begin
if (!(_T_3)) begin
if (_T_11) begin
if (!(_T_14)) begin
shiftReg <= _T_18;
end
end
end
end
end
endmodule
module UartController(
input clock,
input reset,
input io_isStalled,
output [31:0] io_rx_data_o,
output [7:0] io_addr_o,
input [15:0] io_CLK_PER_BIT,
input io_rxd,
output io_valid,
output io_done
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
`endif // RANDOMIZE_REG_INIT
// wire rx_clock; // @[UartController.scala 25:18]
// wire rxreset; // @[UartController.scala 25:18]
wire [15:0] rx_io_CLK_PER_BIT; // @[UartController.scala 25:18]
wire rx_io_rxd; // @[UartController.scala 25:18]
wire rx_io_valid; // @[UartController.scala 25:18]
wire [7:0] rx_io_data; // @[UartController.scala 25:18]
reg regDone; // @[UartController.scala 19:24]
reg [2:0] count; // @[UartController.scala 20:22]
reg [31:0] regFinalData; // @[UartController.scala 21:29]
reg [13:0] regAddr; // @[UartController.scala 22:24]
reg regValid; // @[UartController.scala 23:25]
reg [7:0] dataReg; // @[UartController.scala 30:24]
reg [7:0] regLSB1; // @[UartController.scala 31:24]
reg [7:0] regLSB2; // @[UartController.scala 32:24]
reg [7:0] regMSB1; // @[UartController.scala 33:24]
wire _T = ~regDone; // @[UartController.scala 36:24]
wire _T_1 = io_isStalled & _T; // @[UartController.scala 36:21]
wire _T_2 = rx_io_valid; // @[UartController.scala 37:22]
wire [2:0] _T_4 = count + 3'h1; // @[UartController.scala 41:22]
wire _T_5 = 3'h1 == count; // @[Conditional.scala 37:30]
wire _T_6 = 3'h2 == count; // @[Conditional.scala 37:30]
wire _T_7 = 3'h3 == count; // @[Conditional.scala 37:30]
wire _T_8 = 3'h4 == count; // @[Conditional.scala 37:30]
wire [31:0] _T_11 = {dataReg,regMSB1,regLSB2,regLSB1}; // @[Cat.scala 29:58]
wire _T_12 = _T_11 == 32'hfff; // @[UartController.scala 58:17]
wire [13:0] _T_14 = regAddr + 14'h1; // @[UartController.scala 65:28]
wire _GEN_6 = _T_12 | regDone; // @[UartController.scala 58:36]
wire _T_15 = count == 3'h4; // @[UartController.scala 72:14]
Rx rx ( // @[UartController.scala 25:18]
.clock(clock),
.reset(reset),
.io_CLK_PER_BIT(rx_io_CLK_PER_BIT),
.io_rxd(rx_io_rxd),
.io_valid(rx_io_valid),
.io_data(rx_io_data)
);
assign io_rx_data_o = regFinalData; // @[UartController.scala 77:16]
assign io_addr_o = regAddr[7:0]; // @[UartController.scala 76:13]
assign io_valid = regValid; // @[UartController.scala 78:12]
assign io_done = regDone; // @[UartController.scala 79:11]
//assign rx_clock = clock;
//assign rxreset = reset;
assign rx_io_CLK_PER_BIT = io_CLK_PER_BIT; // @[UartController.scala 27:21]
assign rx_io_rxd = io_rxd; // @[UartController.scala 28:13]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
regDone = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
count = _RAND_1[2:0];
_RAND_2 = {1{`RANDOM}};
regFinalData = _RAND_2[31:0];
_RAND_3 = {1{`RANDOM}};
regAddr = _RAND_3[13:0];
_RAND_4 = {1{`RANDOM}};
regValid = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
dataReg = _RAND_5[7:0];
_RAND_6 = {1{`RANDOM}};
regLSB1 = _RAND_6[7:0];
_RAND_7 = {1{`RANDOM}};
regLSB2 = _RAND_7[7:0];
_RAND_8 = {1{`RANDOM}};
regMSB1 = _RAND_8[7:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
regDone <= 1'h0;
end else if (!(_T_5)) begin
if (!(_T_6)) begin
if (!(_T_7)) begin
if (_T_8) begin
regDone <= _GEN_6;
end
end
end
end
if (reset) begin
count <= 3'h0;
end else if (_T_15) begin
count <= 3'h0;
end else if (_T_1) begin
if (_T_2) begin
count <= _T_4;
end
end
if (reset) begin
regFinalData <= 32'h0;
end else if (!(_T_5)) begin
if (!(_T_6)) begin
if (!(_T_7)) begin
if (_T_8) begin
if (_T_12) begin
regFinalData <= 32'h0;
end else begin
regFinalData <= _T_11;
end
end
end
end
end
if (reset) begin
regAddr <= 14'h3fff;
end else if (!(_T_5)) begin
if (!(_T_6)) begin
if (!(_T_7)) begin
if (_T_8) begin
if (_T_12) begin
regAddr <= 14'h0;
end else begin
regAddr <= _T_14;
end
end
end
end
end
if (reset) begin
regValid <= 1'h0;
end else if (_T_5) begin
if (_T_1) begin
if (_T_2) begin
regValid <= 1'h0;
end
end
end else if (_T_6) begin
if (_T_1) begin
if (_T_2) begin
regValid <= 1'h0;
end
end
end else if (_T_7) begin
if (_T_1) begin
if (_T_2) begin
regValid <= 1'h0;
end
end
end else if (_T_8) begin
if (_T_12) begin
regValid <= 1'h0;
end else begin
regValid <= 1'h1;
end
end else if (_T_1) begin
if (_T_2) begin
regValid <= 1'h0;
end
end
if (reset) begin
dataReg <= 8'h0;
end else if (_T_1) begin
if (_T_2) begin
dataReg <= rx_io_data;
end
end
if (reset) begin
regLSB1 <= 8'h0;
end else if (_T_5) begin
regLSB1 <= dataReg;
end
if (reset) begin
regLSB2 <= 8'h0;
end else if (!(_T_5)) begin
if (_T_6) begin
regLSB2 <= dataReg;
end
end
if (reset) begin
regMSB1 <= 8'h0;
end else if (!(_T_5)) begin
if (!(_T_6)) begin
if (_T_7) begin
regMSB1 <= dataReg;
end
end
end
end
endmodule
module ID_EX(
input clock,
input reset,
input [31:0] io_pc_in,
input [31:0] io_pc4_in,
input [4:0] io_rs1_sel_in,
input [4:0] io_rs2_sel_in,
input [31:0] io_rs1_in,
input [31:0] io_rs2_in,
input [31:0] io_imm,
input [4:0] io_rd_sel_in,
input [2:0] io_func3_in,
input [6:0] io_func7_in,
input io_ctrl_MemWr_in,
input io_ctrl_MemRd_in,
input io_ctrl_CsrWen_in,
input io_ctrl_RegWr_in,
input io_ctrl_MemToReg_in,
input [3:0] io_ctrl_AluOp_in,
input [1:0] io_ctrl_OpA_sel_in,
input io_ctrl_OpB_sel_in,
input [6:0] io_inst_op_in,
input [31:0] io_csr_data_i,
input io_stall,
output [31:0] io_pc_out,
output [31:0] io_pc4_out,
output [31:0] io_rs1_out,
output [31:0] io_rs2_out,
output [31:0] io_imm_out,
output [2:0] io_func3_out,
output [6:0] io_func7_out,
output [6:0] io_inst_op_out,
output [4:0] io_rd_sel_out,
output [4:0] io_rs1_sel_out,
output [4:0] io_rs2_sel_out,
output io_ctrl_MemWr_out,
output io_ctrl_MemRd_out,
output io_ctrl_RegWr_out,
output io_ctrl_CsrWen_out,
output io_ctrl_MemToReg_out,
output [3:0] io_ctrl_AluOp_out,
output [1:0] io_ctrl_OpA_sel_out,
output io_ctrl_OpB_sel_out,
output [31:0] io_csr_data_o
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
reg [31:0] _RAND_11;
reg [31:0] _RAND_12;
reg [31:0] _RAND_13;
reg [31:0] _RAND_14;
reg [31:0] _RAND_15;
reg [31:0] _RAND_16;
reg [31:0] _RAND_17;
reg [31:0] _RAND_18;
reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
reg [31:0] pc_reg; // @[ID_EX.scala 59:25]
reg [31:0] pc4_reg; // @[ID_EX.scala 60:26]
reg [31:0] rs1_reg; // @[ID_EX.scala 61:26]
reg [31:0] rs2_reg; // @[ID_EX.scala 62:26]
reg [31:0] imm_reg; // @[ID_EX.scala 63:26]
reg [4:0] rd_sel_reg; // @[ID_EX.scala 64:29]
reg [4:0] rs1_sel_reg; // @[ID_EX.scala 65:30]
reg [4:0] rs2_sel_reg; // @[ID_EX.scala 66:30]
reg [2:0] func3_reg; // @[ID_EX.scala 67:28]
reg [6:0] func7_reg; // @[ID_EX.scala 68:28]
reg [6:0] inst_op_reg; // @[ID_EX.scala 69:30]
reg [31:0] csr_data_reg; // @[ID_EX.scala 71:31]
reg ctrl_MemWr_reg; // @[ID_EX.scala 73:33]
reg ctrl_MemRd_reg; // @[ID_EX.scala 74:33]
reg ctrl_RegWr_reg; // @[ID_EX.scala 76:33]
reg ctrl_CsrWen_reg; // @[ID_EX.scala 77:34]
reg ctrl_MemToReg_reg; // @[ID_EX.scala 78:36]
reg [3:0] ctrl_AluOp_reg; // @[ID_EX.scala 79:33]
reg [1:0] ctrl_OpA_sel_reg; // @[ID_EX.scala 80:35]
reg ctrl_OpB_sel_reg; // @[ID_EX.scala 81:35]
wire _T = ~io_stall; // @[ID_EX.scala 85:19]
assign io_pc_out = pc_reg; // @[ID_EX.scala 113:19 ID_EX.scala 140:19]
assign io_pc4_out = pc4_reg; // @[ID_EX.scala 114:20 ID_EX.scala 141:20]
assign io_rs1_out = rs1_reg; // @[ID_EX.scala 115:20 ID_EX.scala 142:20]
assign io_rs2_out = rs2_reg; // @[ID_EX.scala 116:20 ID_EX.scala 143:20]
assign io_imm_out = imm_reg; // @[ID_EX.scala 118:20 ID_EX.scala 145:20]
assign io_func3_out = func3_reg; // @[ID_EX.scala 122:22 ID_EX.scala 149:22]
assign io_func7_out = func7_reg; // @[ID_EX.scala 123:22 ID_EX.scala 150:22]
assign io_inst_op_out = inst_op_reg; // @[ID_EX.scala 124:24 ID_EX.scala 151:24]
assign io_rd_sel_out = rd_sel_reg; // @[ID_EX.scala 119:23 ID_EX.scala 146:23]
assign io_rs1_sel_out = rs1_sel_reg; // @[ID_EX.scala 120:24 ID_EX.scala 147:24]
assign io_rs2_sel_out = rs2_sel_reg; // @[ID_EX.scala 121:24 ID_EX.scala 148:24]
assign io_ctrl_MemWr_out = ctrl_MemWr_reg; // @[ID_EX.scala 126:27 ID_EX.scala 154:27]
assign io_ctrl_MemRd_out = ctrl_MemRd_reg; // @[ID_EX.scala 127:27 ID_EX.scala 155:27]
assign io_ctrl_RegWr_out = ctrl_RegWr_reg; // @[ID_EX.scala 129:27 ID_EX.scala 157:27]
assign io_ctrl_CsrWen_out = ctrl_CsrWen_reg; // @[ID_EX.scala 130:28 ID_EX.scala 158:28]
assign io_ctrl_MemToReg_out = ctrl_MemToReg_reg; // @[ID_EX.scala 131:30 ID_EX.scala 159:30]
assign io_ctrl_AluOp_out = ctrl_AluOp_reg; // @[ID_EX.scala 132:27 ID_EX.scala 160:27]
assign io_ctrl_OpA_sel_out = ctrl_OpA_sel_reg; // @[ID_EX.scala 133:29 ID_EX.scala 161:29]
assign io_ctrl_OpB_sel_out = ctrl_OpB_sel_reg; // @[ID_EX.scala 134:29 ID_EX.scala 162:29]
assign io_csr_data_o = csr_data_reg; // @[ID_EX.scala 117:23 ID_EX.scala 144:23]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
pc_reg = _RAND_0[31:0];
_RAND_1 = {1{`RANDOM}};
pc4_reg = _RAND_1[31:0];
_RAND_2 = {1{`RANDOM}};
rs1_reg = _RAND_2[31:0];
_RAND_3 = {1{`RANDOM}};
rs2_reg = _RAND_3[31:0];
_RAND_4 = {1{`RANDOM}};
imm_reg = _RAND_4[31:0];
_RAND_5 = {1{`RANDOM}};
rd_sel_reg = _RAND_5[4:0];
_RAND_6 = {1{`RANDOM}};
rs1_sel_reg = _RAND_6[4:0];
_RAND_7 = {1{`RANDOM}};
rs2_sel_reg = _RAND_7[4:0];
_RAND_8 = {1{`RANDOM}};
func3_reg = _RAND_8[2:0];
_RAND_9 = {1{`RANDOM}};
func7_reg = _RAND_9[6:0];
_RAND_10 = {1{`RANDOM}};
inst_op_reg = _RAND_10[6:0];
_RAND_11 = {1{`RANDOM}};
csr_data_reg = _RAND_11[31:0];
_RAND_12 = {1{`RANDOM}};
ctrl_MemWr_reg = _RAND_12[0:0];
_RAND_13 = {1{`RANDOM}};
ctrl_MemRd_reg = _RAND_13[0:0];
_RAND_14 = {1{`RANDOM}};
ctrl_RegWr_reg = _RAND_14[0:0];
_RAND_15 = {1{`RANDOM}};
ctrl_CsrWen_reg = _RAND_15[0:0];
_RAND_16 = {1{`RANDOM}};
ctrl_MemToReg_reg = _RAND_16[0:0];
_RAND_17 = {1{`RANDOM}};
ctrl_AluOp_reg = _RAND_17[3:0];
_RAND_18 = {1{`RANDOM}};
ctrl_OpA_sel_reg = _RAND_18[1:0];
_RAND_19 = {1{`RANDOM}};
ctrl_OpB_sel_reg = _RAND_19[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
pc_reg <= 32'sh0;
end else if (_T) begin
pc_reg <= io_pc_in;
end
if (reset) begin
pc4_reg <= 32'sh0;
end else if (_T) begin
pc4_reg <= io_pc4_in;
end
if (reset) begin
rs1_reg <= 32'sh0;
end else if (_T) begin
rs1_reg <= io_rs1_in;
end
if (reset) begin
rs2_reg <= 32'sh0;
end else if (_T) begin
rs2_reg <= io_rs2_in;
end
if (reset) begin
imm_reg <= 32'sh0;
end else if (_T) begin
imm_reg <= io_imm;
end
if (reset) begin
rd_sel_reg <= 5'h0;
end else if (_T) begin
rd_sel_reg <= io_rd_sel_in;
end
if (reset) begin
rs1_sel_reg <= 5'h0;
end else if (_T) begin
rs1_sel_reg <= io_rs1_sel_in;
end
if (reset) begin
rs2_sel_reg <= 5'h0;
end else if (_T) begin
rs2_sel_reg <= io_rs2_sel_in;
end
if (reset) begin
func3_reg <= 3'h0;
end else if (_T) begin
func3_reg <= io_func3_in;
end
if (reset) begin
func7_reg <= 7'h0;
end else if (_T) begin
func7_reg <= io_func7_in;
end
if (reset) begin
inst_op_reg <= 7'h0;
end else if (_T) begin
inst_op_reg <= io_inst_op_in;
end
if (reset) begin
csr_data_reg <= 32'h0;
end else if (_T) begin
csr_data_reg <= io_csr_data_i;
end
if (reset) begin
ctrl_MemWr_reg <= 1'h0;
end else if (_T) begin
ctrl_MemWr_reg <= io_ctrl_MemWr_in;
end
if (reset) begin
ctrl_MemRd_reg <= 1'h0;
end else if (_T) begin
ctrl_MemRd_reg <= io_ctrl_MemRd_in;
end
if (reset) begin
ctrl_RegWr_reg <= 1'h0;
end else if (_T) begin
ctrl_RegWr_reg <= io_ctrl_RegWr_in;
end
if (reset) begin
ctrl_CsrWen_reg <= 1'h0;
end else if (_T) begin
ctrl_CsrWen_reg <= io_ctrl_CsrWen_in;
end
if (reset) begin
ctrl_MemToReg_reg <= 1'h0;
end else if (_T) begin
ctrl_MemToReg_reg <= io_ctrl_MemToReg_in;
end
if (reset) begin
ctrl_AluOp_reg <= 4'h0;
end else if (_T) begin
ctrl_AluOp_reg <= io_ctrl_AluOp_in;
end
if (reset) begin
ctrl_OpA_sel_reg <= 2'h0;
end else if (_T) begin
ctrl_OpA_sel_reg <= io_ctrl_OpA_sel_in;
end
if (reset) begin
ctrl_OpB_sel_reg <= 1'h0;
end else if (_T) begin
ctrl_OpB_sel_reg <= io_ctrl_OpB_sel_in;
end
end
endmodule
module EX_MEM(
input clock,
input reset,
input io_ctrl_MemWr_in,
input io_ctrl_MemRd_in,
input io_ctrl_RegWr_in,
input io_ctrl_CsrWen_in,
input io_ctrl_MemToReg_in,
input [31:0] io_rs2_in,
input [4:0] io_rd_sel_in,
input [31:0] io_alu_in,
input [2:0] io_EX_MEM_func3,
input [31:0] io_csr_data_i,
input io_stall,
output io_ctrl_MemWr_out,
output io_ctrl_MemRd_out,
output io_ctrl_RegWr_out,
output io_ctrl_CsrWen_out,
output io_ctrl_MemToReg_out,
output [31:0] io_rs2_out,
output [4:0] io_rd_sel_out,
output [31:0] io_alu_output,
output [2:0] io_EX_MEM_func3_out,
output [31:0] io_csr_data_o
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
`endif // RANDOMIZE_REG_INIT
reg reg_memWr; // @[EX_MEM.scala 37:32]
reg reg_memRd; // @[EX_MEM.scala 38:32]
reg reg_regWr; // @[EX_MEM.scala 39:32]
reg reg_csrWen; // @[EX_MEM.scala 40:33]
reg reg_memToReg; // @[EX_MEM.scala 41:35]
reg [31:0] reg_rs2; // @[EX_MEM.scala 42:30]
reg [4:0] reg_rd_sel; // @[EX_MEM.scala 43:33]
reg [31:0] reg_alu_output; // @[EX_MEM.scala 45:37]
reg [2:0] reg_func3; // @[EX_MEM.scala 46:37]
reg [31:0] reg_csr_data; // @[EX_MEM.scala 49:35]
wire _T = ~io_stall; // @[EX_MEM.scala 51:19]
assign io_ctrl_MemWr_out = reg_memWr; // @[EX_MEM.scala 82:23]
assign io_ctrl_MemRd_out = reg_memRd; // @[EX_MEM.scala 83:23]
assign io_ctrl_RegWr_out = reg_regWr; // @[EX_MEM.scala 84:23]
assign io_ctrl_CsrWen_out = reg_csrWen; // @[EX_MEM.scala 85:24]
assign io_ctrl_MemToReg_out = reg_memToReg; // @[EX_MEM.scala 86:26]
assign io_rs2_out = reg_rs2; // @[EX_MEM.scala 87:16]
assign io_rd_sel_out = reg_rd_sel; // @[EX_MEM.scala 88:19]
assign io_alu_output = reg_alu_output; // @[EX_MEM.scala 90:19]
assign io_EX_MEM_func3_out = reg_func3; // @[EX_MEM.scala 91:25]
assign io_csr_data_o = reg_csr_data; // @[EX_MEM.scala 94:19]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_memWr = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
reg_memRd = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
reg_regWr = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
reg_csrWen = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
reg_memToReg = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
reg_rs2 = _RAND_5[31:0];
_RAND_6 = {1{`RANDOM}};
reg_rd_sel = _RAND_6[4:0];
_RAND_7 = {1{`RANDOM}};
reg_alu_output = _RAND_7[31:0];
_RAND_8 = {1{`RANDOM}};
reg_func3 = _RAND_8[2:0];
_RAND_9 = {1{`RANDOM}};
reg_csr_data = _RAND_9[31:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
reg_memWr <= 1'h0;
end else if (_T) begin
reg_memWr <= io_ctrl_MemWr_in;
end
if (reset) begin
reg_memRd <= 1'h0;
end else if (_T) begin
reg_memRd <= io_ctrl_MemRd_in;
end
if (reset) begin
reg_regWr <= 1'h0;
end else if (_T) begin
reg_regWr <= io_ctrl_RegWr_in;
end
if (reset) begin
reg_csrWen <= 1'h0;
end else if (_T) begin
reg_csrWen <= io_ctrl_CsrWen_in;
end
if (reset) begin
reg_memToReg <= 1'h0;
end else if (_T) begin
reg_memToReg <= io_ctrl_MemToReg_in;
end
if (reset) begin
reg_rs2 <= 32'sh0;
end else if (_T) begin
reg_rs2 <= io_rs2_in;
end
if (reset) begin
reg_rd_sel <= 5'h0;
end else if (_T) begin
reg_rd_sel <= io_rd_sel_in;
end
if (reset) begin
reg_alu_output <= 32'sh0;
end else if (_T) begin
reg_alu_output <= io_alu_in;
end
if (reset) begin
reg_func3 <= 3'h0;
end else if (_T) begin
reg_func3 <= io_EX_MEM_func3;
end
if (reset) begin
reg_csr_data <= 32'h0;
end else if (_T) begin
reg_csr_data <= io_csr_data_i;
end
end
endmodule
module MEM_WB(
input clock,
input reset,
input io_ctrl_RegWr_in,
input io_ctrl_CsrWen_in,
input io_ctrl_MemToReg_in,
input [4:0] io_rd_sel_in,
input io_ctrl_MemRd_in,
input [31:0] io_dmem_data_in,
input [31:0] io_alu_in,
input [31:0] io_csr_data_in,
input io_stall,
output io_ctrl_RegWr_out,
output io_ctrl_CsrWen_out,
output io_ctrl_MemToReg_out,
output io_ctrl_MemRd_out,
output [4:0] io_rd_sel_out,
output [31:0] io_dmem_data_out,
output [31:0] io_alu_output,
output [31:0] io_csr_data_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
reg reg_regWr; // @[MEM_WB.scala 32:28]
reg reg_csrWen; // @[MEM_WB.scala 34:29]
reg reg_memToReg; // @[MEM_WB.scala 36:31]
reg reg_memRd; // @[MEM_WB.scala 38:28]
reg [4:0] reg_rdSel; // @[MEM_WB.scala 40:28]
reg [31:0] reg_dataMem_data; // @[MEM_WB.scala 42:35]
reg [31:0] reg_alu_output; // @[MEM_WB.scala 44:33]
reg [31:0] reg_csr_data; // @[MEM_WB.scala 50:31]
wire _T = ~io_stall; // @[MEM_WB.scala 52:19]
assign io_ctrl_RegWr_out = reg_regWr; // @[MEM_WB.scala 65:27 MEM_WB.scala 76:27]
assign io_ctrl_CsrWen_out = reg_csrWen; // @[MEM_WB.scala 66:28 MEM_WB.scala 77:28]
assign io_ctrl_MemToReg_out = reg_memToReg; // @[MEM_WB.scala 64:30 MEM_WB.scala 75:30]
assign io_ctrl_MemRd_out = reg_memRd; // @[MEM_WB.scala 67:27 MEM_WB.scala 78:27]
assign io_rd_sel_out = reg_rdSel; // @[MEM_WB.scala 68:23 MEM_WB.scala 79:23]
assign io_dmem_data_out = reg_dataMem_data; // @[MEM_WB.scala 69:26 MEM_WB.scala 80:26]
assign io_alu_output = reg_alu_output; // @[MEM_WB.scala 70:23 MEM_WB.scala 81:23]
assign io_csr_data_out = reg_csr_data; // @[MEM_WB.scala 73:25 MEM_WB.scala 84:25]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_regWr = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
reg_csrWen = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
reg_memToReg = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
reg_memRd = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
reg_rdSel = _RAND_4[4:0];
_RAND_5 = {1{`RANDOM}};
reg_dataMem_data = _RAND_5[31:0];
_RAND_6 = {1{`RANDOM}};
reg_alu_output = _RAND_6[31:0];
_RAND_7 = {1{`RANDOM}};
reg_csr_data = _RAND_7[31:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
reg_regWr <= 1'h0;
end else if (_T) begin
reg_regWr <= io_ctrl_RegWr_in;
end
if (reset) begin
reg_csrWen <= 1'h0;
end else if (_T) begin
reg_csrWen <= io_ctrl_CsrWen_in;
end
if (reset) begin
reg_memToReg <= 1'h0;
end else if (_T) begin
reg_memToReg <= io_ctrl_MemToReg_in;
end
if (reset) begin
reg_memRd <= 1'h0;
end else if (_T) begin
reg_memRd <= io_ctrl_MemRd_in;
end
if (reset) begin
reg_rdSel <= 5'h0;
end else if (_T) begin
reg_rdSel <= io_rd_sel_in;
end
if (reset) begin
reg_dataMem_data <= 32'sh0;
end else if (_T) begin
reg_dataMem_data <= io_dmem_data_in;
end
if (reset) begin
reg_alu_output <= 32'sh0;
end else if (_T) begin
reg_alu_output <= io_alu_in;
end
if (reset) begin
reg_csr_data <= 32'h0;
end else if (_T) begin
reg_csr_data <= io_csr_data_in;
end
end
endmodule
module Pc(
input clock,
input reset,
input [31:0] io_in,
output [31:0] io_out,
output [31:0] io_pc4
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
wire [31:0] _T_2 = 32'sh30 - 32'sh4; // @[Pc.scala 13:30]
reg [31:0] reg_; // @[Pc.scala 13:18]
assign io_out = reg_; // @[Pc.scala 16:12]
assign io_pc4 = $signed(reg_) + 32'sh4; // @[Pc.scala 15:12]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
reg_ = _RAND_0[31:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
reg_ <= _T_2;
end else begin
reg_ <= io_in;
end
end
endmodule
module Fetch(
input clock,
input reset,
input io_core_instr_gnt_i,
input io_core_instr_rvalid_i,
input [31:0] io_core_instr_rdata_i,
input io_csrRegFile_irq_pending_i,
input io_csrRegFile_csr_mstatus_mie_i,
input [31:0] io_csrRegFile_csr_mtvec_i,
output io_csrRegFile_csr_mtvec_init_o,
output io_csrRegFile_csr_save_cause_o,
output io_csrRegFile_csr_save_if_o,
output [31:0] io_csrRegFile_csr_if_pc_o,
output [5:0] io_csrRegFile_exc_cause_o,
input [31:0] io_csrRegFile_csr_mepc_i,
input io_core_init_mtvec_i,
input [31:0] io_decode_sb_imm_i,
input [31:0] io_decode_uj_imm_i,
input [31:0] io_decode_jalr_imm_i,
input [1:0] io_decode_ctrl_next_pc_sel_i,
input io_decode_ctrl_out_branch_i,
input io_decode_branchLogic_output_i,
input [31:0] io_decode_hazardDetection_pc_i,
input [31:0] io_decode_hazardDetection_inst_i,
input [31:0] io_decode_hazardDetection_current_pc_i,
input io_decode_hazardDetection_pc_forward_i,
input io_decode_hazardDetection_inst_forward_i,
input io_decode_mret_inst_i,
input io_core_stall_i,
output [31:0] io_core_instr_addr_o,
output io_core_instr_req_o,
output [31:0] io_decode_if_id_pc_o,
output [31:0] io_decode_if_id_pc4_o,
output [31:0] io_decode_if_id_inst_o
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
//wire pc_clock; // @[Fetch.scala 94:18]
// wire pcreset; // @[Fetch.scala 94:18]
wire [31:0] pc_io_in; // @[Fetch.scala 94:18]
wire [31:0] pc_io_out; // @[Fetch.scala 94:18]
wire [31:0] pc_io_pc4; // @[Fetch.scala 94:18]
reg [31:0] if_id_pc_reg; // @[Fetch.scala 102:25]
reg [31:0] if_id_pc4_reg; // @[Fetch.scala 103:26]
reg [31:0] if_id_inst_reg; // @[Fetch.scala 104:31]
wire handle_irq = io_csrRegFile_irq_pending_i & io_csrRegFile_csr_mstatus_mie_i; // @[Fetch.scala 107:48]
wire _T_12 = ~io_core_stall_i; // @[Fetch.scala 127:8]
wire _T_13 = ~handle_irq; // @[Fetch.scala 127:28]
wire _T_14 = _T_12 & _T_13; // @[Fetch.scala 127:25]
wire [31:0] _GEN_0 = _T_14 ? $signed(pc_io_out) : $signed(if_id_pc_reg); // @[Fetch.scala 127:38]
wire _T_23 = io_decode_ctrl_next_pc_sel_i == 2'h1; // @[Fetch.scala 163:41]
wire _T_26 = io_decode_branchLogic_output_i & io_decode_ctrl_out_branch_i; // @[Fetch.scala 164:53]
wire [31:0] _GEN_6 = _T_26 ? $signed(io_decode_sb_imm_i) : $signed(pc_io_pc4); // @[Fetch.scala 164:93]
wire _T_27 = io_decode_ctrl_next_pc_sel_i == 2'h2; // @[Fetch.scala 172:47]
wire _T_28 = io_decode_ctrl_next_pc_sel_i == 2'h3; // @[Fetch.scala 177:47]
wire [31:0] _GEN_10 = io_decode_mret_inst_i ? $signed(io_csrRegFile_csr_mepc_i) : $signed(pc_io_pc4); // @[Fetch.scala 182:41]
wire [31:0] _GEN_14 = _T_28 ? $signed(io_decode_jalr_imm_i) : $signed(_GEN_10); // @[Fetch.scala 177:60]
wire [31:0] _GEN_18 = _T_27 ? $signed(io_decode_uj_imm_i) : $signed(_GEN_14); // @[Fetch.scala 172:60]
wire [31:0] _GEN_22 = _T_23 ? $signed(_GEN_6) : $signed(_GEN_18); // @[Fetch.scala 163:54]
wire [31:0] _GEN_26 = io_decode_hazardDetection_pc_forward_i ? $signed(io_decode_hazardDetection_pc_i) : $signed(_GEN_22); // @[Fetch.scala 160:58]
wire _T_31 = _T_12 & handle_irq; // @[Fetch.scala 191:31]
wire [31:0] _T_37 = {io_csrRegFile_csr_mtvec_i[31:8],1'h0,7'h2c}; // @[Fetch.scala 192:123]
wire [31:0] _T_45 = _T_28 ? io_decode_jalr_imm_i : pc_io_out; // @[Fetch.scala 200:12]
wire [31:0] _T_46 = _T_27 ? io_decode_uj_imm_i : _T_45; // @[Fetch.scala 199:10]
wire [31:0] _T_47 = _T_23 ? io_decode_sb_imm_i : _T_46; // @[Fetch.scala 198:37]
wire [31:0] _GEN_30 = _T_31 ? $signed(_T_37) : $signed(pc_io_out); // @[Fetch.scala 191:43]
wire [31:0] _GEN_33 = _T_31 ? _T_47 : 32'h0; // @[Fetch.scala 191:43]
wire [5:0] _GEN_34 = _T_31 ? 6'h2b : 6'h0; // @[Fetch.scala 191:43]
Pc pc ( // @[Fetch.scala 94:18]
.clock(clock),
.reset(reset),
.io_in(pc_io_in),
.io_out(pc_io_out),
.io_pc4(pc_io_pc4)
);
assign io_csrRegFile_csr_mtvec_init_o = io_core_init_mtvec_i; // @[Fetch.scala 114:34]
assign io_csrRegFile_csr_save_cause_o = _T_14 ? 1'h0 : _T_31; // @[Fetch.scala 99:34 Fetch.scala 118:34 Fetch.scala 201:36]
assign io_csrRegFile_csr_save_if_o = _T_14 ? 1'h0 : _T_31; // @[Fetch.scala 97:31 Fetch.scala 117:31 Fetch.scala 194:33]
assign io_csrRegFile_csr_if_pc_o = _T_14 ? 32'h0 : _GEN_33; // @[Fetch.scala 98:29 Fetch.scala 198:31]
assign io_csrRegFile_exc_cause_o = _T_14 ? 6'h0 : _GEN_34; // @[Fetch.scala 119:29 Fetch.scala 202:31]
assign io_core_instr_addr_o = {{18'd0}, pc_io_in[13:0]}; // @[Fetch.scala 121:24]
assign io_core_instr_req_o = io_core_instr_gnt_i; // @[Fetch.scala 123:23]
assign io_decode_if_id_pc_o = if_id_pc_reg; // @[Fetch.scala 209:24]
assign io_decode_if_id_pc4_o = if_id_pc4_reg; // @[Fetch.scala 210:25]
assign io_decode_if_id_inst_o = if_id_inst_reg; // @[Fetch.scala 211:26]
//assign pc_clock = clock;
// assign pcreset = reset;
assign pc_io_in = _T_14 ? $signed(_GEN_26) : $signed(_GEN_30); // @[Fetch.scala 161:16 Fetch.scala 165:20 Fetch.scala 170:20 Fetch.scala 173:18 Fetch.scala 178:18 Fetch.scala 183:18 Fetch.scala 188:18 Fetch.scala 192:14 Fetch.scala 205:16]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
if_id_pc_reg = _RAND_0[31:0];
_RAND_1 = {1{`RANDOM}};
if_id_pc4_reg = _RAND_1[31:0];
_RAND_2 = {1{`RANDOM}};
if_id_inst_reg = _RAND_2[31:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (_T_14) begin
if (io_decode_hazardDetection_pc_forward_i) begin
if (_T_14) begin
if (io_decode_hazardDetection_inst_forward_i) begin
if_id_pc_reg <= io_decode_hazardDetection_current_pc_i;
end else if (_T_14) begin
if_id_pc_reg <= pc_io_out;
end
end else if (_T_14) begin
if_id_pc_reg <= pc_io_out;
end
end else if (_T_23) begin
if (_T_26) begin
if_id_pc_reg <= 32'sh0;
end else if (_T_14) begin
if (io_decode_hazardDetection_inst_forward_i) begin
if_id_pc_reg <= io_decode_hazardDetection_current_pc_i;
end else if (_T_14) begin
if_id_pc_reg <= pc_io_out;
end
end else if (_T_14) begin
if_id_pc_reg <= pc_io_out;
end
end else if (_T_27) begin
if_id_pc_reg <= 32'sh0;
end else if (_T_28) begin
if_id_pc_reg <= 32'sh0;
end else if (io_decode_mret_inst_i) begin
if_id_pc_reg <= 32'sh0;
end else if (_T_14) begin
if (io_decode_hazardDetection_inst_forward_i) begin
if_id_pc_reg <= io_decode_hazardDetection_current_pc_i;
end else begin
if_id_pc_reg <= _GEN_0;
end
end else begin
if_id_pc_reg <= _GEN_0;
end
end else if (_T_14) begin
if (io_decode_hazardDetection_inst_forward_i) begin
if_id_pc_reg <= io_decode_hazardDetection_current_pc_i;
end else begin
if_id_pc_reg <= _GEN_0;
end
end else begin
if_id_pc_reg <= _GEN_0;
end
if (_T_14) begin
if (io_decode_hazardDetection_pc_forward_i) begin
if (_T_14) begin
if_id_pc4_reg <= pc_io_pc4;
end
end else if (_T_23) begin
if (_T_26) begin
if_id_pc4_reg <= 32'sh0;
end else if (_T_14) begin
if_id_pc4_reg <= pc_io_pc4;
end
end else if (_T_27) begin
if_id_pc4_reg <= 32'sh0;
end else if (_T_28) begin
if_id_pc4_reg <= 32'sh0;
end else if (io_decode_mret_inst_i) begin
if_id_pc4_reg <= 32'sh0;
end else if (_T_14) begin
if_id_pc4_reg <= pc_io_pc4;
end
end else if (_T_14) begin
if_id_pc4_reg <= pc_io_pc4;
end
if (reset) begin
if_id_inst_reg <= 32'h13;
end else if (_T_14) begin
if (io_decode_hazardDetection_pc_forward_i) begin
if (_T_14) begin
if (io_decode_hazardDetection_inst_forward_i) begin
if_id_inst_reg <= io_decode_hazardDetection_inst_i;
end else if (io_core_instr_rvalid_i) begin
if_id_inst_reg <= io_core_instr_rdata_i;
end else begin
if_id_inst_reg <= 32'h13;
end
end
end else if (_T_23) begin
if (_T_26) begin
if_id_inst_reg <= 32'h13;
end else if (_T_14) begin
if (io_decode_hazardDetection_inst_forward_i) begin
if_id_inst_reg <= io_decode_hazardDetection_inst_i;
end else if (io_core_instr_rvalid_i) begin
if_id_inst_reg <= io_core_instr_rdata_i;
end else begin
if_id_inst_reg <= 32'h13;
end
end
end else if (_T_27) begin
if_id_inst_reg <= 32'h13;
end else if (_T_28) begin
if_id_inst_reg <= 32'h13;
end else if (io_decode_mret_inst_i) begin
if_id_inst_reg <= 32'h13;
end else if (_T_14) begin
if (io_decode_hazardDetection_inst_forward_i) begin
if_id_inst_reg <= io_decode_hazardDetection_inst_i;
end else if (io_core_instr_rvalid_i) begin
if_id_inst_reg <= io_core_instr_rdata_i;
end else begin
if_id_inst_reg <= 32'h13;
end
end
end else if (_T_31) begin
if_id_inst_reg <= 32'h13;
end else if (_T_14) begin
if (io_decode_hazardDetection_inst_forward_i) begin
if_id_inst_reg <= io_decode_hazardDetection_inst_i;
end else if (io_core_instr_rvalid_i) begin
if_id_inst_reg <= io_core_instr_rdata_i;
end else begin
if_id_inst_reg <= 32'h13;
end
end
end
endmodule
module HazardDetection(
input [31:0] io_IF_ID_INST,
input io_ID_EX_MEMREAD,
input [4:0] io_ID_EX_REGRD,
input [31:0] io_pc_in,
input [31:0] io_current_pc,
input io_IF_ID_MEMREAD,
output io_inst_forward,
output io_pc_forward,
output io_ctrl_forward,
output [31:0] io_inst_out,
output [31:0] io_pc_out,
output [31:0] io_current_pc_out
);
wire [4:0] rs1_sel = io_IF_ID_INST[19:15]; // @[HazardDetection.scala 20:30]
wire [4:0] rs2_sel = io_IF_ID_INST[24:20]; // @[HazardDetection.scala 21:30]
wire _T_2 = io_ID_EX_REGRD == rs1_sel; // @[HazardDetection.scala 24:59]
wire _T_3 = io_ID_EX_MEMREAD & _T_2; // @[HazardDetection.scala 24:40]
wire _T_6 = io_ID_EX_REGRD == rs2_sel; // @[HazardDetection.scala 35:90]
wire _T_7 = _T_2 | _T_6; // @[HazardDetection.scala 35:71]
wire _T_8 = io_ID_EX_MEMREAD & _T_7; // @[HazardDetection.scala 35:38]
assign io_inst_forward = io_IF_ID_MEMREAD ? _T_3 : _T_8; // @[HazardDetection.scala 48:23 HazardDetection.scala 57:21 HazardDetection.scala 48:23 HazardDetection.scala 57:21]
assign io_pc_forward = io_IF_ID_MEMREAD ? _T_3 : _T_8; // @[HazardDetection.scala 49:21 HazardDetection.scala 58:19 HazardDetection.scala 49:21 HazardDetection.scala 58:19]
assign io_ctrl_forward = io_IF_ID_MEMREAD ? _T_3 : _T_8; // @[HazardDetection.scala 50:23 HazardDetection.scala 59:21 HazardDetection.scala 50:23 HazardDetection.scala 59:21]
assign io_inst_out = io_IF_ID_INST; // @[HazardDetection.scala 51:19 HazardDetection.scala 60:17 HazardDetection.scala 51:19 HazardDetection.scala 60:17]
assign io_pc_out = io_pc_in; // @[HazardDetection.scala 52:17 HazardDetection.scala 61:15 HazardDetection.scala 52:17 HazardDetection.scala 61:15]
assign io_current_pc_out = io_current_pc; // @[HazardDetection.scala 53:25 HazardDetection.scala 62:23 HazardDetection.scala 53:25 HazardDetection.scala 62:23]
endmodule
module InstructionTypeDecode(
input [2:0] io_func3,
input [6:0] io_func7,
input [6:0] io_opcode,
output io_r_type,
output io_load_type,
output io_s_type,
output io_sb_type,
output io_i_type,
output io_jalr_type,
output io_jal_type,
output io_lui_type,
output io_Auipc,
output io_multiply,
output io_csr_imm_type,
output io_csr_type,
output [1:0] io_csr_op
);
wire _T = io_opcode == 7'h33; // @[InstructionTypeDecode.scala 27:20]
wire _T_1 = io_func7 == 7'h1; // @[InstructionTypeDecode.scala 29:23]
wire _GEN_1 = _T_1 ? 1'h0 : 1'h1; // @[InstructionTypeDecode.scala 30:9]
wire _T_2 = io_opcode == 7'h3; // @[InstructionTypeDecode.scala 39:25]
wire _T_3 = io_opcode == 7'h23; // @[InstructionTypeDecode.scala 41:27]
wire _T_4 = io_opcode == 7'h63; // @[InstructionTypeDecode.scala 43:27]
wire _T_5 = io_opcode == 7'h13; // @[InstructionTypeDecode.scala 45:27]
wire _T_6 = io_opcode == 7'h67; // @[InstructionTypeDecode.scala 47:27]
wire _T_7 = io_opcode == 7'h6f; // @[InstructionTypeDecode.scala 49:27]
wire _T_8 = io_opcode == 7'h37; // @[InstructionTypeDecode.scala 51:27]
wire _T_9 = io_opcode == 7'h17; // @[InstructionTypeDecode.scala 54:26]
wire _T_10 = io_opcode == 7'h73; // @[InstructionTypeDecode.scala 56:27]
wire _T_11 = io_func3 == 3'h1; // @[InstructionTypeDecode.scala 56:56]
wire _T_12 = _T_10 & _T_11; // @[InstructionTypeDecode.scala 56:44]
wire _T_14 = io_func3 == 3'h2; // @[InstructionTypeDecode.scala 59:56]
wire _T_15 = _T_10 & _T_14; // @[InstructionTypeDecode.scala 59:44]
wire _T_17 = io_func3 == 3'h3; // @[InstructionTypeDecode.scala 62:56]
wire _T_18 = _T_10 & _T_17; // @[InstructionTypeDecode.scala 62:44]
wire _T_20 = io_func3 == 3'h5; // @[InstructionTypeDecode.scala 65:56]
wire _T_21 = _T_10 & _T_20; // @[InstructionTypeDecode.scala 65:44]
wire _T_23 = io_func3 == 3'h6; // @[InstructionTypeDecode.scala 68:56]
wire _T_24 = _T_10 & _T_23; // @[InstructionTypeDecode.scala 68:44]
wire _T_26 = io_func3 == 3'h7; // @[InstructionTypeDecode.scala 71:56]
wire _T_27 = _T_10 & _T_26; // @[InstructionTypeDecode.scala 71:44]
wire [1:0] _GEN_3 = _T_27 ? 2'h3 : 2'h0; // @[InstructionTypeDecode.scala 71:70]
wire _GEN_5 = _T_24 | _T_27; // @[InstructionTypeDecode.scala 68:70]
wire [1:0] _GEN_6 = _T_24 ? 2'h2 : _GEN_3; // @[InstructionTypeDecode.scala 68:70]
wire _GEN_8 = _T_21 | _GEN_5; // @[InstructionTypeDecode.scala 65:70]
wire [1:0] _GEN_9 = _T_21 ? 2'h1 : _GEN_6; // @[InstructionTypeDecode.scala 65:70]
wire [1:0] _GEN_12 = _T_18 ? 2'h3 : _GEN_9; // @[InstructionTypeDecode.scala 62:70]
wire _GEN_13 = _T_18 ? 1'h0 : _GEN_8; // @[InstructionTypeDecode.scala 62:70]
wire _GEN_15 = _T_15 | _T_18; // @[InstructionTypeDecode.scala 59:70]
wire [1:0] _GEN_16 = _T_15 ? 2'h2 : _GEN_12; // @[InstructionTypeDecode.scala 59:70]
wire _GEN_17 = _T_15 ? 1'h0 : _GEN_13; // @[InstructionTypeDecode.scala 59:70]
wire _GEN_19 = _T_12 | _GEN_15; // @[InstructionTypeDecode.scala 56:70]
wire [1:0] _GEN_20 = _T_12 ? 2'h1 : _GEN_16; // @[InstructionTypeDecode.scala 56:70]
wire _GEN_21 = _T_12 ? 1'h0 : _GEN_17; // @[InstructionTypeDecode.scala 56:70]
wire _GEN_24 = _T_9 ? 1'h0 : _GEN_19; // @[InstructionTypeDecode.scala 54:44]
wire [1:0] _GEN_25 = _T_9 ? 2'h0 : _GEN_20; // @[InstructionTypeDecode.scala 54:44]
wire _GEN_26 = _T_9 ? 1'h0 : _GEN_21; // @[InstructionTypeDecode.scala 54:44]
wire _GEN_29 = _T_8 ? 1'h0 : _T_9; // @[InstructionTypeDecode.scala 51:45]
wire _GEN_30 = _T_8 ? 1'h0 : _GEN_24; // @[InstructionTypeDecode.scala 51:45]
wire [1:0] _GEN_31 = _T_8 ? 2'h0 : _GEN_25; // @[InstructionTypeDecode.scala 51:45]
wire _GEN_32 = _T_8 ? 1'h0 : _GEN_26; // @[InstructionTypeDecode.scala 51:45]
wire _GEN_35 = _T_7 ? 1'h0 : _T_8; // @[InstructionTypeDecode.scala 49:45]
wire _GEN_36 = _T_7 ? 1'h0 : _GEN_29; // @[InstructionTypeDecode.scala 49:45]
wire _GEN_37 = _T_7 ? 1'h0 : _GEN_30; // @[InstructionTypeDecode.scala 49:45]
wire [1:0] _GEN_38 = _T_7 ? 2'h0 : _GEN_31; // @[InstructionTypeDecode.scala 49:45]
wire _GEN_39 = _T_7 ? 1'h0 : _GEN_32; // @[InstructionTypeDecode.scala 49:45]
wire _GEN_42 = _T_6 ? 1'h0 : _T_7; // @[InstructionTypeDecode.scala 47:45]
wire _GEN_43 = _T_6 ? 1'h0 : _GEN_35; // @[InstructionTypeDecode.scala 47:45]
wire _GEN_44 = _T_6 ? 1'h0 : _GEN_36; // @[InstructionTypeDecode.scala 47:45]
wire _GEN_45 = _T_6 ? 1'h0 : _GEN_37; // @[InstructionTypeDecode.scala 47:45]
wire [1:0] _GEN_46 = _T_6 ? 2'h0 : _GEN_38; // @[InstructionTypeDecode.scala 47:45]
wire _GEN_47 = _T_6 ? 1'h0 : _GEN_39; // @[InstructionTypeDecode.scala 47:45]
wire _GEN_50 = _T_5 ? 1'h0 : _T_6; // @[InstructionTypeDecode.scala 45:45]
wire _GEN_51 = _T_5 ? 1'h0 : _GEN_42; // @[InstructionTypeDecode.scala 45:45]
wire _GEN_52 = _T_5 ? 1'h0 : _GEN_43; // @[InstructionTypeDecode.scala 45:45]
wire _GEN_53 = _T_5 ? 1'h0 : _GEN_44; // @[InstructionTypeDecode.scala 45:45]
wire _GEN_54 = _T_5 ? 1'h0 : _GEN_45; // @[InstructionTypeDecode.scala 45:45]
wire [1:0] _GEN_55 = _T_5 ? 2'h0 : _GEN_46; // @[InstructionTypeDecode.scala 45:45]
wire _GEN_56 = _T_5 ? 1'h0 : _GEN_47; // @[InstructionTypeDecode.scala 45:45]
wire _GEN_59 = _T_4 ? 1'h0 : _T_5; // @[InstructionTypeDecode.scala 43:45]
wire _GEN_60 = _T_4 ? 1'h0 : _GEN_50; // @[InstructionTypeDecode.scala 43:45]
wire _GEN_61 = _T_4 ? 1'h0 : _GEN_51; // @[InstructionTypeDecode.scala 43:45]
wire _GEN_62 = _T_4 ? 1'h0 : _GEN_52; // @[InstructionTypeDecode.scala 43:45]
wire _GEN_63 = _T_4 ? 1'h0 : _GEN_53; // @[InstructionTypeDecode.scala 43:45]
wire _GEN_64 = _T_4 ? 1'h0 : _GEN_54; // @[InstructionTypeDecode.scala 43:45]
wire [1:0] _GEN_65 = _T_4 ? 2'h0 : _GEN_55; // @[InstructionTypeDecode.scala 43:45]
wire _GEN_66 = _T_4 ? 1'h0 : _GEN_56; // @[InstructionTypeDecode.scala 43:45]
wire _GEN_69 = _T_3 ? 1'h0 : _T_4; // @[InstructionTypeDecode.scala 41:45]
wire _GEN_70 = _T_3 ? 1'h0 : _GEN_59; // @[InstructionTypeDecode.scala 41:45]
wire _GEN_71 = _T_3 ? 1'h0 : _GEN_60; // @[InstructionTypeDecode.scala 41:45]
wire _GEN_72 = _T_3 ? 1'h0 : _GEN_61; // @[InstructionTypeDecode.scala 41:45]
wire _GEN_73 = _T_3 ? 1'h0 : _GEN_62; // @[InstructionTypeDecode.scala 41:45]
wire _GEN_74 = _T_3 ? 1'h0 : _GEN_63; // @[InstructionTypeDecode.scala 41:45]
wire _GEN_75 = _T_3 ? 1'h0 : _GEN_64; // @[InstructionTypeDecode.scala 41:45]
wire [1:0] _GEN_76 = _T_3 ? 2'h0 : _GEN_65; // @[InstructionTypeDecode.scala 41:45]
wire _GEN_77 = _T_3 ? 1'h0 : _GEN_66; // @[InstructionTypeDecode.scala 41:45]
wire _GEN_80 = _T_2 ? 1'h0 : _T_3; // @[InstructionTypeDecode.scala 39:43]
wire _GEN_81 = _T_2 ? 1'h0 : _GEN_69; // @[InstructionTypeDecode.scala 39:43]
wire _GEN_82 = _T_2 ? 1'h0 : _GEN_70; // @[InstructionTypeDecode.scala 39:43]
wire _GEN_83 = _T_2 ? 1'h0 : _GEN_71; // @[InstructionTypeDecode.scala 39:43]
wire _GEN_84 = _T_2 ? 1'h0 : _GEN_72; // @[InstructionTypeDecode.scala 39:43]
wire _GEN_85 = _T_2 ? 1'h0 : _GEN_73; // @[InstructionTypeDecode.scala 39:43]
wire _GEN_86 = _T_2 ? 1'h0 : _GEN_74; // @[InstructionTypeDecode.scala 39:43]
wire _GEN_87 = _T_2 ? 1'h0 : _GEN_75; // @[InstructionTypeDecode.scala 39:43]
wire [1:0] _GEN_88 = _T_2 ? 2'h0 : _GEN_76; // @[InstructionTypeDecode.scala 39:43]
wire _GEN_89 = _T_2 ? 1'h0 : _GEN_77; // @[InstructionTypeDecode.scala 39:43]
assign io_r_type = _T & _GEN_1; // @[InstructionTypeDecode.scala 82:19 InstructionTypeDecode.scala 32:23 InstructionTypeDecode.scala 36:21 InstructionTypeDecode.scala 82:19]
assign io_load_type = _T ? 1'h0 : _T_2; // @[InstructionTypeDecode.scala 83:22 InstructionTypeDecode.scala 40:22 InstructionTypeDecode.scala 83:22]
assign io_s_type = _T ? 1'h0 : _GEN_80; // @[InstructionTypeDecode.scala 84:19 InstructionTypeDecode.scala 42:19 InstructionTypeDecode.scala 84:19]
assign io_sb_type = _T ? 1'h0 : _GEN_81; // @[InstructionTypeDecode.scala 85:20 InstructionTypeDecode.scala 44:20 InstructionTypeDecode.scala 85:20]
assign io_i_type = _T ? 1'h0 : _GEN_82; // @[InstructionTypeDecode.scala 86:19 InstructionTypeDecode.scala 46:19 InstructionTypeDecode.scala 86:19]
assign io_jalr_type = _T ? 1'h0 : _GEN_83; // @[InstructionTypeDecode.scala 87:22 InstructionTypeDecode.scala 48:22 InstructionTypeDecode.scala 87:22]
assign io_jal_type = _T ? 1'h0 : _GEN_84; // @[InstructionTypeDecode.scala 88:21 InstructionTypeDecode.scala 50:21 InstructionTypeDecode.scala 88:21]
assign io_lui_type = _T ? 1'h0 : _GEN_85; // @[InstructionTypeDecode.scala 89:21 InstructionTypeDecode.scala 52:21 InstructionTypeDecode.scala 89:21]
assign io_Auipc = _T ? 1'h0 : _GEN_86; // @[InstructionTypeDecode.scala 90:21 InstructionTypeDecode.scala 55:18 InstructionTypeDecode.scala 90:21]
assign io_multiply = _T & _T_1; // @[InstructionTypeDecode.scala 91:21 InstructionTypeDecode.scala 31:23 InstructionTypeDecode.scala 91:21]
assign io_csr_imm_type = _T ? 1'h0 : _GEN_89; // @[InstructionTypeDecode.scala 93:25 InstructionTypeDecode.scala 66:25 InstructionTypeDecode.scala 69:25 InstructionTypeDecode.scala 72:25 InstructionTypeDecode.scala 93:25]
assign io_csr_type = _T ? 1'h0 : _GEN_87; // @[InstructionTypeDecode.scala 92:21 InstructionTypeDecode.scala 57:21 InstructionTypeDecode.scala 60:21 InstructionTypeDecode.scala 63:21 InstructionTypeDecode.scala 92:21]
assign io_csr_op = _T ? 2'h0 : _GEN_88; // @[InstructionTypeDecode.scala 94:19 InstructionTypeDecode.scala 58:19 InstructionTypeDecode.scala 61:19 InstructionTypeDecode.scala 64:19 InstructionTypeDecode.scala 67:19 InstructionTypeDecode.scala 70:19 InstructionTypeDecode.scala 73:19 InstructionTypeDecode.scala 94:19]
endmodule
module ControlDecode(
input io_in_r_type,
input io_in_load_type,
input io_in_s_type,
input io_in_sb_type,
input io_in_i_type,
input io_in_jalr_type,
input io_in_jal_type,
input io_in_lui_type,
input io_in_csr_type,
input io_in_csr_imm_type,
input io_Auipc,
input io_multiply,
output io_memWrite,
output io_memRead,
output io_branch,
output io_regWrite,
output io_csr_wen,
output io_memToReg,
output [3:0] io_aluOperation,
output [1:0] io_operand_a_sel,
output io_operand_b_sel,
output [1:0] io_extend_sel,
output [1:0] io_next_pc_sel
);
wire [4:0] _GEN_2 = io_in_csr_imm_type ? 5'h8 : 5'h1c; // @[ControlDecode.scala 169:45]
wire _GEN_4 = io_in_csr_type | io_in_csr_imm_type; // @[ControlDecode.scala 157:41]
wire [4:0] _GEN_5 = io_in_csr_type ? 5'h8 : _GEN_2; // @[ControlDecode.scala 157:41]
wire _GEN_7 = io_multiply | _GEN_4; // @[ControlDecode.scala 145:36]
wire [4:0] _GEN_8 = io_multiply ? 5'h9 : _GEN_5; // @[ControlDecode.scala 145:36]
wire _GEN_9 = io_multiply ? 1'h0 : _GEN_4; // @[ControlDecode.scala 145:36]
wire _GEN_11 = io_Auipc | _GEN_7; // @[ControlDecode.scala 133:5]
wire [4:0] _GEN_12 = io_Auipc ? 5'h7 : _GEN_8; // @[ControlDecode.scala 133:5]
wire _GEN_14 = io_Auipc | _GEN_9; // @[ControlDecode.scala 133:5]
wire [1:0] _GEN_15 = io_Auipc ? 2'h2 : 2'h0; // @[ControlDecode.scala 133:5]
wire _GEN_16 = io_Auipc ? 1'h0 : _GEN_9; // @[ControlDecode.scala 133:5]
wire _GEN_18 = io_in_lui_type | _GEN_11; // @[ControlDecode.scala 120:5]
wire [4:0] _GEN_19 = io_in_lui_type ? 5'h6 : _GEN_12; // @[ControlDecode.scala 120:5]
wire [1:0] _GEN_20 = io_in_lui_type ? 2'h3 : {{1'd0}, io_Auipc}; // @[ControlDecode.scala 120:5]
wire _GEN_21 = io_in_lui_type | _GEN_14; // @[ControlDecode.scala 120:5]
wire [1:0] _GEN_22 = io_in_lui_type ? 2'h2 : _GEN_15; // @[ControlDecode.scala 120:5]
wire _GEN_23 = io_in_lui_type ? 1'h0 : _GEN_16; // @[ControlDecode.scala 120:5]
wire _GEN_25 = io_in_jal_type | _GEN_18; // @[ControlDecode.scala 107:41]
wire [4:0] _GEN_26 = io_in_jal_type ? 5'h3 : _GEN_19; // @[ControlDecode.scala 107:41]
wire [1:0] _GEN_27 = io_in_jal_type ? 2'h2 : _GEN_20; // @[ControlDecode.scala 107:41]
wire _GEN_28 = io_in_jal_type ? 1'h0 : _GEN_21; // @[ControlDecode.scala 107:41]
wire [1:0] _GEN_29 = io_in_jal_type ? 2'h0 : _GEN_22; // @[ControlDecode.scala 107:41]
wire [1:0] _GEN_30 = io_in_jal_type ? 2'h2 : 2'h0; // @[ControlDecode.scala 107:41]
wire _GEN_31 = io_in_jal_type ? 1'h0 : _GEN_23; // @[ControlDecode.scala 107:41]
wire _GEN_33 = io_in_jalr_type | _GEN_25; // @[ControlDecode.scala 96:42]
wire [4:0] _GEN_34 = io_in_jalr_type ? 5'h3 : _GEN_26; // @[ControlDecode.scala 96:42]
wire [1:0] _GEN_35 = io_in_jalr_type ? 2'h2 : _GEN_27; // @[ControlDecode.scala 96:42]
wire _GEN_36 = io_in_jalr_type ? 1'h0 : _GEN_28; // @[ControlDecode.scala 96:42]
wire [1:0] _GEN_37 = io_in_jalr_type ? 2'h0 : _GEN_29; // @[ControlDecode.scala 96:42]
wire [1:0] _GEN_38 = io_in_jalr_type ? 2'h3 : _GEN_30; // @[ControlDecode.scala 96:42]
wire _GEN_39 = io_in_jalr_type ? 1'h0 : _GEN_31; // @[ControlDecode.scala 96:42]
wire _GEN_41 = io_in_i_type | _GEN_33; // @[ControlDecode.scala 85:39]
wire [4:0] _GEN_42 = io_in_i_type ? 5'h1 : _GEN_34; // @[ControlDecode.scala 85:39]
wire [1:0] _GEN_43 = io_in_i_type ? 2'h0 : _GEN_35; // @[ControlDecode.scala 85:39]
wire _GEN_44 = io_in_i_type | _GEN_36; // @[ControlDecode.scala 85:39]
wire [1:0] _GEN_45 = io_in_i_type ? 2'h0 : _GEN_37; // @[ControlDecode.scala 85:39]
wire [1:0] _GEN_46 = io_in_i_type ? 2'h0 : _GEN_38; // @[ControlDecode.scala 85:39]
wire _GEN_47 = io_in_i_type ? 1'h0 : _GEN_39; // @[ControlDecode.scala 85:39]
wire _GEN_50 = io_in_sb_type ? 1'h0 : _GEN_41; // @[ControlDecode.scala 74:40]
wire [4:0] _GEN_51 = io_in_sb_type ? 5'h2 : _GEN_42; // @[ControlDecode.scala 74:40]
wire [1:0] _GEN_52 = io_in_sb_type ? 2'h0 : _GEN_43; // @[ControlDecode.scala 74:40]
wire _GEN_53 = io_in_sb_type ? 1'h0 : _GEN_44; // @[ControlDecode.scala 74:40]
wire [1:0] _GEN_54 = io_in_sb_type ? 2'h0 : _GEN_45; // @[ControlDecode.scala 74:40]
wire [1:0] _GEN_55 = io_in_sb_type ? 2'h1 : _GEN_46; // @[ControlDecode.scala 74:40]
wire _GEN_56 = io_in_sb_type ? 1'h0 : _GEN_47; // @[ControlDecode.scala 74:40]
wire _GEN_59 = io_in_s_type ? 1'h0 : io_in_sb_type; // @[ControlDecode.scala 62:39]
wire _GEN_60 = io_in_s_type ? 1'h0 : _GEN_50; // @[ControlDecode.scala 62:39]
wire [4:0] _GEN_61 = io_in_s_type ? 5'h5 : _GEN_51; // @[ControlDecode.scala 62:39]
wire [1:0] _GEN_62 = io_in_s_type ? 2'h0 : _GEN_52; // @[ControlDecode.scala 62:39]
wire _GEN_63 = io_in_s_type | _GEN_53; // @[ControlDecode.scala 62:39]
wire [1:0] _GEN_64 = io_in_s_type ? 2'h1 : _GEN_54; // @[ControlDecode.scala 62:39]
wire [1:0] _GEN_65 = io_in_s_type ? 2'h0 : _GEN_55; // @[ControlDecode.scala 62:39]
wire _GEN_66 = io_in_s_type ? 1'h0 : _GEN_56; // @[ControlDecode.scala 62:39]
wire _GEN_67 = io_in_load_type ? 1'h0 : io_in_s_type; // @[ControlDecode.scala 50:40]
wire _GEN_69 = io_in_load_type ? 1'h0 : _GEN_59; // @[ControlDecode.scala 50:40]
wire _GEN_70 = io_in_load_type | _GEN_60; // @[ControlDecode.scala 50:40]
wire [4:0] _GEN_71 = io_in_load_type ? 5'h4 : _GEN_61; // @[ControlDecode.scala 50:40]
wire [1:0] _GEN_72 = io_in_load_type ? 2'h0 : _GEN_62; // @[ControlDecode.scala 50:40]
wire _GEN_73 = io_in_load_type | _GEN_63; // @[ControlDecode.scala 50:40]
wire [1:0] _GEN_74 = io_in_load_type ? 2'h0 : _GEN_64; // @[ControlDecode.scala 50:40]
wire [1:0] _GEN_75 = io_in_load_type ? 2'h0 : _GEN_65; // @[ControlDecode.scala 50:40]
wire _GEN_76 = io_in_load_type ? 1'h0 : _GEN_66; // @[ControlDecode.scala 50:40]
wire [4:0] _GEN_81 = io_in_r_type ? 5'h0 : _GEN_71; // @[ControlDecode.scala 37:32]
assign io_memWrite = io_in_r_type ? 1'h0 : _GEN_67; // @[ControlDecode.scala 188:21 ControlDecode.scala 38:21 ControlDecode.scala 52:21 ControlDecode.scala 64:21 ControlDecode.scala 75:21 ControlDecode.scala 86:21 ControlDecode.scala 97:21 ControlDecode.scala 108:21 ControlDecode.scala 121:21 ControlDecode.scala 134:21 ControlDecode.scala 146:21 ControlDecode.scala 158:21 ControlDecode.scala 170:21 ControlDecode.scala 188:21]
assign io_memRead = io_in_r_type ? 1'h0 : io_in_load_type; // @[ControlDecode.scala 189:21 ControlDecode.scala 39:21 ControlDecode.scala 53:21 ControlDecode.scala 65:21 ControlDecode.scala 76:21 ControlDecode.scala 87:21 ControlDecode.scala 98:21 ControlDecode.scala 109:21 ControlDecode.scala 122:21 ControlDecode.scala 135:21 ControlDecode.scala 147:21 ControlDecode.scala 159:20 ControlDecode.scala 171:20 ControlDecode.scala 189:21]
assign io_branch = io_in_r_type ? 1'h0 : _GEN_69; // @[ControlDecode.scala 190:19 ControlDecode.scala 40:19 ControlDecode.scala 54:19 ControlDecode.scala 66:19 ControlDecode.scala 77:19 ControlDecode.scala 88:19 ControlDecode.scala 99:19 ControlDecode.scala 110:19 ControlDecode.scala 123:19 ControlDecode.scala 136:19 ControlDecode.scala 148:19 ControlDecode.scala 160:19 ControlDecode.scala 172:19 ControlDecode.scala 190:19]
assign io_regWrite = io_in_r_type | _GEN_70; // @[ControlDecode.scala 191:21 ControlDecode.scala 41:21 ControlDecode.scala 55:21 ControlDecode.scala 67:21 ControlDecode.scala 78:21 ControlDecode.scala 89:21 ControlDecode.scala 100:21 ControlDecode.scala 111:21 ControlDecode.scala 124:21 ControlDecode.scala 137:21 ControlDecode.scala 149:21 ControlDecode.scala 161:21 ControlDecode.scala 173:21 ControlDecode.scala 191:21]
assign io_csr_wen = io_in_r_type ? 1'h0 : _GEN_76; // @[ControlDecode.scala 198:20 ControlDecode.scala 162:20 ControlDecode.scala 174:20 ControlDecode.scala 198:20]
assign io_memToReg = io_in_r_type ? 1'h0 : io_in_load_type; // @[ControlDecode.scala 192:21 ControlDecode.scala 42:21 ControlDecode.scala 56:21 ControlDecode.scala 68:21 ControlDecode.scala 79:21 ControlDecode.scala 90:21 ControlDecode.scala 101:21 ControlDecode.scala 112:21 ControlDecode.scala 125:21 ControlDecode.scala 138:21 ControlDecode.scala 150:21 ControlDecode.scala 163:21 ControlDecode.scala 175:21 ControlDecode.scala 192:21]
assign io_aluOperation = _GEN_81[3:0]; // @[ControlDecode.scala 193:25 ControlDecode.scala 43:25 ControlDecode.scala 57:25 ControlDecode.scala 69:25 ControlDecode.scala 80:25 ControlDecode.scala 91:25 ControlDecode.scala 102:25 ControlDecode.scala 113:25 ControlDecode.scala 126:25 ControlDecode.scala 139:25 ControlDecode.scala 151:25 ControlDecode.scala 164:25 ControlDecode.scala 176:25 ControlDecode.scala 193:25]
assign io_operand_a_sel = io_in_r_type ? 2'h0 : _GEN_72; // @[ControlDecode.scala 194:26 ControlDecode.scala 44:26 ControlDecode.scala 58:26 ControlDecode.scala 70:26 ControlDecode.scala 81:26 ControlDecode.scala 92:26 ControlDecode.scala 103:26 ControlDecode.scala 114:26 ControlDecode.scala 127:26 ControlDecode.scala 140:26 ControlDecode.scala 152:26 ControlDecode.scala 165:26 ControlDecode.scala 177:26 ControlDecode.scala 194:26]
assign io_operand_b_sel = io_in_r_type ? 1'h0 : _GEN_73; // @[ControlDecode.scala 195:26 ControlDecode.scala 45:26 ControlDecode.scala 59:26 ControlDecode.scala 71:26 ControlDecode.scala 82:26 ControlDecode.scala 93:26 ControlDecode.scala 104:26 ControlDecode.scala 115:26 ControlDecode.scala 128:26 ControlDecode.scala 141:26 ControlDecode.scala 153:26 ControlDecode.scala 166:26 ControlDecode.scala 178:26 ControlDecode.scala 195:26]
assign io_extend_sel = io_in_r_type ? 2'h0 : _GEN_74; // @[ControlDecode.scala 196:23 ControlDecode.scala 46:23 ControlDecode.scala 60:23 ControlDecode.scala 72:23 ControlDecode.scala 83:23 ControlDecode.scala 94:23 ControlDecode.scala 105:23 ControlDecode.scala 116:23 ControlDecode.scala 129:23 ControlDecode.scala 142:23 ControlDecode.scala 154:23 ControlDecode.scala 167:23 ControlDecode.scala 179:23 ControlDecode.scala 196:23]
assign io_next_pc_sel = io_in_r_type ? 2'h0 : _GEN_75; // @[ControlDecode.scala 197:24 ControlDecode.scala 47:24 ControlDecode.scala 61:24 ControlDecode.scala 73:24 ControlDecode.scala 84:24 ControlDecode.scala 95:24 ControlDecode.scala 106:24 ControlDecode.scala 117:24 ControlDecode.scala 130:24 ControlDecode.scala 143:24 ControlDecode.scala 155:24 ControlDecode.scala 168:24 ControlDecode.scala 180:24 ControlDecode.scala 197:24]
endmodule
module Control(
input [6:0] io_in_opcode,
input [6:0] io_func7,
input [2:0] io_func3,
output io_out_memWrite,
output io_out_branch,
output io_out_memRead,
output io_out_regWrite,
output io_csr_we_o,
output io_csr_imm_type,
output [1:0] io_csr_op_o,
output io_out_memToReg,
output [3:0] io_out_aluOp,
output [1:0] io_out_operand_a_sel,
output io_out_operand_b_sel,
output [1:0] io_out_extend_sel,
output [1:0] io_out_next_pc_sel
);
wire [2:0] instruction_type_decode_io_func3; // @[Control.scala 26:41]
wire [6:0] instruction_type_decode_io_func7; // @[Control.scala 26:41]
wire [6:0] instruction_type_decode_io_opcode; // @[Control.scala 26:41]
wire instruction_type_decode_io_r_type; // @[Control.scala 26:41]
wire instruction_type_decode_io_load_type; // @[Control.scala 26:41]
wire instruction_type_decode_io_s_type; // @[Control.scala 26:41]
wire instruction_type_decode_io_sb_type; // @[Control.scala 26:41]
wire instruction_type_decode_io_i_type; // @[Control.scala 26:41]
wire instruction_type_decode_io_jalr_type; // @[Control.scala 26:41]
wire instruction_type_decode_io_jal_type; // @[Control.scala 26:41]
wire instruction_type_decode_io_lui_type; // @[Control.scala 26:41]
wire instruction_type_decode_io_Auipc; // @[Control.scala 26:41]
wire instruction_type_decode_io_multiply; // @[Control.scala 26:41]
wire instruction_type_decode_io_csr_imm_type; // @[Control.scala 26:41]
wire instruction_type_decode_io_csr_type; // @[Control.scala 26:41]
wire [1:0] instruction_type_decode_io_csr_op; // @[Control.scala 26:41]
wire control_decode_io_in_r_type; // @[Control.scala 27:32]
wire control_decode_io_in_load_type; // @[Control.scala 27:32]
wire control_decode_io_in_s_type; // @[Control.scala 27:32]
wire control_decode_io_in_sb_type; // @[Control.scala 27:32]
wire control_decode_io_in_i_type; // @[Control.scala 27:32]
wire control_decode_io_in_jalr_type; // @[Control.scala 27:32]
wire control_decode_io_in_jal_type; // @[Control.scala 27:32]
wire control_decode_io_in_lui_type; // @[Control.scala 27:32]
wire control_decode_io_in_csr_type; // @[Control.scala 27:32]
wire control_decode_io_in_csr_imm_type; // @[Control.scala 27:32]
wire control_decode_io_Auipc; // @[Control.scala 27:32]
wire control_decode_io_multiply; // @[Control.scala 27:32]
wire control_decode_io_memWrite; // @[Control.scala 27:32]
wire control_decode_io_memRead; // @[Control.scala 27:32]
wire control_decode_io_branch; // @[Control.scala 27:32]
wire control_decode_io_regWrite; // @[Control.scala 27:32]
wire control_decode_io_csr_wen; // @[Control.scala 27:32]
wire control_decode_io_memToReg; // @[Control.scala 27:32]
wire [3:0] control_decode_io_aluOperation; // @[Control.scala 27:32]
wire [1:0] control_decode_io_operand_a_sel; // @[Control.scala 27:32]
wire control_decode_io_operand_b_sel; // @[Control.scala 27:32]
wire [1:0] control_decode_io_extend_sel; // @[Control.scala 27:32]
wire [1:0] control_decode_io_next_pc_sel; // @[Control.scala 27:32]
InstructionTypeDecode instruction_type_decode ( // @[Control.scala 26:41]
.io_func3(instruction_type_decode_io_func3),
.io_func7(instruction_type_decode_io_func7),
.io_opcode(instruction_type_decode_io_opcode),
.io_r_type(instruction_type_decode_io_r_type),
.io_load_type(instruction_type_decode_io_load_type),
.io_s_type(instruction_type_decode_io_s_type),
.io_sb_type(instruction_type_decode_io_sb_type),
.io_i_type(instruction_type_decode_io_i_type),
.io_jalr_type(instruction_type_decode_io_jalr_type),
.io_jal_type(instruction_type_decode_io_jal_type),
.io_lui_type(instruction_type_decode_io_lui_type),
.io_Auipc(instruction_type_decode_io_Auipc),
.io_multiply(instruction_type_decode_io_multiply),
.io_csr_imm_type(instruction_type_decode_io_csr_imm_type),
.io_csr_type(instruction_type_decode_io_csr_type),
.io_csr_op(instruction_type_decode_io_csr_op)
);
ControlDecode control_decode ( // @[Control.scala 27:32]
.io_in_r_type(control_decode_io_in_r_type),
.io_in_load_type(control_decode_io_in_load_type),
.io_in_s_type(control_decode_io_in_s_type),
.io_in_sb_type(control_decode_io_in_sb_type),
.io_in_i_type(control_decode_io_in_i_type),
.io_in_jalr_type(control_decode_io_in_jalr_type),
.io_in_jal_type(control_decode_io_in_jal_type),
.io_in_lui_type(control_decode_io_in_lui_type),
.io_in_csr_type(control_decode_io_in_csr_type),
.io_in_csr_imm_type(control_decode_io_in_csr_imm_type),
.io_Auipc(control_decode_io_Auipc),
.io_multiply(control_decode_io_multiply),
.io_memWrite(control_decode_io_memWrite),
.io_memRead(control_decode_io_memRead),
.io_branch(control_decode_io_branch),
.io_regWrite(control_decode_io_regWrite),
.io_csr_wen(control_decode_io_csr_wen),
.io_memToReg(control_decode_io_memToReg),
.io_aluOperation(control_decode_io_aluOperation),
.io_operand_a_sel(control_decode_io_operand_a_sel),
.io_operand_b_sel(control_decode_io_operand_b_sel),
.io_extend_sel(control_decode_io_extend_sel),
.io_next_pc_sel(control_decode_io_next_pc_sel)
);
assign io_out_memWrite = control_decode_io_memWrite; // @[Control.scala 43:21]
assign io_out_branch = control_decode_io_branch; // @[Control.scala 44:19]
assign io_out_memRead = control_decode_io_memRead; // @[Control.scala 45:20]
assign io_out_regWrite = control_decode_io_regWrite; // @[Control.scala 46:21]
assign io_csr_we_o = control_decode_io_csr_wen; // @[Control.scala 47:17]
assign io_csr_imm_type = instruction_type_decode_io_csr_imm_type; // @[Control.scala 57:21]
assign io_csr_op_o = instruction_type_decode_io_csr_op; // @[Control.scala 56:17]
assign io_out_memToReg = control_decode_io_memToReg; // @[Control.scala 48:21]
assign io_out_aluOp = control_decode_io_aluOperation; // @[Control.scala 49:18]
assign io_out_operand_a_sel = control_decode_io_operand_a_sel; // @[Control.scala 50:26]
assign io_out_operand_b_sel = control_decode_io_operand_b_sel; // @[Control.scala 51:26]
assign io_out_extend_sel = control_decode_io_extend_sel; // @[Control.scala 52:23]
assign io_out_next_pc_sel = control_decode_io_next_pc_sel; // @[Control.scala 53:24]
assign instruction_type_decode_io_func3 = io_func3; // @[Control.scala 29:39]
assign instruction_type_decode_io_func7 = io_func7; // @[Control.scala 58:38]
assign instruction_type_decode_io_opcode = io_in_opcode; // @[Control.scala 28:39]
assign control_decode_io_in_r_type = instruction_type_decode_io_r_type; // @[Control.scala 30:33]
assign control_decode_io_in_load_type = instruction_type_decode_io_load_type; // @[Control.scala 31:36]
assign control_decode_io_in_s_type = instruction_type_decode_io_s_type; // @[Control.scala 32:33]
assign control_decode_io_in_sb_type = instruction_type_decode_io_sb_type; // @[Control.scala 33:34]
assign control_decode_io_in_i_type = instruction_type_decode_io_i_type; // @[Control.scala 34:33]
assign control_decode_io_in_jalr_type = instruction_type_decode_io_jalr_type; // @[Control.scala 35:36]
assign control_decode_io_in_jal_type = instruction_type_decode_io_jal_type; // @[Control.scala 36:35]
assign control_decode_io_in_lui_type = instruction_type_decode_io_lui_type; // @[Control.scala 37:35]
assign control_decode_io_in_csr_type = instruction_type_decode_io_csr_type; // @[Control.scala 40:35]
assign control_decode_io_in_csr_imm_type = instruction_type_decode_io_csr_imm_type; // @[Control.scala 41:39]
assign control_decode_io_Auipc = instruction_type_decode_io_Auipc; // @[Control.scala 38:35]
assign control_decode_io_multiply = instruction_type_decode_io_multiply; // @[Control.scala 39:35]
endmodule
module DecodeForwardUnit(
input [4:0] io_ID_EX_REGRD,
input io_ID_EX_MEMRD,
input [4:0] io_EX_MEM_REGRD,
input io_EX_MEM_MEMRD,
input [4:0] io_MEM_WB_REGRD,
input io_MEM_WB_MEMRD,
input io_execute_regwrite,
input io_mem_regwrite,
input io_wb_regwrite,
input [4:0] io_rs1_sel,
input [4:0] io_rs2_sel,
input io_ctrl_branch,
output [3:0] io_forward_rs1,
output [3:0] io_forward_rs2
);
wire _T_1 = io_ID_EX_REGRD != 5'h0; // @[DecodeForwardUnit.scala 29:27]
wire _T_2 = ~io_ID_EX_MEMRD; // @[DecodeForwardUnit.scala 29:60]
wire _T_3 = _T_1 & _T_2; // @[DecodeForwardUnit.scala 29:42]
wire _T_4 = io_ID_EX_REGRD == io_rs1_sel; // @[DecodeForwardUnit.scala 29:87]
wire _T_5 = _T_3 & _T_4; // @[DecodeForwardUnit.scala 29:68]
wire _T_6 = io_ID_EX_REGRD == io_rs2_sel; // @[DecodeForwardUnit.scala 29:122]
wire _T_7 = _T_5 & _T_6; // @[DecodeForwardUnit.scala 29:103]
wire _T_17 = _T_3 & _T_6; // @[DecodeForwardUnit.scala 34:75]
wire _GEN_2 = _T_5 ? 1'h0 : _T_17; // @[DecodeForwardUnit.scala 32:111]
wire _GEN_3 = _T_7 | _T_5; // @[DecodeForwardUnit.scala 29:139]
wire _GEN_4 = _T_7 | _GEN_2; // @[DecodeForwardUnit.scala 29:139]
wire _T_18 = io_EX_MEM_REGRD != 5'h0; // @[DecodeForwardUnit.scala 39:28]
wire _T_19 = ~io_EX_MEM_MEMRD; // @[DecodeForwardUnit.scala 39:62]
wire _T_20 = _T_18 & _T_19; // @[DecodeForwardUnit.scala 39:43]
wire _T_23 = _T_1 & _T_4; // @[DecodeForwardUnit.scala 40:43]
wire _T_25 = _T_23 & _T_6; // @[DecodeForwardUnit.scala 40:78]
wire _T_26 = ~_T_25; // @[DecodeForwardUnit.scala 40:9]
wire _T_27 = _T_20 & _T_26; // @[DecodeForwardUnit.scala 39:70]
wire _T_28 = io_EX_MEM_REGRD == io_rs1_sel; // @[DecodeForwardUnit.scala 41:26]
wire _T_29 = _T_27 & _T_28; // @[DecodeForwardUnit.scala 40:114]
wire _T_30 = io_EX_MEM_REGRD == io_rs2_sel; // @[DecodeForwardUnit.scala 41:62]
wire _T_31 = _T_29 & _T_30; // @[DecodeForwardUnit.scala 41:42]
wire _T_37 = _T_1 & _T_6; // @[DecodeForwardUnit.scala 47:43]
wire _T_38 = ~_T_37; // @[DecodeForwardUnit.scala 47:9]
wire _T_39 = _T_20 & _T_38; // @[DecodeForwardUnit.scala 46:77]
wire _T_41 = _T_39 & _T_30; // @[DecodeForwardUnit.scala 47:79]
wire _T_48 = ~_T_23; // @[DecodeForwardUnit.scala 53:9]
wire _T_49 = _T_20 & _T_48; // @[DecodeForwardUnit.scala 52:77]
wire _T_51 = _T_49 & _T_28; // @[DecodeForwardUnit.scala 53:79]
wire _T_54 = _T_18 & io_EX_MEM_MEMRD; // @[DecodeForwardUnit.scala 58:50]
wire _T_61 = _T_54 & _T_26; // @[DecodeForwardUnit.scala 58:77]
wire _T_63 = _T_61 & _T_28; // @[DecodeForwardUnit.scala 59:114]
wire _T_65 = _T_63 & _T_30; // @[DecodeForwardUnit.scala 60:42]
wire _T_73 = _T_54 & _T_38; // @[DecodeForwardUnit.scala 65:77]
wire _T_75 = _T_73 & _T_30; // @[DecodeForwardUnit.scala 66:79]
wire _T_78 = io_ctrl_branch & _T_18; // @[DecodeForwardUnit.scala 71:42]
wire _T_80 = _T_78 & io_EX_MEM_MEMRD; // @[DecodeForwardUnit.scala 71:76]
wire _T_85 = _T_80 & _T_48; // @[DecodeForwardUnit.scala 71:103]
wire _T_87 = _T_85 & _T_28; // @[DecodeForwardUnit.scala 72:79]
wire [2:0] _GEN_5 = _T_87 ? 3'h4 : {{2'd0}, _GEN_3}; // @[DecodeForwardUnit.scala 73:43]
wire [2:0] _GEN_6 = _T_75 ? 3'h4 : {{2'd0}, _GEN_4}; // @[DecodeForwardUnit.scala 67:43]
wire [2:0] _GEN_7 = _T_75 ? {{2'd0}, _GEN_3} : _GEN_5; // @[DecodeForwardUnit.scala 67:43]
wire [2:0] _GEN_8 = _T_65 ? 3'h4 : _GEN_7; // @[DecodeForwardUnit.scala 60:79]
wire [2:0] _GEN_9 = _T_65 ? 3'h4 : _GEN_6; // @[DecodeForwardUnit.scala 60:79]
wire [2:0] _GEN_10 = _T_51 ? 3'h2 : _GEN_8; // @[DecodeForwardUnit.scala 54:43]
wire [2:0] _GEN_11 = _T_51 ? {{2'd0}, _GEN_4} : _GEN_9; // @[DecodeForwardUnit.scala 54:43]
wire [2:0] _GEN_12 = _T_41 ? 3'h2 : _GEN_11; // @[DecodeForwardUnit.scala 48:43]
wire [2:0] _GEN_13 = _T_41 ? {{2'd0}, _GEN_3} : _GEN_10; // @[DecodeForwardUnit.scala 48:43]
wire [2:0] _GEN_14 = _T_31 ? 3'h2 : _GEN_13; // @[DecodeForwardUnit.scala 41:79]
wire [2:0] _GEN_15 = _T_31 ? 3'h2 : _GEN_12; // @[DecodeForwardUnit.scala 41:79]
wire _T_88 = io_MEM_WB_REGRD != 5'h0; // @[DecodeForwardUnit.scala 80:28]
wire _T_89 = ~io_MEM_WB_MEMRD; // @[DecodeForwardUnit.scala 80:62]
wire _T_90 = _T_88 & _T_89; // @[DecodeForwardUnit.scala 80:43]
wire _T_97 = _T_90 & _T_26; // @[DecodeForwardUnit.scala 80:70]
wire _T_100 = _T_18 & _T_28; // @[DecodeForwardUnit.scala 84:44]
wire _T_102 = _T_100 & _T_30; // @[DecodeForwardUnit.scala 84:80]
wire _T_103 = ~_T_102; // @[DecodeForwardUnit.scala 84:9]
wire _T_104 = _T_97 & _T_103; // @[DecodeForwardUnit.scala 82:114]
wire _T_105 = io_MEM_WB_REGRD == io_rs1_sel; // @[DecodeForwardUnit.scala 85:26]
wire _T_106 = _T_104 & _T_105; // @[DecodeForwardUnit.scala 84:117]
wire _T_107 = io_MEM_WB_REGRD == io_rs2_sel; // @[DecodeForwardUnit.scala 85:62]
wire _T_108 = _T_106 & _T_107; // @[DecodeForwardUnit.scala 85:42]
wire _T_116 = _T_90 & _T_38; // @[DecodeForwardUnit.scala 91:77]
wire _T_119 = _T_18 & _T_30; // @[DecodeForwardUnit.scala 95:46]
wire _T_120 = ~_T_119; // @[DecodeForwardUnit.scala 95:11]
wire _T_121 = _T_116 & _T_120; // @[DecodeForwardUnit.scala 93:81]
wire _T_123 = _T_121 & _T_107; // @[DecodeForwardUnit.scala 95:83]
wire _T_131 = _T_90 & _T_48; // @[DecodeForwardUnit.scala 101:77]
wire _T_135 = ~_T_100; // @[DecodeForwardUnit.scala 105:11]
wire _T_136 = _T_131 & _T_135; // @[DecodeForwardUnit.scala 103:81]
wire _T_138 = _T_136 & _T_105; // @[DecodeForwardUnit.scala 105:83]
wire _T_141 = _T_88 & io_MEM_WB_MEMRD; // @[DecodeForwardUnit.scala 110:52]
wire _T_148 = _T_141 & _T_26; // @[DecodeForwardUnit.scala 110:79]
wire _T_155 = _T_148 & _T_103; // @[DecodeForwardUnit.scala 112:114]
wire _T_157 = _T_155 & _T_105; // @[DecodeForwardUnit.scala 114:117]
wire _T_159 = _T_157 & _T_107; // @[DecodeForwardUnit.scala 115:42]
wire _T_167 = _T_141 & _T_38; // @[DecodeForwardUnit.scala 121:77]
wire _T_172 = _T_167 & _T_120; // @[DecodeForwardUnit.scala 123:81]
wire _T_174 = _T_172 & _T_107; // @[DecodeForwardUnit.scala 125:83]
wire _T_182 = _T_141 & _T_48; // @[DecodeForwardUnit.scala 131:77]
wire _T_187 = _T_182 & _T_135; // @[DecodeForwardUnit.scala 133:81]
wire _T_189 = _T_187 & _T_105; // @[DecodeForwardUnit.scala 135:82]
wire [2:0] _GEN_16 = _T_189 ? 3'h5 : _GEN_14; // @[DecodeForwardUnit.scala 136:45]
wire [2:0] _GEN_17 = _T_174 ? 3'h5 : _GEN_15; // @[DecodeForwardUnit.scala 126:45]
wire [2:0] _GEN_18 = _T_174 ? _GEN_14 : _GEN_16; // @[DecodeForwardUnit.scala 126:45]
wire [2:0] _GEN_19 = _T_159 ? 3'h5 : _GEN_18; // @[DecodeForwardUnit.scala 115:79]
wire [2:0] _GEN_20 = _T_159 ? 3'h5 : _GEN_17; // @[DecodeForwardUnit.scala 115:79]
wire [2:0] _GEN_21 = _T_138 ? 3'h3 : _GEN_19; // @[DecodeForwardUnit.scala 106:45]
wire [2:0] _GEN_22 = _T_138 ? _GEN_15 : _GEN_20; // @[DecodeForwardUnit.scala 106:45]
wire [2:0] _GEN_23 = _T_123 ? 3'h3 : _GEN_22; // @[DecodeForwardUnit.scala 96:45]
wire [2:0] _GEN_24 = _T_123 ? _GEN_14 : _GEN_21; // @[DecodeForwardUnit.scala 96:45]
wire [2:0] _GEN_25 = _T_108 ? 3'h3 : _GEN_24; // @[DecodeForwardUnit.scala 85:79]
wire [2:0] _GEN_26 = _T_108 ? 3'h3 : _GEN_23; // @[DecodeForwardUnit.scala 85:79]
wire _T_190 = ~io_ctrl_branch; // @[DecodeForwardUnit.scala 144:32]
wire _T_193 = io_execute_regwrite & _T_1; // @[DecodeForwardUnit.scala 146:42]
wire _T_195 = _T_193 & _T_2; // @[DecodeForwardUnit.scala 146:75]
wire _T_197 = _T_195 & _T_4; // @[DecodeForwardUnit.scala 146:101]
wire [2:0] _GEN_27 = _T_197 ? 3'h6 : 3'h0; // @[DecodeForwardUnit.scala 146:136]
wire _T_200 = io_mem_regwrite & _T_18; // @[DecodeForwardUnit.scala 151:38]
wire _T_202 = _T_200 & _T_19; // @[DecodeForwardUnit.scala 151:72]
wire _T_207 = _T_202 & _T_48; // @[DecodeForwardUnit.scala 151:99]
wire _T_209 = _T_207 & _T_28; // @[DecodeForwardUnit.scala 152:81]
wire _T_214 = _T_200 & io_EX_MEM_MEMRD; // @[DecodeForwardUnit.scala 158:79]
wire _T_219 = _T_214 & _T_48; // @[DecodeForwardUnit.scala 158:106]
wire _T_221 = _T_219 & _T_28; // @[DecodeForwardUnit.scala 159:83]
wire [3:0] _GEN_28 = _T_221 ? 4'h9 : {{1'd0}, _GEN_27}; // @[DecodeForwardUnit.scala 160:47]
wire [3:0] _GEN_29 = _T_209 ? 4'h7 : _GEN_28; // @[DecodeForwardUnit.scala 153:45]
wire _T_224 = io_wb_regwrite & _T_88; // @[DecodeForwardUnit.scala 168:37]
wire _T_226 = _T_224 & _T_89; // @[DecodeForwardUnit.scala 168:71]
wire _T_231 = _T_226 & _T_48; // @[DecodeForwardUnit.scala 168:98]
wire _T_236 = _T_231 & _T_135; // @[DecodeForwardUnit.scala 170:81]
wire _T_238 = _T_236 & _T_105; // @[DecodeForwardUnit.scala 172:83]
wire _T_243 = _T_224 & io_MEM_WB_MEMRD; // @[DecodeForwardUnit.scala 178:79]
wire _T_248 = _T_243 & _T_48; // @[DecodeForwardUnit.scala 178:106]
wire _T_253 = _T_248 & _T_135; // @[DecodeForwardUnit.scala 180:81]
wire _T_255 = _T_253 & _T_105; // @[DecodeForwardUnit.scala 182:83]
wire [3:0] _GEN_30 = _T_255 ? 4'ha : _GEN_29; // @[DecodeForwardUnit.scala 183:45]
wire [3:0] _GEN_31 = _T_238 ? 4'h8 : _GEN_30; // @[DecodeForwardUnit.scala 173:45]
wire [3:0] _GEN_32 = _T_190 ? _GEN_31 : 4'h0; // @[DecodeForwardUnit.scala 144:41]
wire [2:0] _GEN_34 = io_ctrl_branch ? _GEN_26 : 3'h0; // @[DecodeForwardUnit.scala 27:34]
assign io_forward_rs1 = io_ctrl_branch ? {{1'd0}, _GEN_25} : _GEN_32; // @[DecodeForwardUnit.scala 23:20 DecodeForwardUnit.scala 30:24 DecodeForwardUnit.scala 33:24 DecodeForwardUnit.scala 43:24 DecodeForwardUnit.scala 56:24 DecodeForwardUnit.scala 62:24 DecodeForwardUnit.scala 75:24 DecodeForwardUnit.scala 87:24 DecodeForwardUnit.scala 108:26 DecodeForwardUnit.scala 117:24 DecodeForwardUnit.scala 138:26 DecodeForwardUnit.scala 147:26 DecodeForwardUnit.scala 155:26 DecodeForwardUnit.scala 162:28 DecodeForwardUnit.scala 175:26 DecodeForwardUnit.scala 185:26]
assign io_forward_rs2 = {{1'd0}, _GEN_34}; // @[DecodeForwardUnit.scala 24:20 DecodeForwardUnit.scala 31:24 DecodeForwardUnit.scala 35:24 DecodeForwardUnit.scala 44:24 DecodeForwardUnit.scala 50:24 DecodeForwardUnit.scala 63:24 DecodeForwardUnit.scala 69:24 DecodeForwardUnit.scala 88:24 DecodeForwardUnit.scala 98:26 DecodeForwardUnit.scala 118:24 DecodeForwardUnit.scala 128:26]
endmodule
module BranchLogic(
input [31:0] io_in_rs1,
input [31:0] io_in_rs2,
input [2:0] io_in_func3,
output io_output
);
wire _T = io_in_func3 == 3'h0; // @[BranchLogic.scala 13:20]
wire _T_1 = $signed(io_in_rs1) == $signed(io_in_rs2); // @[BranchLogic.scala 15:20]
wire _T_2 = io_in_func3 == 3'h1; // @[BranchLogic.scala 20:27]
wire _T_3 = $signed(io_in_rs1) != $signed(io_in_rs2); // @[BranchLogic.scala 22:20]
wire _T_4 = io_in_func3 == 3'h4; // @[BranchLogic.scala 27:27]
wire _T_5 = $signed(io_in_rs1) < $signed(io_in_rs2); // @[BranchLogic.scala 29:20]
wire _T_6 = io_in_func3 == 3'h5; // @[BranchLogic.scala 34:27]
wire _T_7 = $signed(io_in_rs1) >= $signed(io_in_rs2); // @[BranchLogic.scala 36:20]
wire _T_8 = io_in_func3 == 3'h6; // @[BranchLogic.scala 41:27]
wire _T_11 = io_in_rs1 < io_in_rs2; // @[BranchLogic.scala 43:27]
wire _T_12 = io_in_func3 == 3'h7; // @[BranchLogic.scala 48:27]
wire _T_15 = io_in_rs1 >= io_in_rs2; // @[BranchLogic.scala 50:27]
wire _GEN_6 = _T_12 & _T_15; // @[BranchLogic.scala 48:41]
wire _GEN_7 = _T_8 ? _T_11 : _GEN_6; // @[BranchLogic.scala 41:41]
wire _GEN_8 = _T_6 ? _T_7 : _GEN_7; // @[BranchLogic.scala 34:41]
wire _GEN_9 = _T_4 ? _T_5 : _GEN_8; // @[BranchLogic.scala 27:41]
wire _GEN_10 = _T_2 ? _T_3 : _GEN_9; // @[BranchLogic.scala 20:41]
assign io_output = _T ? _T_1 : _GEN_10; // @[BranchLogic.scala 16:17 BranchLogic.scala 18:17 BranchLogic.scala 23:17 BranchLogic.scala 25:17 BranchLogic.scala 30:17 BranchLogic.scala 32:17 BranchLogic.scala 37:17 BranchLogic.scala 39:17 BranchLogic.scala 44:17 BranchLogic.scala 46:17 BranchLogic.scala 51:17 BranchLogic.scala 53:17 BranchLogic.scala 56:15]
endmodule
module RegisterFile(
input clock,
input reset,
input io_regWrite,
input [4:0] io_rd_sel,
input [4:0] io_rs1_sel,
input [4:0] io_rs2_sel,
input [31:0] io_writeData,
output [31:0] io_rs1,
output [31:0] io_rs2
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
reg [31:0] _RAND_11;
reg [31:0] _RAND_12;
reg [31:0] _RAND_13;
reg [31:0] _RAND_14;
reg [31:0] _RAND_15;
reg [31:0] _RAND_16;
reg [31:0] _RAND_17;
reg [31:0] _RAND_18;
reg [31:0] _RAND_19;
reg [31:0] _RAND_20;
reg [31:0] _RAND_21;
reg [31:0] _RAND_22;
reg [31:0] _RAND_23;
reg [31:0] _RAND_24;
reg [31:0] _RAND_25;
reg [31:0] _RAND_26;
reg [31:0] _RAND_27;
reg [31:0] _RAND_28;
reg [31:0] _RAND_29;
reg [31:0] _RAND_30;
reg [31:0] _RAND_31;
`endif // RANDOMIZE_REG_INIT
reg [31:0] registers_0; // @[RegisterFile.scala 20:28]
reg [31:0] registers_1; // @[RegisterFile.scala 20:28]
reg [31:0] registers_2; // @[RegisterFile.scala 20:28]
reg [31:0] registers_3; // @[RegisterFile.scala 20:28]
reg [31:0] registers_4; // @[RegisterFile.scala 20:28]
reg [31:0] registers_5; // @[RegisterFile.scala 20:28]
reg [31:0] registers_6; // @[RegisterFile.scala 20:28]
reg [31:0] registers_7; // @[RegisterFile.scala 20:28]
reg [31:0] registers_8; // @[RegisterFile.scala 20:28]
reg [31:0] registers_9; // @[RegisterFile.scala 20:28]
reg [31:0] registers_10; // @[RegisterFile.scala 20:28]
reg [31:0] registers_11; // @[RegisterFile.scala 20:28]
reg [31:0] registers_12; // @[RegisterFile.scala 20:28]
reg [31:0] registers_13; // @[RegisterFile.scala 20:28]
reg [31:0] registers_14; // @[RegisterFile.scala 20:28]
reg [31:0] registers_15; // @[RegisterFile.scala 20:28]
reg [31:0] registers_16; // @[RegisterFile.scala 20:28]
reg [31:0] registers_17; // @[RegisterFile.scala 20:28]
reg [31:0] registers_18; // @[RegisterFile.scala 20:28]
reg [31:0] registers_19; // @[RegisterFile.scala 20:28]
reg [31:0] registers_20; // @[RegisterFile.scala 20:28]
reg [31:0] registers_21; // @[RegisterFile.scala 20:28]
reg [31:0] registers_22; // @[RegisterFile.scala 20:28]
reg [31:0] registers_23; // @[RegisterFile.scala 20:28]
reg [31:0] registers_24; // @[RegisterFile.scala 20:28]
reg [31:0] registers_25; // @[RegisterFile.scala 20:28]
reg [31:0] registers_26; // @[RegisterFile.scala 20:28]
reg [31:0] registers_27; // @[RegisterFile.scala 20:28]
reg [31:0] registers_28; // @[RegisterFile.scala 20:28]
reg [31:0] registers_29; // @[RegisterFile.scala 20:28]
reg [31:0] registers_30; // @[RegisterFile.scala 20:28]
reg [31:0] registers_31; // @[RegisterFile.scala 20:28]
wire [31:0] _GEN_1 = 5'h1 == io_rs1_sel ? $signed(registers_1) : $signed(registers_0); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_2 = 5'h2 == io_rs1_sel ? $signed(registers_2) : $signed(_GEN_1); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_3 = 5'h3 == io_rs1_sel ? $signed(registers_3) : $signed(_GEN_2); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_4 = 5'h4 == io_rs1_sel ? $signed(registers_4) : $signed(_GEN_3); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_5 = 5'h5 == io_rs1_sel ? $signed(registers_5) : $signed(_GEN_4); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_6 = 5'h6 == io_rs1_sel ? $signed(registers_6) : $signed(_GEN_5); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_7 = 5'h7 == io_rs1_sel ? $signed(registers_7) : $signed(_GEN_6); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_8 = 5'h8 == io_rs1_sel ? $signed(registers_8) : $signed(_GEN_7); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_9 = 5'h9 == io_rs1_sel ? $signed(registers_9) : $signed(_GEN_8); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_10 = 5'ha == io_rs1_sel ? $signed(registers_10) : $signed(_GEN_9); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_11 = 5'hb == io_rs1_sel ? $signed(registers_11) : $signed(_GEN_10); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_12 = 5'hc == io_rs1_sel ? $signed(registers_12) : $signed(_GEN_11); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_13 = 5'hd == io_rs1_sel ? $signed(registers_13) : $signed(_GEN_12); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_14 = 5'he == io_rs1_sel ? $signed(registers_14) : $signed(_GEN_13); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_15 = 5'hf == io_rs1_sel ? $signed(registers_15) : $signed(_GEN_14); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_16 = 5'h10 == io_rs1_sel ? $signed(registers_16) : $signed(_GEN_15); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_17 = 5'h11 == io_rs1_sel ? $signed(registers_17) : $signed(_GEN_16); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_18 = 5'h12 == io_rs1_sel ? $signed(registers_18) : $signed(_GEN_17); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_19 = 5'h13 == io_rs1_sel ? $signed(registers_19) : $signed(_GEN_18); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_20 = 5'h14 == io_rs1_sel ? $signed(registers_20) : $signed(_GEN_19); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_21 = 5'h15 == io_rs1_sel ? $signed(registers_21) : $signed(_GEN_20); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_22 = 5'h16 == io_rs1_sel ? $signed(registers_22) : $signed(_GEN_21); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_23 = 5'h17 == io_rs1_sel ? $signed(registers_23) : $signed(_GEN_22); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_24 = 5'h18 == io_rs1_sel ? $signed(registers_24) : $signed(_GEN_23); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_25 = 5'h19 == io_rs1_sel ? $signed(registers_25) : $signed(_GEN_24); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_26 = 5'h1a == io_rs1_sel ? $signed(registers_26) : $signed(_GEN_25); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_27 = 5'h1b == io_rs1_sel ? $signed(registers_27) : $signed(_GEN_26); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_28 = 5'h1c == io_rs1_sel ? $signed(registers_28) : $signed(_GEN_27); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_29 = 5'h1d == io_rs1_sel ? $signed(registers_29) : $signed(_GEN_28); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_30 = 5'h1e == io_rs1_sel ? $signed(registers_30) : $signed(_GEN_29); // @[RegisterFile.scala 25:12]
wire [31:0] _GEN_33 = 5'h1 == io_rs2_sel ? $signed(registers_1) : $signed(registers_0); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_34 = 5'h2 == io_rs2_sel ? $signed(registers_2) : $signed(_GEN_33); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_35 = 5'h3 == io_rs2_sel ? $signed(registers_3) : $signed(_GEN_34); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_36 = 5'h4 == io_rs2_sel ? $signed(registers_4) : $signed(_GEN_35); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_37 = 5'h5 == io_rs2_sel ? $signed(registers_5) : $signed(_GEN_36); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_38 = 5'h6 == io_rs2_sel ? $signed(registers_6) : $signed(_GEN_37); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_39 = 5'h7 == io_rs2_sel ? $signed(registers_7) : $signed(_GEN_38); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_40 = 5'h8 == io_rs2_sel ? $signed(registers_8) : $signed(_GEN_39); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_41 = 5'h9 == io_rs2_sel ? $signed(registers_9) : $signed(_GEN_40); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_42 = 5'ha == io_rs2_sel ? $signed(registers_10) : $signed(_GEN_41); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_43 = 5'hb == io_rs2_sel ? $signed(registers_11) : $signed(_GEN_42); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_44 = 5'hc == io_rs2_sel ? $signed(registers_12) : $signed(_GEN_43); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_45 = 5'hd == io_rs2_sel ? $signed(registers_13) : $signed(_GEN_44); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_46 = 5'he == io_rs2_sel ? $signed(registers_14) : $signed(_GEN_45); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_47 = 5'hf == io_rs2_sel ? $signed(registers_15) : $signed(_GEN_46); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_48 = 5'h10 == io_rs2_sel ? $signed(registers_16) : $signed(_GEN_47); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_49 = 5'h11 == io_rs2_sel ? $signed(registers_17) : $signed(_GEN_48); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_50 = 5'h12 == io_rs2_sel ? $signed(registers_18) : $signed(_GEN_49); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_51 = 5'h13 == io_rs2_sel ? $signed(registers_19) : $signed(_GEN_50); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_52 = 5'h14 == io_rs2_sel ? $signed(registers_20) : $signed(_GEN_51); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_53 = 5'h15 == io_rs2_sel ? $signed(registers_21) : $signed(_GEN_52); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_54 = 5'h16 == io_rs2_sel ? $signed(registers_22) : $signed(_GEN_53); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_55 = 5'h17 == io_rs2_sel ? $signed(registers_23) : $signed(_GEN_54); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_56 = 5'h18 == io_rs2_sel ? $signed(registers_24) : $signed(_GEN_55); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_57 = 5'h19 == io_rs2_sel ? $signed(registers_25) : $signed(_GEN_56); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_58 = 5'h1a == io_rs2_sel ? $signed(registers_26) : $signed(_GEN_57); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_59 = 5'h1b == io_rs2_sel ? $signed(registers_27) : $signed(_GEN_58); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_60 = 5'h1c == io_rs2_sel ? $signed(registers_28) : $signed(_GEN_59); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_61 = 5'h1d == io_rs2_sel ? $signed(registers_29) : $signed(_GEN_60); // @[RegisterFile.scala 26:12]
wire [31:0] _GEN_62 = 5'h1e == io_rs2_sel ? $signed(registers_30) : $signed(_GEN_61); // @[RegisterFile.scala 26:12]
wire _T_2 = io_rd_sel == 5'h0; // @[RegisterFile.scala 28:24]
assign io_rs1 = 5'h1f == io_rs1_sel ? $signed(registers_31) : $signed(_GEN_30); // @[RegisterFile.scala 25:12]
assign io_rs2 = 5'h1f == io_rs2_sel ? $signed(registers_31) : $signed(_GEN_62); // @[RegisterFile.scala 26:12]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
registers_0 = _RAND_0[31:0];
_RAND_1 = {1{`RANDOM}};
registers_1 = _RAND_1[31:0];
_RAND_2 = {1{`RANDOM}};
registers_2 = _RAND_2[31:0];
_RAND_3 = {1{`RANDOM}};
registers_3 = _RAND_3[31:0];
_RAND_4 = {1{`RANDOM}};
registers_4 = _RAND_4[31:0];
_RAND_5 = {1{`RANDOM}};
registers_5 = _RAND_5[31:0];
_RAND_6 = {1{`RANDOM}};
registers_6 = _RAND_6[31:0];
_RAND_7 = {1{`RANDOM}};
registers_7 = _RAND_7[31:0];
_RAND_8 = {1{`RANDOM}};
registers_8 = _RAND_8[31:0];
_RAND_9 = {1{`RANDOM}};
registers_9 = _RAND_9[31:0];
_RAND_10 = {1{`RANDOM}};
registers_10 = _RAND_10[31:0];
_RAND_11 = {1{`RANDOM}};
registers_11 = _RAND_11[31:0];
_RAND_12 = {1{`RANDOM}};
registers_12 = _RAND_12[31:0];
_RAND_13 = {1{`RANDOM}};
registers_13 = _RAND_13[31:0];
_RAND_14 = {1{`RANDOM}};
registers_14 = _RAND_14[31:0];
_RAND_15 = {1{`RANDOM}};
registers_15 = _RAND_15[31:0];
_RAND_16 = {1{`RANDOM}};
registers_16 = _RAND_16[31:0];
_RAND_17 = {1{`RANDOM}};
registers_17 = _RAND_17[31:0];
_RAND_18 = {1{`RANDOM}};
registers_18 = _RAND_18[31:0];
_RAND_19 = {1{`RANDOM}};
registers_19 = _RAND_19[31:0];
_RAND_20 = {1{`RANDOM}};
registers_20 = _RAND_20[31:0];
_RAND_21 = {1{`RANDOM}};
registers_21 = _RAND_21[31:0];
_RAND_22 = {1{`RANDOM}};
registers_22 = _RAND_22[31:0];
_RAND_23 = {1{`RANDOM}};
registers_23 = _RAND_23[31:0];
_RAND_24 = {1{`RANDOM}};
registers_24 = _RAND_24[31:0];
_RAND_25 = {1{`RANDOM}};
registers_25 = _RAND_25[31:0];
_RAND_26 = {1{`RANDOM}};
registers_26 = _RAND_26[31:0];
_RAND_27 = {1{`RANDOM}};
registers_27 = _RAND_27[31:0];
_RAND_28 = {1{`RANDOM}};
registers_28 = _RAND_28[31:0];
_RAND_29 = {1{`RANDOM}};
registers_29 = _RAND_29[31:0];
_RAND_30 = {1{`RANDOM}};
registers_30 = _RAND_30[31:0];
_RAND_31 = {1{`RANDOM}};
registers_31 = _RAND_31[31:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
registers_0 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
registers_0 <= 32'sh0;
end else if (5'h0 == io_rd_sel) begin
registers_0 <= io_writeData;
end else begin
registers_0 <= 32'sh0;
end
end else begin
registers_0 <= 32'sh0;
end
if (reset) begin
registers_1 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h1 == io_rd_sel) begin
registers_1 <= 32'sh0;
end
end else if (5'h1 == io_rd_sel) begin
registers_1 <= io_writeData;
end
end
if (reset) begin
registers_2 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h2 == io_rd_sel) begin
registers_2 <= 32'sh0;
end
end else if (5'h2 == io_rd_sel) begin
registers_2 <= io_writeData;
end
end
if (reset) begin
registers_3 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h3 == io_rd_sel) begin
registers_3 <= 32'sh0;
end
end else if (5'h3 == io_rd_sel) begin
registers_3 <= io_writeData;
end
end
if (reset) begin
registers_4 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h4 == io_rd_sel) begin
registers_4 <= 32'sh0;
end
end else if (5'h4 == io_rd_sel) begin
registers_4 <= io_writeData;
end
end
if (reset) begin
registers_5 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h5 == io_rd_sel) begin
registers_5 <= 32'sh0;
end
end else if (5'h5 == io_rd_sel) begin
registers_5 <= io_writeData;
end
end
if (reset) begin
registers_6 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h6 == io_rd_sel) begin
registers_6 <= 32'sh0;
end
end else if (5'h6 == io_rd_sel) begin
registers_6 <= io_writeData;
end
end
if (reset) begin
registers_7 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h7 == io_rd_sel) begin
registers_7 <= 32'sh0;
end
end else if (5'h7 == io_rd_sel) begin
registers_7 <= io_writeData;
end
end
if (reset) begin
registers_8 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h8 == io_rd_sel) begin
registers_8 <= 32'sh0;
end
end else if (5'h8 == io_rd_sel) begin
registers_8 <= io_writeData;
end
end
if (reset) begin
registers_9 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h9 == io_rd_sel) begin
registers_9 <= 32'sh0;
end
end else if (5'h9 == io_rd_sel) begin
registers_9 <= io_writeData;
end
end
if (reset) begin
registers_10 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'ha == io_rd_sel) begin
registers_10 <= 32'sh0;
end
end else if (5'ha == io_rd_sel) begin
registers_10 <= io_writeData;
end
end
if (reset) begin
registers_11 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'hb == io_rd_sel) begin
registers_11 <= 32'sh0;
end
end else if (5'hb == io_rd_sel) begin
registers_11 <= io_writeData;
end
end
if (reset) begin
registers_12 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'hc == io_rd_sel) begin
registers_12 <= 32'sh0;
end
end else if (5'hc == io_rd_sel) begin
registers_12 <= io_writeData;
end
end
if (reset) begin
registers_13 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'hd == io_rd_sel) begin
registers_13 <= 32'sh0;
end
end else if (5'hd == io_rd_sel) begin
registers_13 <= io_writeData;
end
end
if (reset) begin
registers_14 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'he == io_rd_sel) begin
registers_14 <= 32'sh0;
end
end else if (5'he == io_rd_sel) begin
registers_14 <= io_writeData;
end
end
if (reset) begin
registers_15 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'hf == io_rd_sel) begin
registers_15 <= 32'sh0;
end
end else if (5'hf == io_rd_sel) begin
registers_15 <= io_writeData;
end
end
if (reset) begin
registers_16 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h10 == io_rd_sel) begin
registers_16 <= 32'sh0;
end
end else if (5'h10 == io_rd_sel) begin
registers_16 <= io_writeData;
end
end
if (reset) begin
registers_17 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h11 == io_rd_sel) begin
registers_17 <= 32'sh0;
end
end else if (5'h11 == io_rd_sel) begin
registers_17 <= io_writeData;
end
end
if (reset) begin
registers_18 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h12 == io_rd_sel) begin
registers_18 <= 32'sh0;
end
end else if (5'h12 == io_rd_sel) begin
registers_18 <= io_writeData;
end
end
if (reset) begin
registers_19 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h13 == io_rd_sel) begin
registers_19 <= 32'sh0;
end
end else if (5'h13 == io_rd_sel) begin
registers_19 <= io_writeData;
end
end
if (reset) begin
registers_20 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h14 == io_rd_sel) begin
registers_20 <= 32'sh0;
end
end else if (5'h14 == io_rd_sel) begin
registers_20 <= io_writeData;
end
end
if (reset) begin
registers_21 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h15 == io_rd_sel) begin
registers_21 <= 32'sh0;
end
end else if (5'h15 == io_rd_sel) begin
registers_21 <= io_writeData;
end
end
if (reset) begin
registers_22 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h16 == io_rd_sel) begin
registers_22 <= 32'sh0;
end
end else if (5'h16 == io_rd_sel) begin
registers_22 <= io_writeData;
end
end
if (reset) begin
registers_23 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h17 == io_rd_sel) begin
registers_23 <= 32'sh0;
end
end else if (5'h17 == io_rd_sel) begin
registers_23 <= io_writeData;
end
end
if (reset) begin
registers_24 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h18 == io_rd_sel) begin
registers_24 <= 32'sh0;
end
end else if (5'h18 == io_rd_sel) begin
registers_24 <= io_writeData;
end
end
if (reset) begin
registers_25 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h19 == io_rd_sel) begin
registers_25 <= 32'sh0;
end
end else if (5'h19 == io_rd_sel) begin
registers_25 <= io_writeData;
end
end
if (reset) begin
registers_26 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h1a == io_rd_sel) begin
registers_26 <= 32'sh0;
end
end else if (5'h1a == io_rd_sel) begin
registers_26 <= io_writeData;
end
end
if (reset) begin
registers_27 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h1b == io_rd_sel) begin
registers_27 <= 32'sh0;
end
end else if (5'h1b == io_rd_sel) begin
registers_27 <= io_writeData;
end
end
if (reset) begin
registers_28 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h1c == io_rd_sel) begin
registers_28 <= 32'sh0;
end
end else if (5'h1c == io_rd_sel) begin
registers_28 <= io_writeData;
end
end
if (reset) begin
registers_29 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h1d == io_rd_sel) begin
registers_29 <= 32'sh0;
end
end else if (5'h1d == io_rd_sel) begin
registers_29 <= io_writeData;
end
end
if (reset) begin
registers_30 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h1e == io_rd_sel) begin
registers_30 <= 32'sh0;
end
end else if (5'h1e == io_rd_sel) begin
registers_30 <= io_writeData;
end
end
if (reset) begin
registers_31 <= 32'sh0;
end else if (io_regWrite) begin
if (_T_2) begin
if (5'h1f == io_rd_sel) begin
registers_31 <= 32'sh0;
end
end else if (5'h1f == io_rd_sel) begin
registers_31 <= io_writeData;
end
end
end
endmodule
module ImmediateGeneration(
input [31:0] io_instruction,
input [31:0] io_pc,
output [31:0] io_s_imm,
output [31:0] io_sb_imm,
output [31:0] io_u_imm,
output [31:0] io_uj_imm,
output [31:0] io_i_imm
);
wire [4:0] s_lower_half = io_instruction[11:7]; // @[ImmediateGeneration.scala 19:38]
wire [6:0] s_upper_half = io_instruction[31:25]; // @[ImmediateGeneration.scala 20:38]
wire [11:0] s_imm_12 = {s_upper_half,s_lower_half}; // @[Cat.scala 29:58]
wire [19:0] _T_2 = s_imm_12[11] ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
wire [3:0] sb_lower_half = io_instruction[11:8]; // @[ImmediateGeneration.scala 28:39]
wire [5:0] sb_upper_half = io_instruction[30:25]; // @[ImmediateGeneration.scala 29:39]
wire sb_11thbit = io_instruction[7]; // @[ImmediateGeneration.scala 30:36]
wire sb_12thbit = io_instruction[31]; // @[ImmediateGeneration.scala 31:36]
wire [12:0] sb_imm_13 = {sb_12thbit,sb_11thbit,sb_upper_half,sb_lower_half,1'h0}; // @[Cat.scala 29:58]
wire [18:0] _T_10 = sb_imm_13[12] ? 19'h7ffff : 19'h0; // @[Bitwise.scala 72:12]
wire [31:0] sb_imm_32 = {_T_10,sb_12thbit,sb_11thbit,sb_upper_half,sb_lower_half,1'h0}; // @[ImmediateGeneration.scala 33:61]
wire [19:0] u_imm_20 = io_instruction[31:12]; // @[ImmediateGeneration.scala 39:34]
wire [11:0] _T_17 = u_imm_20[19] ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12]
wire [31:0] u_imm_32 = {_T_17,u_imm_20}; // @[Cat.scala 29:58]
wire [43:0] _GEN_0 = {u_imm_32, 12'h0}; // @[ImmediateGeneration.scala 42:37]
wire [46:0] _T_18 = {{3'd0}, _GEN_0}; // @[ImmediateGeneration.scala 43:34]
wire [9:0] uj_lower_half = io_instruction[30:21]; // @[ImmediateGeneration.scala 48:39]
wire uj_11thbit = io_instruction[20]; // @[ImmediateGeneration.scala 49:36]
wire [7:0] uj_upper_half = io_instruction[19:12]; // @[ImmediateGeneration.scala 50:39]
wire [20:0] uj_imm_21 = {sb_12thbit,uj_upper_half,uj_11thbit,uj_lower_half,1'h0}; // @[Cat.scala 29:58]
wire [10:0] _T_25 = uj_imm_21[20] ? 11'h7ff : 11'h0; // @[Bitwise.scala 72:12]
wire [31:0] uj_imm_32 = {_T_25,sb_12thbit,uj_upper_half,uj_11thbit,uj_lower_half,1'h0}; // @[ImmediateGeneration.scala 53:61]
wire [11:0] i_imm_12 = io_instruction[31:20]; // @[ImmediateGeneration.scala 59:34]
wire [19:0] _T_32 = i_imm_12[11] ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
assign io_s_imm = {_T_2,s_upper_half,s_lower_half}; // @[ImmediateGeneration.scala 23:14]
assign io_sb_imm = $signed(sb_imm_32) + $signed(io_pc); // @[ImmediateGeneration.scala 34:15]
assign io_u_imm = _T_18[31:0]; // @[ImmediateGeneration.scala 43:14]
assign io_uj_imm = $signed(uj_imm_32) + $signed(io_pc); // @[ImmediateGeneration.scala 54:15]
assign io_i_imm = {_T_32,i_imm_12}; // @[ImmediateGeneration.scala 61:14]
endmodule
module StructuralDetector(
input [4:0] io_rs1_sel,
input [4:0] io_rs2_sel,
input io_MEM_WB_regWr,
input [4:0] io_MEM_WB_REGRD,
input [6:0] io_inst_op_in,
output io_fwd_rs1,
output io_fwd_rs2
);
wire _T_1 = io_MEM_WB_REGRD != 5'h0; // @[StructuralDetector.scala 27:51]
wire _T_2 = io_MEM_WB_regWr & _T_1; // @[StructuralDetector.scala 27:32]
wire _T_3 = io_MEM_WB_REGRD == io_rs1_sel; // @[StructuralDetector.scala 27:86]
wire _T_4 = _T_2 & _T_3; // @[StructuralDetector.scala 27:66]
wire _T_5 = io_inst_op_in != 7'h37; // @[StructuralDetector.scala 27:118]
wire _T_10 = io_MEM_WB_REGRD == io_rs2_sel; // @[StructuralDetector.scala 33:86]
wire _T_11 = _T_2 & _T_10; // @[StructuralDetector.scala 33:67]
assign io_fwd_rs1 = _T_4 & _T_5; // @[StructuralDetector.scala 28:16 StructuralDetector.scala 30:16]
assign io_fwd_rs2 = _T_11 & _T_5; // @[StructuralDetector.scala 34:16 StructuralDetector.scala 36:16]
endmodule
module Jalr(
input [31:0] io_input_a,
input [31:0] io_input_b,
output [31:0] io_output
);
wire [31:0] sum = $signed(io_input_a) + $signed(io_input_b); // @[Jalr.scala 12:26]
wire [32:0] _GEN_0 = {{1{sum[31]}},sum}; // @[Jalr.scala 13:22]
wire [32:0] _T_3 = $signed(_GEN_0) & 33'shfffffffe; // @[Jalr.scala 13:22]
assign io_output = _T_3[31:0]; // @[Jalr.scala 13:15]
endmodule
module CsrPrimitive(
input clock,
input reset,
input [5:0] io_i_wrdata,
input io_i_wr_en,
output [5:0] io_o_rd_data
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [5:0] rdata_q; // @[CsrPrimitive.scala 13:24]
assign io_o_rd_data = rdata_q; // @[CsrPrimitive.scala 18:16]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
rdata_q = _RAND_0[5:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
rdata_q <= 6'hd;
end else if (io_i_wr_en) begin
rdata_q <= io_i_wrdata;
end
end
endmodule
module CsrPrimitive_1(
input clock,
input reset,
input [31:0] io_i_wrdata,
input io_i_wr_en,
output [31:0] io_o_rd_data
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [31:0] rdata_q; // @[CsrPrimitive.scala 13:24]
assign io_o_rd_data = rdata_q; // @[CsrPrimitive.scala 18:16]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
rdata_q = _RAND_0[31:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
rdata_q <= 32'h0;
end else if (io_i_wr_en) begin
rdata_q <= io_i_wrdata;
end
end
endmodule
module CsrPrimitive_2(
input clock,
input reset,
input [2:0] io_i_wrdata,
input io_i_wr_en,
output [2:0] io_o_rd_data
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [2:0] rdata_q; // @[CsrPrimitive.scala 13:24]
assign io_o_rd_data = rdata_q; // @[CsrPrimitive.scala 18:16]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
rdata_q = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
rdata_q <= 3'h4;
end else if (io_i_wr_en) begin
rdata_q <= io_i_wrdata;
end
end
endmodule
module CsrPrimitive_4(
input clock,
input reset,
input [5:0] io_i_wrdata,
input io_i_wr_en,
output [5:0] io_o_rd_data
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [5:0] rdata_q; // @[CsrPrimitive.scala 13:24]
assign io_o_rd_data = rdata_q; // @[CsrPrimitive.scala 18:16]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
rdata_q = _RAND_0[5:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
rdata_q <= 6'h0;
end else if (io_i_wr_en) begin
rdata_q <= io_i_wrdata;
end
end
endmodule
module CsrPrimitive_6(
input clock,
input reset,
input [31:0] io_i_wrdata,
input io_i_wr_en,
output [31:0] io_o_rd_data
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [31:0] rdata_q; // @[CsrPrimitive.scala 13:24]
assign io_o_rd_data = rdata_q; // @[CsrPrimitive.scala 18:16]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
rdata_q = _RAND_0[31:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
rdata_q <= 32'h1;
end else if (io_i_wr_en) begin
rdata_q <= io_i_wrdata;
end
end
endmodule
module CsrPrimitive_7(
input clock,
input reset,
input [27:0] io_i_wrdata,
input io_i_wr_en,
output [27:0] io_o_rd_data
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [27:0] rdata_q; // @[CsrPrimitive.scala 13:24]
assign io_o_rd_data = rdata_q; // @[CsrPrimitive.scala 18:16]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
rdata_q = _RAND_0[27:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
rdata_q <= 28'h0;
end else if (io_i_wr_en) begin
rdata_q <= io_i_wrdata;
end
end
endmodule
module BrqCounter(
input clock,
input reset,
input io_i_counter_inc,
input io_i_counterh_we,
input io_i_counter_we,
input [31:0] io_i_counter_val,
output [63:0] io_o_counter_val
);
`ifdef RANDOMIZE_REG_INIT
reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
wire we = io_i_counter_we | io_i_counterh_we; // @[BrqCounter.scala 27:35]
reg [63:0] counter_q; // @[BrqCounter.scala 57:26]
wire [31:0] counter_msb = io_i_counterh_we ? io_i_counter_val : counter_q[63:32]; // @[BrqCounter.scala 34:3]
wire [31:0] counter_lsb = io_i_counterh_we ? counter_q[31:0] : io_i_counter_val; // @[BrqCounter.scala 34:3]
wire [63:0] counter_load = {counter_msb,counter_lsb}; // @[Cat.scala 29:58]
wire [63:0] counter_upd = counter_q + 64'h1; // @[BrqCounter.scala 41:47]
assign io_o_counter_val = counter_q; // @[BrqCounter.scala 76:20]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {2{`RANDOM}};
counter_q = _RAND_0[63:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
counter_q <= 64'h0;
end else if (we) begin
counter_q <= counter_load;
end else if (io_i_counter_inc) begin
counter_q <= counter_upd;
end
end
endmodule
module BrqCounter_2(
input clock,
input reset,
input io_i_counter_inc,
input io_i_counterh_we,
input io_i_counter_we,
input [31:0] io_i_counter_val,
output [63:0] io_o_counter_val
);
`ifdef RANDOMIZE_REG_INIT
reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
wire we = io_i_counter_we | io_i_counterh_we; // @[BrqCounter.scala 27:35]
reg [39:0] counter_q; // @[BrqCounter.scala 57:26]
wire [79:0] _T_1 = {40'h0,counter_q}; // @[Cat.scala 29:58]
wire [63:0] counter = _T_1[63:0]; // @[BrqCounter.scala 16:21 BrqCounter.scala 28:16]
wire [31:0] counter_msb = io_i_counterh_we ? io_i_counter_val : counter[63:32]; // @[BrqCounter.scala 34:3]
wire [31:0] counter_lsb = io_i_counterh_we ? counter[31:0] : io_i_counter_val; // @[BrqCounter.scala 34:3]
wire [63:0] counter_load = {counter_msb,counter_lsb}; // @[Cat.scala 29:58]
wire [39:0] counter_upd = counter[39:0] + 40'h1; // @[BrqCounter.scala 41:47]
assign io_o_counter_val = _T_1[63:0]; // @[BrqCounter.scala 76:20]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {2{`RANDOM}};
counter_q = _RAND_0[39:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
counter_q <= 40'h0;
end else if (we) begin
counter_q <= counter_load[39:0];
end else if (io_i_counter_inc) begin
counter_q <= counter_upd;
end else begin
counter_q <= counter[39:0];
end
end
endmodule
module CsrRegisterFile(
input clock,
input reset,
output [31:0] io_o_csr_mtvec,
input io_i_csr_mtvec_init,
input io_i_csr_access,
input [11:0] io_i_csr_addr,
input [31:0] io_i_csr_wdata,
input [1:0] io_i_csr_op,
input io_i_csr_op_en,
output [31:0] io_o_csr_rdata,
input io_i_irq_external,
output io_o_irq_pending,
output [2:0] io_o_irqs,
output io_o_csr_mstatus_mie,
output [31:0] io_o_csr_mepc,
input [31:0] io_i_pc_if,
input io_i_csr_save_if,
input io_i_csr_restore_mret,
input io_i_csr_save_cause,
input [5:0] io_i_csr_mcause,
output io_o_illegal_csr_insn
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [63:0] _RAND_2;
reg [63:0] _RAND_3;
reg [63:0] _RAND_4;
reg [63:0] _RAND_5;
reg [63:0] _RAND_6;
reg [63:0] _RAND_7;
reg [63:0] _RAND_8;
reg [63:0] _RAND_9;
reg [63:0] _RAND_10;
reg [63:0] _RAND_11;
reg [63:0] _RAND_12;
reg [63:0] _RAND_13;
reg [63:0] _RAND_14;
reg [63:0] _RAND_15;
reg [63:0] _RAND_16;
reg [63:0] _RAND_17;
reg [63:0] _RAND_18;
reg [63:0] _RAND_19;
reg [63:0] _RAND_20;
reg [63:0] _RAND_21;
reg [63:0] _RAND_22;
reg [63:0] _RAND_23;
reg [63:0] _RAND_24;
reg [63:0] _RAND_25;
reg [63:0] _RAND_26;
reg [63:0] _RAND_27;
reg [63:0] _RAND_28;
reg [63:0] _RAND_29;
reg [63:0] _RAND_30;
reg [63:0] _RAND_31;
reg [63:0] _RAND_32;
reg [63:0] _RAND_33;
reg [31:0] _RAND_34;
reg [31:0] _RAND_35;
reg [31:0] _RAND_36;
reg [31:0] _RAND_37;
reg [31:0] _RAND_38;
reg [31:0] _RAND_39;
reg [31:0] _RAND_40;
reg [31:0] _RAND_41;
reg [31:0] _RAND_42;
reg [31:0] _RAND_43;
reg [31:0] _RAND_44;
reg [31:0] _RAND_45;
reg [31:0] _RAND_46;
reg [31:0] _RAND_47;
reg [31:0] _RAND_48;
reg [31:0] _RAND_49;
reg [31:0] _RAND_50;
reg [31:0] _RAND_51;
reg [31:0] _RAND_52;
reg [31:0] _RAND_53;
reg [31:0] _RAND_54;
reg [31:0] _RAND_55;
reg [31:0] _RAND_56;
reg [31:0] _RAND_57;
reg [31:0] _RAND_58;
reg [31:0] _RAND_59;
reg [31:0] _RAND_60;
reg [31:0] _RAND_61;
reg [31:0] _RAND_62;
reg [31:0] _RAND_63;
reg [31:0] _RAND_64;
reg [31:0] _RAND_65;
`endif // RANDOMIZE_REG_INIT
// wire PRIM_MSTATUS_clock; // @[CsrRegisterFile.scala 647:28]
// wire PRIM_MSTATUSreset; // @[CsrRegisterFile.scala 647:28]
wire [5:0] PRIM_MSTATUS_io_i_wrdata; // @[CsrRegisterFile.scala 647:28]
wire PRIM_MSTATUS_io_i_wr_en; // @[CsrRegisterFile.scala 647:28]
wire [5:0] PRIM_MSTATUS_io_o_rd_data; // @[CsrRegisterFile.scala 647:28]
// wire PRIM_MEPC_clock; // @[CsrRegisterFile.scala 653:25]
// wire PRIM_MEPCreset; // @[CsrRegisterFile.scala 653:25]
wire [31:0] PRIM_MEPC_io_i_wrdata; // @[CsrRegisterFile.scala 653:25]
wire PRIM_MEPC_io_i_wr_en; // @[CsrRegisterFile.scala 653:25]
wire [31:0] PRIM_MEPC_io_o_rd_data; // @[CsrRegisterFile.scala 653:25]
// wire PRIM_MIE_clock; // @[CsrRegisterFile.scala 664:24]
// wire PRIM_MIEreset; // @[CsrRegisterFile.scala 664:24]
wire [2:0] PRIM_MIE_io_i_wrdata; // @[CsrRegisterFile.scala 664:24]
wire PRIM_MIE_io_i_wr_en; // @[CsrRegisterFile.scala 664:24]
wire [2:0] PRIM_MIE_io_o_rd_data; // @[CsrRegisterFile.scala 664:24]
// wire PRIM_MSCRATCH_clock; // @[CsrRegisterFile.scala 671:29]
// wire PRIM_MSCRATCHreset; // @[CsrRegisterFile.scala 671:29]
wire [31:0] PRIM_MSCRATCH_io_i_wrdata; // @[CsrRegisterFile.scala 671:29]
wire PRIM_MSCRATCH_io_i_wr_en; // @[CsrRegisterFile.scala 671:29]
wire [31:0] PRIM_MSCRATCH_io_o_rd_data; // @[CsrRegisterFile.scala 671:29]
// wire PRIM_MCAUSE_clock; // @[CsrRegisterFile.scala 678:27]
// wire PRIM_MCAUSEreset; // @[CsrRegisterFile.scala 678:27]
wire [5:0] PRIM_MCAUSE_io_i_wrdata; // @[CsrRegisterFile.scala 678:27]
wire PRIM_MCAUSE_io_i_wr_en; // @[CsrRegisterFile.scala 678:27]
wire [5:0] PRIM_MCAUSE_io_o_rd_data; // @[CsrRegisterFile.scala 678:27]
// wire PRIM_MTVAL_clock; // @[CsrRegisterFile.scala 684:26]
// wire PRIM_MTVALreset; // @[CsrRegisterFile.scala 684:26]
wire [31:0] PRIM_MTVAL_io_i_wrdata; // @[CsrRegisterFile.scala 684:26]
wire PRIM_MTVAL_io_i_wr_en; // @[CsrRegisterFile.scala 684:26]
wire [31:0] PRIM_MTVAL_io_o_rd_data; // @[CsrRegisterFile.scala 684:26]
// wire PRIM_MTVEC_clock; // @[CsrRegisterFile.scala 691:26]
// wire PRIM_MTVECreset; // @[CsrRegisterFile.scala 691:26]
wire [31:0] PRIM_MTVEC_io_i_wrdata; // @[CsrRegisterFile.scala 691:26]
wire PRIM_MTVEC_io_i_wr_en; // @[CsrRegisterFile.scala 691:26]
wire [31:0] PRIM_MTVEC_io_o_rd_data; // @[CsrRegisterFile.scala 691:26]
// wire PRIM_DCSR_clock; // @[CsrRegisterFile.scala 701:25]
// wire PRIM_DCSRreset; // @[CsrRegisterFile.scala 701:25]
wire [27:0] PRIM_DCSR_io_i_wrdata; // @[CsrRegisterFile.scala 701:25]
wire PRIM_DCSR_io_i_wr_en; // @[CsrRegisterFile.scala 701:25]
wire [27:0] PRIM_DCSR_io_o_rd_data; // @[CsrRegisterFile.scala 701:25]
// wire PRIM_DEPC_clock; // @[CsrRegisterFile.scala 708:25]
//wire PRIM_DEPCreset; // @[CsrRegisterFile.scala 708:25]
wire [31:0] PRIM_DEPC_io_i_wrdata; // @[CsrRegisterFile.scala 708:25]
wire PRIM_DEPC_io_i_wr_en; // @[CsrRegisterFile.scala 708:25]
wire [31:0] PRIM_DEPC_io_o_rd_data; // @[CsrRegisterFile.scala 708:25]
// wire PRIM_DSCRATCH0_clock; // @[CsrRegisterFile.scala 714:30]
//wire PRIM_DSCRATCH0reset; // @[CsrRegisterFile.scala 714:30]
wire [31:0] PRIM_DSCRATCH0_io_i_wrdata; // @[CsrRegisterFile.scala 714:30]
wire PRIM_DSCRATCH0_io_i_wr_en; // @[CsrRegisterFile.scala 714:30]
wire [31:0] PRIM_DSCRATCH0_io_o_rd_data; // @[CsrRegisterFile.scala 714:30]
//wire PRIM_DSCRATCH1_clock; // @[CsrRegisterFile.scala 721:30]
// wire PRIM_DSCRATCH1reset; // @[CsrRegisterFile.scala 721:30]
wire [31:0] PRIM_DSCRATCH1_io_i_wrdata; // @[CsrRegisterFile.scala 721:30]
wire PRIM_DSCRATCH1_io_i_wr_en; // @[CsrRegisterFile.scala 721:30]
wire [31:0] PRIM_DSCRATCH1_io_o_rd_data; // @[CsrRegisterFile.scala 721:30]
//wire COUNT_MCYCLE_clock; // @[CsrRegisterFile.scala 777:28]
// wire COUNT_MCYCLEreset; // @[CsrRegisterFile.scala 777:28]
wire COUNT_MCYCLE_io_i_counter_inc; // @[CsrRegisterFile.scala 777:28]
wire COUNT_MCYCLE_io_i_counterh_we; // @[CsrRegisterFile.scala 777:28]
wire COUNT_MCYCLE_io_i_counter_we; // @[CsrRegisterFile.scala 777:28]
wire [31:0] COUNT_MCYCLE_io_i_counter_val; // @[CsrRegisterFile.scala 777:28]
wire [63:0] COUNT_MCYCLE_io_o_counter_val; // @[CsrRegisterFile.scala 777:28]
//wire COUNT_MINSTRET_clock; // @[CsrRegisterFile.scala 785:30]
// wire COUNT_MINSTRETreset; // @[CsrRegisterFile.scala 785:30]
wire COUNT_MINSTRET_io_i_counter_inc; // @[CsrRegisterFile.scala 785:30]
wire COUNT_MINSTRET_io_i_counterh_we; // @[CsrRegisterFile.scala 785:30]
wire COUNT_MINSTRET_io_i_counter_we; // @[CsrRegisterFile.scala 785:30]
wire [31:0] COUNT_MINSTRET_io_i_counter_val; // @[CsrRegisterFile.scala 785:30]
wire [63:0] COUNT_MINSTRET_io_o_counter_val; // @[CsrRegisterFile.scala 785:30]
//wire BrqCounter_clock; // @[CsrRegisterFile.scala 797:26]
// wire BrqCounterreset; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_io_i_counter_inc; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_io_i_counterh_we; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_io_i_counter_we; // @[CsrRegisterFile.scala 797:26]
wire [31:0] BrqCounter_io_i_counter_val; // @[CsrRegisterFile.scala 797:26]
wire [63:0] BrqCounter_io_o_counter_val; // @[CsrRegisterFile.scala 797:26]
//wire BrqCounter_1_clock; // @[CsrRegisterFile.scala 797:26]
// wire BrqCounter_1reset; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_1_io_i_counter_inc; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_1_io_i_counterh_we; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_1_io_i_counter_we; // @[CsrRegisterFile.scala 797:26]
wire [31:0] BrqCounter_1_io_i_counter_val; // @[CsrRegisterFile.scala 797:26]
wire [63:0] BrqCounter_1_io_o_counter_val; // @[CsrRegisterFile.scala 797:26]
//wire BrqCounter_2_clock; // @[CsrRegisterFile.scala 797:26]
// wire BrqCounter_2reset; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_2_io_i_counter_inc; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_2_io_i_counterh_we; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_2_io_i_counter_we; // @[CsrRegisterFile.scala 797:26]
wire [31:0] BrqCounter_2_io_i_counter_val; // @[CsrRegisterFile.scala 797:26]
wire [63:0] BrqCounter_2_io_o_counter_val; // @[CsrRegisterFile.scala 797:26]
//wire BrqCounter_3_clock; // @[CsrRegisterFile.scala 797:26]
// wire BrqCounter_3reset; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_3_io_i_counter_inc; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_3_io_i_counterh_we; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_3_io_i_counter_we; // @[CsrRegisterFile.scala 797:26]
wire [31:0] BrqCounter_3_io_i_counter_val; // @[CsrRegisterFile.scala 797:26]
wire [63:0] BrqCounter_3_io_o_counter_val; // @[CsrRegisterFile.scala 797:26]
//wire BrqCounter_4_clock; // @[CsrRegisterFile.scala 797:26]
// wire BrqCounter_4reset; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_4_io_i_counter_inc; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_4_io_i_counterh_we; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_4_io_i_counter_we; // @[CsrRegisterFile.scala 797:26]
wire [31:0] BrqCounter_4_io_i_counter_val; // @[CsrRegisterFile.scala 797:26]
wire [63:0] BrqCounter_4_io_o_counter_val; // @[CsrRegisterFile.scala 797:26]
// wire BrqCounter_5_clock; // @[CsrRegisterFile.scala 797:26]
// wire BrqCounter_5reset; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_5_io_i_counter_inc; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_5_io_i_counterh_we; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_5_io_i_counter_we; // @[CsrRegisterFile.scala 797:26]
wire [31:0] BrqCounter_5_io_i_counter_val; // @[CsrRegisterFile.scala 797:26]
wire [63:0] BrqCounter_5_io_o_counter_val; // @[CsrRegisterFile.scala 797:26]
// wire BrqCounter_6_clock; // @[CsrRegisterFile.scala 797:26]
// wire BrqCounter_6reset; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_6_io_i_counter_inc; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_6_io_i_counterh_we; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_6_io_i_counter_we; // @[CsrRegisterFile.scala 797:26]
wire [31:0] BrqCounter_6_io_i_counter_val; // @[CsrRegisterFile.scala 797:26]
wire [63:0] BrqCounter_6_io_o_counter_val; // @[CsrRegisterFile.scala 797:26]
// wire BrqCounter_7_clock; // @[CsrRegisterFile.scala 797:26]
// wire BrqCounter_7reset; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_7_io_i_counter_inc; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_7_io_i_counterh_we; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_7_io_i_counter_we; // @[CsrRegisterFile.scala 797:26]
wire [31:0] BrqCounter_7_io_i_counter_val; // @[CsrRegisterFile.scala 797:26]
wire [63:0] BrqCounter_7_io_o_counter_val; // @[CsrRegisterFile.scala 797:26]
//wire BrqCounter_8_clock; // @[CsrRegisterFile.scala 797:26]
// wire BrqCounter_8reset; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_8_io_i_counter_inc; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_8_io_i_counterh_we; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_8_io_i_counter_we; // @[CsrRegisterFile.scala 797:26]
wire [31:0] BrqCounter_8_io_i_counter_val; // @[CsrRegisterFile.scala 797:26]
wire [63:0] BrqCounter_8_io_o_counter_val; // @[CsrRegisterFile.scala 797:26]
//wire BrqCounter_9_clock; // @[CsrRegisterFile.scala 797:26]
// wire BrqCounter_9reset; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_9_io_i_counter_inc; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_9_io_i_counterh_we; // @[CsrRegisterFile.scala 797:26]
wire BrqCounter_9_io_i_counter_we; // @[CsrRegisterFile.scala 797:26]
wire [31:0] BrqCounter_9_io_i_counter_val; // @[CsrRegisterFile.scala 797:26]
wire [63:0] BrqCounter_9_io_o_counter_val; // @[CsrRegisterFile.scala 797:26]
reg [1:0] priv_lvl_q; // @[CsrRegisterFile.scala 100:27]
reg [12:0] mcountinhibit_q; // @[CsrRegisterFile.scala 133:49]
reg [63:0] mhpmcounter_0; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_1; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_2; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_3; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_4; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_5; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_6; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_7; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_8; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_9; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_10; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_11; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_12; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_13; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_14; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_15; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_16; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_17; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_18; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_19; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_20; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_21; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_22; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_23; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_24; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_25; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_26; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_27; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_28; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_29; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_30; // @[CsrRegisterFile.scala 137:49]
reg [63:0] mhpmcounter_31; // @[CsrRegisterFile.scala 137:49]
reg [31:0] mhpmevent_0; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_1; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_2; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_3; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_4; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_5; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_6; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_7; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_8; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_9; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_10; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_11; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_12; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_13; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_14; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_15; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_16; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_17; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_18; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_19; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_20; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_21; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_22; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_23; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_24; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_25; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_26; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_27; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_28; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_29; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_30; // @[CsrRegisterFile.scala 142:49]
reg [31:0] mhpmevent_31; // @[CsrRegisterFile.scala 142:49]
wire illegal_csr_priv = io_i_csr_addr[9:8] > priv_lvl_q; // @[CsrRegisterFile.scala 201:43]
wire _T_39 = io_i_csr_addr[11:10] == 2'h3; // @[CsrRegisterFile.scala 203:47]
wire _T_514 = io_i_csr_op == 2'h1; // @[CsrRegisterFile.scala 618:47]
wire _T_515 = io_i_csr_op == 2'h2; // @[CsrRegisterFile.scala 618:89]
wire _T_516 = _T_514 | _T_515; // @[CsrRegisterFile.scala 618:74]
wire _T_517 = io_i_csr_op == 2'h3; // @[CsrRegisterFile.scala 618:129]
wire _T_518 = _T_516 | _T_517; // @[CsrRegisterFile.scala 618:114]
wire csr_wreq = io_i_csr_op_en & _T_518; // @[CsrRegisterFile.scala 618:31]
wire illegal_csr_write = _T_39 & csr_wreq; // @[CsrRegisterFile.scala 203:60]
wire _T_44 = io_i_csr_addr == 12'hf14; // @[CsrRegisterFile.scala 218:22]
wire _T_45 = io_i_csr_addr == 12'h300; // @[CsrRegisterFile.scala 223:29]
wire _T_56 = io_i_csr_addr == 12'h301; // @[CsrRegisterFile.scala 231:29]
wire _T_57 = io_i_csr_addr == 12'h304; // @[CsrRegisterFile.scala 236:29]
wire _T_64 = io_i_csr_addr == 12'h340; // @[CsrRegisterFile.scala 244:29]
wire _T_65 = io_i_csr_addr == 12'h305; // @[CsrRegisterFile.scala 250:29]
wire _T_66 = io_i_csr_addr == 12'h341; // @[CsrRegisterFile.scala 259:29]
wire _T_67 = io_i_csr_addr == 12'h342; // @[CsrRegisterFile.scala 265:29]
wire _T_72 = io_i_csr_addr == 12'h343; // @[CsrRegisterFile.scala 272:29]
wire _T_73 = io_i_csr_addr == 12'h344; // @[CsrRegisterFile.scala 277:29]
wire _T_80 = io_i_csr_addr == 12'h7b0; // @[CsrRegisterFile.scala 285:29]
wire _T_95 = io_i_csr_addr == 12'h7b1; // @[CsrRegisterFile.scala 290:29]
wire _T_97 = io_i_csr_addr == 12'h7b2; // @[CsrRegisterFile.scala 295:29]
wire _T_98 = io_i_csr_addr == 12'h7b3; // @[CsrRegisterFile.scala 299:29]
wire _T_100 = io_i_csr_addr == 12'h320; // @[CsrRegisterFile.scala 305:29]
wire _T_101 = io_i_csr_addr == 12'h323; // @[CsrRegisterFile.scala 310:30]
wire _T_102 = io_i_csr_addr == 12'h324; // @[CsrRegisterFile.scala 310:77]
wire _T_103 = _T_101 | _T_102; // @[CsrRegisterFile.scala 310:60]
wire _T_104 = io_i_csr_addr == 12'h325; // @[CsrRegisterFile.scala 310:124]
wire _T_105 = _T_103 | _T_104; // @[CsrRegisterFile.scala 310:107]
wire _T_106 = io_i_csr_addr == 12'h326; // @[CsrRegisterFile.scala 310:171]
wire _T_107 = _T_105 | _T_106; // @[CsrRegisterFile.scala 310:154]
wire _T_108 = io_i_csr_addr == 12'h327; // @[CsrRegisterFile.scala 311:22]
wire _T_109 = _T_107 | _T_108; // @[CsrRegisterFile.scala 310:201]
wire _T_110 = io_i_csr_addr == 12'h328; // @[CsrRegisterFile.scala 311:69]
wire _T_111 = _T_109 | _T_110; // @[CsrRegisterFile.scala 311:52]
wire _T_112 = io_i_csr_addr == 12'h329; // @[CsrRegisterFile.scala 311:116]
wire _T_113 = _T_111 | _T_112; // @[CsrRegisterFile.scala 311:99]
wire _T_114 = io_i_csr_addr == 12'h32a; // @[CsrRegisterFile.scala 311:163]
wire _T_115 = _T_113 | _T_114; // @[CsrRegisterFile.scala 311:146]
wire _T_116 = io_i_csr_addr == 12'h32b; // @[CsrRegisterFile.scala 312:22]
wire _T_117 = _T_115 | _T_116; // @[CsrRegisterFile.scala 311:193]
wire _T_118 = io_i_csr_addr == 12'h32c; // @[CsrRegisterFile.scala 312:69]
wire _T_119 = _T_117 | _T_118; // @[CsrRegisterFile.scala 312:52]
wire _T_120 = io_i_csr_addr == 12'h32d; // @[CsrRegisterFile.scala 312:116]
wire _T_121 = _T_119 | _T_120; // @[CsrRegisterFile.scala 312:99]
wire _T_122 = io_i_csr_addr == 12'h32e; // @[CsrRegisterFile.scala 312:163]
wire _T_123 = _T_121 | _T_122; // @[CsrRegisterFile.scala 312:146]
wire _T_124 = io_i_csr_addr == 12'h32f; // @[CsrRegisterFile.scala 313:22]
wire _T_125 = _T_123 | _T_124; // @[CsrRegisterFile.scala 312:193]
wire _T_126 = io_i_csr_addr == 12'h330; // @[CsrRegisterFile.scala 313:69]
wire _T_127 = _T_125 | _T_126; // @[CsrRegisterFile.scala 313:52]
wire _T_128 = io_i_csr_addr == 12'h331; // @[CsrRegisterFile.scala 313:116]
wire _T_129 = _T_127 | _T_128; // @[CsrRegisterFile.scala 313:99]
wire _T_130 = io_i_csr_addr == 12'h332; // @[CsrRegisterFile.scala 313:163]
wire _T_131 = _T_129 | _T_130; // @[CsrRegisterFile.scala 313:146]
wire _T_132 = io_i_csr_addr == 12'h333; // @[CsrRegisterFile.scala 314:22]
wire _T_133 = _T_131 | _T_132; // @[CsrRegisterFile.scala 313:193]
wire _T_134 = io_i_csr_addr == 12'h334; // @[CsrRegisterFile.scala 314:69]
wire _T_135 = _T_133 | _T_134; // @[CsrRegisterFile.scala 314:52]
wire _T_136 = io_i_csr_addr == 12'h335; // @[CsrRegisterFile.scala 314:116]
wire _T_137 = _T_135 | _T_136; // @[CsrRegisterFile.scala 314:99]
wire _T_138 = io_i_csr_addr == 12'h336; // @[CsrRegisterFile.scala 314:163]
wire _T_139 = _T_137 | _T_138; // @[CsrRegisterFile.scala 314:146]
wire _T_140 = io_i_csr_addr == 12'h337; // @[CsrRegisterFile.scala 315:22]
wire _T_141 = _T_139 | _T_140; // @[CsrRegisterFile.scala 314:193]
wire _T_142 = io_i_csr_addr == 12'h338; // @[CsrRegisterFile.scala 315:69]
wire _T_143 = _T_141 | _T_142; // @[CsrRegisterFile.scala 315:52]
wire _T_144 = io_i_csr_addr == 12'h339; // @[CsrRegisterFile.scala 315:116]
wire _T_145 = _T_143 | _T_144; // @[CsrRegisterFile.scala 315:99]
wire _T_146 = io_i_csr_addr == 12'h33a; // @[CsrRegisterFile.scala 315:163]
wire _T_147 = _T_145 | _T_146; // @[CsrRegisterFile.scala 315:146]
wire _T_148 = io_i_csr_addr == 12'h33b; // @[CsrRegisterFile.scala 316:22]
wire _T_149 = _T_147 | _T_148; // @[CsrRegisterFile.scala 315:193]
wire _T_150 = io_i_csr_addr == 12'h33c; // @[CsrRegisterFile.scala 316:69]
wire _T_151 = _T_149 | _T_150; // @[CsrRegisterFile.scala 316:52]
wire _T_152 = io_i_csr_addr == 12'h33d; // @[CsrRegisterFile.scala 316:116]
wire _T_153 = _T_151 | _T_152; // @[CsrRegisterFile.scala 316:99]
wire _T_154 = io_i_csr_addr == 12'h33e; // @[CsrRegisterFile.scala 316:163]
wire _T_155 = _T_153 | _T_154; // @[CsrRegisterFile.scala 316:146]
wire _T_156 = io_i_csr_addr == 12'h33f; // @[CsrRegisterFile.scala 317:22]
wire _T_157 = _T_155 | _T_156; // @[CsrRegisterFile.scala 316:193]
wire _T_158 = io_i_csr_addr == 12'hb00; // @[CsrRegisterFile.scala 321:30]
wire _T_159 = io_i_csr_addr == 12'hb02; // @[CsrRegisterFile.scala 321:79]
wire _T_160 = _T_158 | _T_159; // @[CsrRegisterFile.scala 321:62]
wire _T_161 = io_i_csr_addr == 12'hb03; // @[CsrRegisterFile.scala 321:128]
wire _T_162 = _T_160 | _T_161; // @[CsrRegisterFile.scala 321:111]
wire _T_163 = io_i_csr_addr == 12'hb04; // @[CsrRegisterFile.scala 321:177]
wire _T_164 = _T_162 | _T_163; // @[CsrRegisterFile.scala 321:160]
wire _T_165 = io_i_csr_addr == 12'hb05; // @[CsrRegisterFile.scala 322:22]
wire _T_166 = _T_164 | _T_165; // @[CsrRegisterFile.scala 321:209]
wire _T_167 = io_i_csr_addr == 12'hb06; // @[CsrRegisterFile.scala 322:71]
wire _T_168 = _T_166 | _T_167; // @[CsrRegisterFile.scala 322:54]
wire _T_169 = io_i_csr_addr == 12'hb07; // @[CsrRegisterFile.scala 322:120]
wire _T_170 = _T_168 | _T_169; // @[CsrRegisterFile.scala 322:103]
wire _T_171 = io_i_csr_addr == 12'hb08; // @[CsrRegisterFile.scala 322:169]
wire _T_172 = _T_170 | _T_171; // @[CsrRegisterFile.scala 322:152]
wire _T_173 = io_i_csr_addr == 12'hb09; // @[CsrRegisterFile.scala 323:22]
wire _T_174 = _T_172 | _T_173; // @[CsrRegisterFile.scala 322:201]
wire _T_175 = io_i_csr_addr == 12'hb0a; // @[CsrRegisterFile.scala 323:71]
wire _T_176 = _T_174 | _T_175; // @[CsrRegisterFile.scala 323:54]
wire _T_177 = io_i_csr_addr == 12'hb0b; // @[CsrRegisterFile.scala 323:120]
wire _T_178 = _T_176 | _T_177; // @[CsrRegisterFile.scala 323:103]
wire _T_179 = io_i_csr_addr == 12'hb0c; // @[CsrRegisterFile.scala 323:169]
wire _T_180 = _T_178 | _T_179; // @[CsrRegisterFile.scala 323:152]
wire _T_181 = io_i_csr_addr == 12'hb0d; // @[CsrRegisterFile.scala 324:22]
wire _T_182 = _T_180 | _T_181; // @[CsrRegisterFile.scala 323:201]
wire _T_183 = io_i_csr_addr == 12'hb0e; // @[CsrRegisterFile.scala 324:71]
wire _T_184 = _T_182 | _T_183; // @[CsrRegisterFile.scala 324:54]
wire _T_185 = io_i_csr_addr == 12'hb0f; // @[CsrRegisterFile.scala 324:120]
wire _T_186 = _T_184 | _T_185; // @[CsrRegisterFile.scala 324:103]
wire _T_187 = io_i_csr_addr == 12'hb10; // @[CsrRegisterFile.scala 324:169]
wire _T_188 = _T_186 | _T_187; // @[CsrRegisterFile.scala 324:152]
wire _T_189 = io_i_csr_addr == 12'hb11; // @[CsrRegisterFile.scala 325:22]
wire _T_190 = _T_188 | _T_189; // @[CsrRegisterFile.scala 324:201]
wire _T_191 = io_i_csr_addr == 12'hb12; // @[CsrRegisterFile.scala 325:71]
wire _T_192 = _T_190 | _T_191; // @[CsrRegisterFile.scala 325:54]
wire _T_193 = io_i_csr_addr == 12'hb13; // @[CsrRegisterFile.scala 325:120]
wire _T_194 = _T_192 | _T_193; // @[CsrRegisterFile.scala 325:103]
wire _T_195 = io_i_csr_addr == 12'hb14; // @[CsrRegisterFile.scala 325:169]
wire _T_196 = _T_194 | _T_195; // @[CsrRegisterFile.scala 325:152]
wire _T_197 = io_i_csr_addr == 12'hb15; // @[CsrRegisterFile.scala 326:22]
wire _T_198 = _T_196 | _T_197; // @[CsrRegisterFile.scala 325:201]
wire _T_199 = io_i_csr_addr == 12'hb16; // @[CsrRegisterFile.scala 326:71]
wire _T_200 = _T_198 | _T_199; // @[CsrRegisterFile.scala 326:54]
wire _T_201 = io_i_csr_addr == 12'hb17; // @[CsrRegisterFile.scala 326:120]
wire _T_202 = _T_200 | _T_201; // @[CsrRegisterFile.scala 326:103]
wire _T_203 = io_i_csr_addr == 12'hb18; // @[CsrRegisterFile.scala 326:169]
wire _T_204 = _T_202 | _T_203; // @[CsrRegisterFile.scala 326:152]
wire _T_205 = io_i_csr_addr == 12'hb19; // @[CsrRegisterFile.scala 327:22]