tree: f48f86c016afbca470556faf77afe8c029470c1f [path history] [tgz]
  1. .github/
  2. docs/
  3. project/
  4. src/
  5. .gitignore
  6. build.sbt
  8. scalastyle-config.xml
  9. scalastyle-test-config.xml

TileLink GitHub Workflow Status

This project deals with creating TileLink bus protocol API with Chisel and generating the RTL for synthesis


TileLink is a protocol developed at SiFive which is used for On-Chip communication. This project implements the TileLink Uncached Lightweight (TL-UL) protocol as described in the specification. This project conforms to the 1.7.1 specification.


TileLink has been implemented in rocketchip but it takes use of diplomacy which is a little advanced stuff to understand. In this project we implement the specification with only the logic provided by the specification and hope to keep it simple enough for other Chisel users to use it in their projects without the need of LazyModules and complex diplomacy negotiation.