|author||Hadir Khan <email@example.com>||Thu Dec 03 00:22:20 2020 +0500|
|committer||Hadir Khan <firstname.lastname@example.org>||Thu Dec 03 00:22:20 2020 +0500|
Added source RTL design in chisel
ابتدا means the start of something. This is a minimal SoC built around a RISC-V based 5 stage pipelined core Buraq-Mini. Both the SoC and the core are made from scratch using CHISEL HDL. The CHISEL source code as well as the emitted verilog are provided in the relvant folders. It is still Work In Progress (WIP). The current SoC architecture is given below.
Main contributors are: