Block diagram of the Spectravel is given below and detailed explanation of the each block is given inside submodules
This directory contains following submodules and directories:
spectrometer- contains digital spectrometer generator with built in test structures designed in Chisel HDL
wb2axip- contains wishbone to AXI4 bridge. Current submodule is forked version of the ZipCPU/wb2axip
doc- contains global block scheme of the
Spectravelblock in svg and png format.
top/dv/SpectrometerTest- contains verilog testbenches for Spectravel integrated with Caravel
user_proj_example.vwhich is the top level verilog file for Spectravel
Before running make commands, we could set the size of FFT inside spectrometer. Default size is 128. For example, we could set the size of the FFT inside spectrometer to be equal to 256 with the command:
$ export SIZE=256
To run verilog generation and Chisel tests, sbt and verilator must be installed. For installation details see this link.
In order to generate verilog file SpectrometerTest.v which contains verilog code for digital spectrometer, run command:
$ make verilog_spectrometer
To run chisel tests for digital spectrometer, run command:
$ make test_spectrometer
In order to run verilog tests for Spectravel connected to Caravel, PDK_ROOT and RISCV32 paths must be set. RISCV32 is path to RV32I Toolchain. For RV32I toolchain installation click here. To check if paths are set, run command:
$ make check-env
Currently there are four different tests for Spectravel connected to Caravel:
All tests contain C code where appropriate Spectravel registers are set in order to obtain desired functionality. Output of the Spectravel is compared with golden model generated with Chisel. In order for test to pass, Spectravel output data must be the same as golden model data.
By default, caravel_spectrometer repository contains all data needed to run verilog tests. Thus, verilog tests can be run without installing sbt.
In order to test Spectravel added to the Caravel, run command:
$ make test_top
To clean data generated by verilog testbenches, run:
$ make clean_top
In order to regenerate verilog code, run chisel tests and run Spectravel tests, run command:
$ make run_all
User address space 0x3000_0000 ├── in_split: 0x3000_0000 ├── plfg_ram: 0x3000_1000 ├── plfg: 0x3000_2100 ├── plfg_split: 0x3000_2200 ├── plfg_mux_0: 0x3000_2210 ├── plfg_mux_1: 0x3000_2220 ├── nco: 0x3000_3000 ├── nco_split: 0x3000_3100 ├── nco_mux_0: 0x3000_3110 ├── nco_mux_1: 0x3000_3120 ├── fft: 0x3000_4000 ├── fft_split: 0x3000_4100 ├── fft_mux_0 0x3000_4110 ├── fft_mux_1: 0x3000_4120 ├── mag: 0x3000_5000 ├── mag_split: 0x3000_5100 ├── mag_mux_0: 0x3000_5110 ├── mag_mux_1: 0x3000_5120 ├── acc_queue: 0x3000_6000 ├── acc: 0x3000_7000 ├── out_mux: 0x3000_8000 ├── out_split: 0x3000_8010 ├── uart: 0x3000_9000 └── uart_split: 0x3000_9100