mpw-one-b-0.9 DRC:0 LVS:0
69 files changed
tree: 7dfce1e09d9399716051d6783c8a9dfa57317e6b
  1. .travis.yml
  2. .travisCI/
  3. LICENSE
  4. Makefile
  5. README.md
  6. def/
  7. doc/
  8. gds/
  9. info.yaml
  10. lef/
  11. macros/
  12. mag/
  13. maglef/
  14. mpw-one-b.md
  15. ngspice/
  16. openlane/
  17. qflow/
  18. scripts/
  19. spi/
  20. user_proj_example.log
  21. user_project_wrapper.log
  22. utils/
  23. verilog/
README.md

SKY130 SHA3 Miner Caravel SOC

miner

Table of Contents

Introduction

In mining a proof-of-work (POW) is used to verify the authenticity of a blockchain entry. What is a POW? A POW is a mathematical puzzle which is difficul to solve but easy to verify.

For this example a SHA3 mining core is defined for a hypothetical blockchain that uses the SHA3-256 hash. Finding a hash that meets certain conditions is difficult, verifying it does is simple.

The core is implemented on Skywater's SKY130 process curtesy of the Open MPW Shuttle Program sponsored by Google.

We are given:

  • H: 256 bit header (Fixed value input)
  • N: 64 bit nonce (The value we must find)
  • D: 256 bit difficulty (Problem difficulty, smaller value = more difficult)

The problem we need to solve is to find any value of N, such that the SHA3-256 hash of the nonce concatenated to the header, is less than or equal to the difficulty:

D >= SHA3({H, N})

NOTE: This will not mine a real blockchain. It intended as an exaple of hashing algorithm optimized for mining using a multi-stage permutation pipeline.

Implementation

This ASIC is generated using end-to-end open source EDA tools. A 12 stage pipeline design is used in two phases since a fully unrolled 24 stage pipeline exceeds the capacity of this ASIC.

Miner Component

The component is an Wishbone bus device with a 23 word memory mapped register file for control and status. All user project Verilog source is contained in the verilog/rtl/sha3_256_miner* files/

User block interface.

SignalWidthDescription
wb_clk_i150MHz Wishbone bus clock (1-bit input)
wb_rst_i1Asynchronous reset (1-bit input)
wbs_stb_i1Select
wbs_cyc_i1Active bus cycle
wbs_we_i1Write enable
wbs_sel_i4Byte lane select
wbs_dat_i32Input data
wbs_adr_i32Address
wbs_ack_o1Bus ccycle acknowledge
wbs_dat_o32Output data
io_inMPRJ_IO_PADSIO pin bus input
io_outMPRJ_IO_PADSIO pin bus output
io_oebMPRJ_IO_PADSIO pin bus output enable
user_clock21300 MHz miner core clock
irq_o1Ative high when solution found (1-bit output)

Register file

Reg. #NameRead/WriteDescription
0-1SOLN_REGRO64-bit Solution
2STATUS_REGROStatus (see below)
3SHA3_REGROFingerprint “SHA3”
4-11HDR_REGRW256-bit Header
12-19DIFF_REGRW256-bit difficulty
20-21START_REGRW64-bit start nonce
22CTL_REGRWControl (see below)

Status register

Bit #NameDescription
0FOUNDSolution found. Solution is stored and IRQ is set. IRQ cleared with next ctl. reg. read.
1RUNNINGThe run ctl bit is set and the solution nonce is auto-incrementing
2TESTINGThe test ctl bit is set and compare diff equal

Control register

Bit #NameDescription
0RUN0 - clear, 1 - auto increment the solution nonce and check hashes
1TEST0 - normal mode, 1 - test mode, look for exact match with diff
2HALT0 - normal mode, 1 - halt mining and raise interrupt
23-16PAD_LASTlast pad byte, 0x80 for KECCACK-256 and SHA3-256
31-24PAD_FIRSTfirst pad byte, 0x01 for KECCACK-256, and 0x06 for SHA3-256

Verilog Module Hierarchy

Top module:  \user_proj_example
Used module:     \sha3_256_miner_core
Used module:         \sha3_256_miner_round
Used module:             \permutation
Used module:     \sha3_256_miner_regs
Parameter \STAGES = 8

Building

Prerequisites

Caravel

Openlane

Google Skywater PDK

Synthesizing

From the command line:

git clone https://github.com/miscellaneousbits/caravel_sha3_256_crypto_miner.git
cd caravel_sha3_256_miner/openlane
make user_proj_example
make user_project_wrapper
cd ..
make ship

This will create the artifacts for sending to the fab.

NOTE: This project is borderline routable at this point. Since the autorouter starts off with a random seed, it will occasionally not converge on 0 violations.

Future

Currently this 12 stage pipeline design is fully autorouted and uses about 990,000 cells and is the most that can be crammed into the available die space. The layout is very sparse in order to get successful routing. It may be possible to optimize and harden smaller repeating blocks the place then manually to achieve a fully unrolled 24 stage pipeline. This would achieve twice the performance of the current version.

Picorv32 Firmware

TBD

Acknowledgments

Many thanks to Mohamed Kassem, Tim Edwards, Sylvain Munaut, Philipp G├╝hring, and many others without whose help this project would not be possible.

Long live open-everything.