blob: 665e56dc3a9d4d821f42d664eca3d34c9c0f93a7 [file] [log] [blame]
###############################################
[INFO]:
___ ____ ___ ____ _ ____ ____ ___
/ \ | \ / _]| \ | | / || \ / _]
| || o ) [_ | _ || | | o || _ | / [_
| O || _/ _]| | || |___ | || | || _]
| || | | [_ | | || || _ || | || [_
\___/ |__| |_____||__|__||_____||__|__||__|__||_____|

[INFO]: Version: mpw-one-b
[INFO]: Running non-interactively
[INFO]: Using design configuration at /project/openlane/user_project_wrapper/config.tcl
[INFO]: Sourcing Configurations from /project/openlane/user_project_wrapper/config.tcl
[INFO]: PDKs root directory: /home/jcyr/openlane/pdks
[INFO]: PDK: sky130A
[INFO]: Setting PDKPATH to /home/jcyr/openlane/pdks/sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /project/openlane/user_project_wrapper/config.tcl
[INFO]: Current run directory is /project/openlane/user_project_wrapper/runs/user_project_wrapper
[INFO]: Preparing LEF Files
mergeLef.py : Merging LEFs
sky130_ef_sc_hd__fakediode_2.lef: SITEs matched found: 0
sky130_ef_sc_hd__fakediode_2.lef: MACROs matched found: 1
sky130_fd_sc_hd.lef: SITEs matched found: 0
sky130_fd_sc_hd.lef: MACROs matched found: 437
mergeLef.py : Merging LEFs complete
mergeLef.py : Merging LEFs
user_proj_example.lef: SITEs matched found: 0
user_proj_example.lef: MACROs matched found: 1
mergeLef.py : Merging LEFs complete
[INFO]: Merging the following extra LEFs: /project/openlane/user_project_wrapper/../../lef/user_proj_example.lef
[INFO]: Trimming Liberty...
[INFO]: Preparation complete
[INFO]: Running Synthesis...
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
1. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/user_project_wrapper/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v
Parsing Verilog input from `/project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v' to AST representation.
Generating RTLIL representation for module `\user_proj_example'.
Warning: Replacing memory \status_r with list of registers. See /project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v:135
Warning: Replacing memory \solution_r with list of registers. See /project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v:133
Generating RTLIL representation for module `\sha3_256_miner_regs'.
Generating RTLIL representation for module `\sha3_256_miner_core_248'.
Warning: Replacing memory \ctl_r with list of registers. See /project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v:277, /project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v:276
Generating RTLIL representation for module `\sha3_256_miner_core_12'.
Warning: Replacing memory \ctl_r with list of registers. See /project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v:435, /project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v:434
Generating RTLIL representation for module `\sha3_256_miner_round'.
Generating RTLIL representation for module `\permutation'.
Successfully finished Verilog frontend.
3. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/user_project_wrapper/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.
4. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v
Parsing Verilog input from `/project/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v' to AST representation.
Generating RTLIL representation for module `\user_project_wrapper'.
Successfully finished Verilog frontend.
5. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/synthesis/hierarchy.dot'.
Dumping module user_project_wrapper to page 1.
6. Executing HIERARCHY pass (managing design hierarchy).
6.1. Analyzing design hierarchy..
Top module: \user_project_wrapper
6.2. Analyzing design hierarchy..
Top module: \user_project_wrapper
Removed 0 unused modules.
7. Printing statistics.
=== user_project_wrapper ===
Number of wires: 18
Number of wire bits: 636
Number of public wires: 18
Number of public wire bits: 636
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 1
user_proj_example 1
8. Executing SPLITNETS pass (splitting up multi-bit signals).
9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..
10. Executing CHECK pass (checking for obvious problems).
checking module user_project_wrapper..
found and reported 0 problems.
11. Printing statistics.
=== user_project_wrapper ===
Number of wires: 18
Number of wire bits: 636
Number of public wires: 18
Number of public wire bits: 636
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 1
user_proj_example 1
Area for cell type \user_proj_example is unknown!
12. Executing Verilog backend.
Dumping module `\user_project_wrapper'.
Warnings: 4 unique messages, 4 total
End of script. Logfile hash: 6888d33be3, CPU: user 0.10s system 0.00s, MEM: 14.46 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 70% 8x read_verilog (0 sec), 24% 2x stat (0 sec), ...
[INFO]: Changing netlist from 0 to /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/synthesis/user_project_wrapper.synthesis.v
[INFO]: Running Static Timing Analysis...
OpenSTA 2.2.0 7662c12482 Copyright (c) 2019, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>
This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details.
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
Error: cannot open '/.sta'.
Warning: /home/jcyr/openlane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
Warning: /home/jcyr/openlane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/synthesis/user_project_wrapper.synthesis.v, line 22 module user_proj_example not found. Creating black box for mprj.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load $cap_load [all_outputs]
tns 0.00
wns 0.00
[INFO]: Synthesis was successful
[INFO]: Creating a synthesis netlist with PG pins.
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
1. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/user_project_wrapper/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v
Parsing Verilog input from `/project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v' to AST representation.
Generating RTLIL representation for module `\user_proj_example'.
Warning: Replacing memory \status_r with list of registers. See /project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v:135
Warning: Replacing memory \solution_r with list of registers. See /project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v:133
Generating RTLIL representation for module `\sha3_256_miner_regs'.
Generating RTLIL representation for module `\sha3_256_miner_core_248'.
Warning: Replacing memory \ctl_r with list of registers. See /project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v:277, /project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v:276
Generating RTLIL representation for module `\sha3_256_miner_core_12'.
Warning: Replacing memory \ctl_r with list of registers. See /project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v:435, /project/openlane/user_project_wrapper/../../verilog/rtl/user_proj_example.v:434
Generating RTLIL representation for module `\sha3_256_miner_round'.
Generating RTLIL representation for module `\permutation'.
Successfully finished Verilog frontend.
3. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/user_project_wrapper/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.
4. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v
Parsing Verilog input from `/project/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v' to AST representation.
Generating RTLIL representation for module `\user_project_wrapper'.
Successfully finished Verilog frontend.
5. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/synthesis/hierarchy.dot'.
Dumping module user_project_wrapper to page 1.
6. Executing HIERARCHY pass (managing design hierarchy).
6.1. Analyzing design hierarchy..
Top module: \user_project_wrapper
6.2. Analyzing design hierarchy..
Top module: \user_project_wrapper
Removed 0 unused modules.
7. Printing statistics.
=== user_project_wrapper ===
Number of wires: 26
Number of wire bits: 644
Number of public wires: 26
Number of public wire bits: 644
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 1
user_proj_example 1
8. Executing SPLITNETS pass (splitting up multi-bit signals).
9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \user_project_wrapper..
10. Executing CHECK pass (checking for obvious problems).
checking module user_project_wrapper..
found and reported 0 problems.
11. Printing statistics.
=== user_project_wrapper ===
Number of wires: 26
Number of wire bits: 644
Number of public wires: 26
Number of public wire bits: 644
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 1
user_proj_example 1
Area for cell type \user_proj_example is unknown!
12. Executing Verilog backend.
Dumping module `\user_project_wrapper'.
Warnings: 4 unique messages, 4 total
End of script. Logfile hash: fd86f58f38, CPU: user 0.10s system 0.00s, MEM: 14.63 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 70% 8x read_verilog (0 sec), 23% 2x stat (0 sec), ...
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Error: cannot open '/.openroad'.
Warning: /home/jcyr/openlane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 439 library cells
Notice 0: Finished LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Warning: LEF master user_proj_example has no liberty cell.
Info: Added 1286 rows of 6323 sites.
[INFO]: Core area width: 2908.96
[INFO]: Core area height: 3498.24
[INFO]: Changing layout from 0 to /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/verilog2def_openroad.def
Notice 0: Reading LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 439 library cells
Notice 0: Finished LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
Notice 0:
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: user_project_wrapper
Notice 0: Created 636 pins.
Notice 0: Created 1 components and 638 component-terminals.
Notice 0: Created 636 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/verilog2def_openroad.def
Top-level design name: user_project_wrapper
Block boundaries: 0 0 2920000 3520000
Writing /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def
[INFO]: Changing layout from /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/verilog2def_openroad.def to /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def
[INFO]: Applying DEF template...
[INFO]: Manual Macro Placement...
Notice 0: Reading LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 439 library cells
Notice 0: Finished LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
Notice 0:
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def
Notice 0: Design: user_project_wrapper
Notice 0: Created 636 pins.
Notice 0: Created 1 components and 638 component-terminals.
Notice 0: Created 636 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def
Placing the following macros:
{'mprj': ['40000', '40000', 'N']}
Design name: user_project_wrapper
Placing mprj
Successfully placed 1 instances
[INFO]: Changing layout from /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def to /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def.macro_placement.def
[INFO]: Power planning the following nets
[INFO]: Power: vccd1 vccd2 vdda1 vdda2
[INFO]: Ground: vssd1 vssd2 vssa1 vssa2
[INFO]: Generating PDN...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Error: cannot open '/.openroad'.
Notice 0: Reading LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 439 library cells
Notice 0: Finished LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def.macro_placement.def
Notice 0: Design: user_project_wrapper
Notice 0: Created 636 pins.
Notice 0: Created 1 components and 638 component-terminals.
Notice 0: Created 636 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def.macro_placement.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016] config: /home/jcyr/openlane/pdks/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_project_wrapper
[INFO] [PDNG-0009] Reading technology data
[ERROR] [PDNG-0037] Cannot find pin vccd1 on instance mprj (user_proj_example)
[ERROR] [PDNG-0037] Cannot find pin vssd1 on instance mprj (user_proj_example)
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
Core Rings
Layer: met4 - width: 3.000 spacing: 1.700 core_offset: 14.000
Layer: met5 - width: 3.000 spacing: 1.700 core_offset: 14.000
Stdcell Rails
Layer: met1 - width: 0.480 pitch: 2.720 offset: 0.000
Straps
Layer: met4 - width: 3.000 pitch: 180.000 offset: 0.000
Layer: met5 - width: 3.000 pitch: 180.000 offset: 0.000
Connect: {met4 met5} {met1 met4}
Type: macro, macro_1
Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
Straps
Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[WARN] [PDNG-0041] No via added at (5.52 10.64 7.02 11.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 16.08 7.02 16.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 21.52 7.02 22.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 26.96 7.02 27.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 32.4 7.02 32.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 37.84 7.02 38.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 43.28 7.02 43.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 48.72 7.02 49.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 54.16 7.02 54.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 59.6 7.02 60.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 65.04 7.02 65.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 70.48 7.02 70.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 75.92 7.02 76.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 81.36 7.02 81.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 86.8 7.02 87.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 92.24 7.02 92.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 97.68 7.02 98.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 103.12 7.02 103.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 108.56 7.02 109.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 114.0 7.02 114.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 119.44 7.02 119.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 124.88 7.02 125.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 130.32 7.02 130.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 135.76 7.02 136.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 141.2 7.02 141.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 146.64 7.02 147.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 152.08 7.02 152.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 157.52 7.02 158.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 162.96 7.02 163.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 168.4 7.02 168.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 173.84 7.02 174.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 179.28 7.02 179.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 184.72 7.02 185.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 190.16 7.02 190.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 195.6 7.02 196.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 201.04 7.02 201.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 206.48 7.02 206.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 211.92 7.02 212.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 217.36 7.02 217.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 222.8 7.02 223.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 228.24 7.02 228.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 233.68 7.02 234.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 239.12 7.02 239.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 244.56 7.02 245.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 250.0 7.02 250.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 255.44 7.02 255.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 260.88 7.02 261.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 266.32 7.02 266.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 271.76 7.02 272.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 277.2 7.02 277.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 282.64 7.02 283.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 288.08 7.02 288.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 293.52 7.02 294.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 298.96 7.02 299.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 304.4 7.02 304.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 309.84 7.02 310.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 315.28 7.02 315.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 320.72 7.02 321.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 326.16 7.02 326.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 331.6 7.02 332.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 337.04 7.02 337.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 342.48 7.02 342.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 347.92 7.02 348.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 353.36 7.02 353.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 358.8 7.02 359.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 364.24 7.02 364.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 369.68 7.02 370.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 375.12 7.02 375.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 380.56 7.02 381.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 386.0 7.02 386.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 391.44 7.02 391.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 396.88 7.02 397.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 402.32 7.02 402.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 407.76 7.02 408.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 413.2 7.02 413.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 418.64 7.02 419.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 424.08 7.02 424.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 429.52 7.02 430.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 434.96 7.02 435.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 440.4 7.02 440.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 445.84 7.02 446.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 451.28 7.02 451.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 456.72 7.02 457.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 462.16 7.02 462.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 467.6 7.02 468.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 473.04 7.02 473.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 478.48 7.02 478.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 483.92 7.02 484.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 489.36 7.02 489.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 494.8 7.02 495.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 500.24 7.02 500.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 505.68 7.02 506.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 511.12 7.02 511.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 516.56 7.02 517.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 522.0 7.02 522.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 527.44 7.02 527.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 532.88 7.02 533.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 538.32 7.02 538.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 543.76 7.02 544.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 549.2 7.02 549.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 554.64 7.02 555.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 560.08 7.02 560.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 565.52 7.02 566.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 570.96 7.02 571.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 576.4 7.02 576.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 581.84 7.02 582.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 587.28 7.02 587.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 592.72 7.02 593.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 598.16 7.02 598.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 603.6 7.02 604.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 609.04 7.02 609.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 614.48 7.02 614.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 619.92 7.02 620.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 625.36 7.02 625.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 630.8 7.02 631.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 636.24 7.02 636.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 641.68 7.02 642.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 647.12 7.02 647.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 652.56 7.02 653.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 658.0 7.02 658.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 663.44 7.02 663.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 668.88 7.02 669.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 674.32 7.02 674.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 679.76 7.02 680.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 685.2 7.02 685.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 690.64 7.02 691.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 696.08 7.02 696.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 701.52 7.02 702.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 706.96 7.02 707.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 712.4 7.02 712.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 717.84 7.02 718.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 723.28 7.02 723.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 728.72 7.02 729.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 734.16 7.02 734.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 739.6 7.02 740.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 745.04 7.02 745.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 750.48 7.02 750.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 755.92 7.02 756.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 761.36 7.02 761.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 766.8 7.02 767.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 772.24 7.02 772.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 777.68 7.02 778.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 783.12 7.02 783.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 788.56 7.02 789.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 794.0 7.02 794.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 799.44 7.02 799.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 804.88 7.02 805.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 810.32 7.02 810.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 815.76 7.02 816.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 821.2 7.02 821.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 826.64 7.02 827.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 832.08 7.02 832.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 837.52 7.02 838.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 842.96 7.02 843.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 848.4 7.02 848.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 853.84 7.02 854.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 859.28 7.02 859.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 864.72 7.02 865.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 870.16 7.02 870.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 875.6 7.02 876.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 881.04 7.02 881.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 886.48 7.02 886.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 891.92 7.02 892.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 897.36 7.02 897.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 902.8 7.02 903.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 908.24 7.02 908.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 913.68 7.02 914.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 919.12 7.02 919.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 924.56 7.02 925.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 930.0 7.02 930.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 935.44 7.02 935.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 940.88 7.02 941.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 946.32 7.02 946.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 951.76 7.02 952.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 957.2 7.02 957.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 962.64 7.02 963.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 968.08 7.02 968.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 973.52 7.02 974.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 978.96 7.02 979.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 984.4 7.02 984.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 989.84 7.02 990.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 995.28 7.02 995.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1000.72 7.02 1001.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1006.16 7.02 1006.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1011.6 7.02 1012.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1017.04 7.02 1017.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1022.48 7.02 1022.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1027.92 7.02 1028.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1033.36 7.02 1033.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1038.8 7.02 1039.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1044.24 7.02 1044.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1049.68 7.02 1050.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1055.12 7.02 1055.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1060.56 7.02 1061.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1066.0 7.02 1066.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1071.44 7.02 1071.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1076.88 7.02 1077.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1082.32 7.02 1082.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1087.76 7.02 1088.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1093.2 7.02 1093.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1098.64 7.02 1099.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1104.08 7.02 1104.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1109.52 7.02 1110.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1114.96 7.02 1115.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1120.4 7.02 1120.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1125.84 7.02 1126.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1131.28 7.02 1131.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1136.72 7.02 1137.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1142.16 7.02 1142.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1147.6 7.02 1148.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1153.04 7.02 1153.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1158.48 7.02 1158.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1163.92 7.02 1164.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1169.36 7.02 1169.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1174.8 7.02 1175.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1180.24 7.02 1180.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1185.68 7.02 1186.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1191.12 7.02 1191.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1196.56 7.02 1197.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1202.0 7.02 1202.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1207.44 7.02 1207.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1212.88 7.02 1213.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1218.32 7.02 1218.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1223.76 7.02 1224.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1229.2 7.02 1229.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1234.64 7.02 1235.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1240.08 7.02 1240.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1245.52 7.02 1246.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1250.96 7.02 1251.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1256.4 7.02 1256.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1261.84 7.02 1262.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1267.28 7.02 1267.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1272.72 7.02 1273.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1278.16 7.02 1278.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1283.6 7.02 1284.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1289.04 7.02 1289.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1294.48 7.02 1294.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1299.92 7.02 1300.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1305.36 7.02 1305.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1310.8 7.02 1311.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1316.24 7.02 1316.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1321.68 7.02 1322.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1327.12 7.02 1327.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1332.56 7.02 1333.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1338.0 7.02 1338.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1343.44 7.02 1343.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1348.88 7.02 1349.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1354.32 7.02 1354.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1359.76 7.02 1360.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1365.2 7.02 1365.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1370.64 7.02 1371.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1376.08 7.02 1376.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1381.52 7.02 1382.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1386.96 7.02 1387.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1392.4 7.02 1392.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1397.84 7.02 1398.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1403.28 7.02 1403.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1408.72 7.02 1409.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1414.16 7.02 1414.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1419.6 7.02 1420.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1425.04 7.02 1425.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1430.48 7.02 1430.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1435.92 7.02 1436.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1441.36 7.02 1441.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1446.8 7.02 1447.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1452.24 7.02 1452.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1457.68 7.02 1458.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1463.12 7.02 1463.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1468.56 7.02 1469.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1474.0 7.02 1474.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1479.44 7.02 1479.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1484.88 7.02 1485.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1490.32 7.02 1490.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1495.76 7.02 1496.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1501.2 7.02 1501.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1506.64 7.02 1507.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1512.08 7.02 1512.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1517.52 7.02 1518.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1522.96 7.02 1523.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1528.4 7.02 1528.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1533.84 7.02 1534.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1539.28 7.02 1539.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1544.72 7.02 1545.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1550.16 7.02 1550.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1555.6 7.02 1556.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1561.04 7.02 1561.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1566.48 7.02 1566.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1571.92 7.02 1572.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1577.36 7.02 1577.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1582.8 7.02 1583.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1588.24 7.02 1588.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1593.68 7.02 1594.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1599.12 7.02 1599.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1604.56 7.02 1605.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1610.0 7.02 1610.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1615.44 7.02 1615.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1620.88 7.02 1621.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1626.32 7.02 1626.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1631.76 7.02 1632.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1637.2 7.02 1637.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1642.64 7.02 1643.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1648.08 7.02 1648.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1653.52 7.02 1654.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1658.96 7.02 1659.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1664.4 7.02 1664.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1669.84 7.02 1670.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1675.28 7.02 1675.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1680.72 7.02 1681.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1686.16 7.02 1686.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1691.6 7.02 1692.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1697.04 7.02 1697.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1702.48 7.02 1702.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1707.92 7.02 1708.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1713.36 7.02 1713.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1718.8 7.02 1719.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1724.24 7.02 1724.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1729.68 7.02 1730.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1735.12 7.02 1735.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1740.56 7.02 1741.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1746.0 7.02 1746.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1751.44 7.02 1751.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1756.88 7.02 1757.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1762.32 7.02 1762.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1767.76 7.02 1768.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1773.2 7.02 1773.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1778.64 7.02 1779.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1784.08 7.02 1784.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1789.52 7.02 1790.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1794.96 7.02 1795.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1800.4 7.02 1800.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1805.84 7.02 1806.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1811.28 7.02 1811.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1816.72 7.02 1817.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1822.16 7.02 1822.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1827.6 7.02 1828.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1833.04 7.02 1833.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1838.48 7.02 1838.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1843.92 7.02 1844.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1849.36 7.02 1849.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1854.8 7.02 1855.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1860.24 7.02 1860.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1865.68 7.02 1866.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1871.12 7.02 1871.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1876.56 7.02 1877.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1882.0 7.02 1882.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1887.44 7.02 1887.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1892.88 7.02 1893.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1898.32 7.02 1898.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1903.76 7.02 1904.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1909.2 7.02 1909.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1914.64 7.02 1915.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1920.08 7.02 1920.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1925.52 7.02 1926.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1930.96 7.02 1931.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1936.4 7.02 1936.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1941.84 7.02 1942.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1947.28 7.02 1947.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1952.72 7.02 1953.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1958.16 7.02 1958.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1963.6 7.02 1964.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1969.04 7.02 1969.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1974.48 7.02 1974.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1979.92 7.02 1980.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1985.36 7.02 1985.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1990.8 7.02 1991.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 1996.24 7.02 1996.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2001.68 7.02 2002.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2007.12 7.02 2007.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2012.56 7.02 2013.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2018.0 7.02 2018.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2023.44 7.02 2023.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2028.88 7.02 2029.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2034.32 7.02 2034.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2039.76 7.02 2040.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2045.2 7.02 2045.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2050.64 7.02 2051.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2056.08 7.02 2056.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2061.52 7.02 2062.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2066.96 7.02 2067.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2072.4 7.02 2072.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2077.84 7.02 2078.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2083.28 7.02 2083.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2088.72 7.02 2089.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2094.16 7.02 2094.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2099.6 7.02 2100.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2105.04 7.02 2105.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2110.48 7.02 2110.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2115.92 7.02 2116.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2121.36 7.02 2121.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2126.8 7.02 2127.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2132.24 7.02 2132.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2137.68 7.02 2138.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2143.12 7.02 2143.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2148.56 7.02 2149.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2154.0 7.02 2154.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2159.44 7.02 2159.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2164.88 7.02 2165.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2170.32 7.02 2170.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2175.76 7.02 2176.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2181.2 7.02 2181.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2186.64 7.02 2187.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2192.08 7.02 2192.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2197.52 7.02 2198.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2202.96 7.02 2203.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2208.4 7.02 2208.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2213.84 7.02 2214.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2219.28 7.02 2219.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2224.72 7.02 2225.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2230.16 7.02 2230.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2235.6 7.02 2236.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2241.04 7.02 2241.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2246.48 7.02 2246.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2251.92 7.02 2252.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2257.36 7.02 2257.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2262.8 7.02 2263.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2268.24 7.02 2268.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2273.68 7.02 2274.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2279.12 7.02 2279.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2284.56 7.02 2285.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2290.0 7.02 2290.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2295.44 7.02 2295.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2300.88 7.02 2301.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2306.32 7.02 2306.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2311.76 7.02 2312.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2317.2 7.02 2317.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2322.64 7.02 2323.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2328.08 7.02 2328.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2333.52 7.02 2334.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2338.96 7.02 2339.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2344.4 7.02 2344.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2349.84 7.02 2350.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2355.28 7.02 2355.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2360.72 7.02 2361.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2366.16 7.02 2366.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2371.6 7.02 2372.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2377.04 7.02 2377.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2382.48 7.02 2382.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2387.92 7.02 2388.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2393.36 7.02 2393.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2398.8 7.02 2399.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2404.24 7.02 2404.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2409.68 7.02 2410.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2415.12 7.02 2415.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2420.56 7.02 2421.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2426.0 7.02 2426.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2431.44 7.02 2431.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2436.88 7.02 2437.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2442.32 7.02 2442.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2447.76 7.02 2448.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2453.2 7.02 2453.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2458.64 7.02 2459.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2464.08 7.02 2464.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2469.52 7.02 2470.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2474.96 7.02 2475.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2480.4 7.02 2480.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2485.84 7.02 2486.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2491.28 7.02 2491.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2496.72 7.02 2497.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2502.16 7.02 2502.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2507.6 7.02 2508.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2513.04 7.02 2513.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2518.48 7.02 2518.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2523.92 7.02 2524.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2529.36 7.02 2529.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2534.8 7.02 2535.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2540.24 7.02 2540.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2545.68 7.02 2546.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2551.12 7.02 2551.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2556.56 7.02 2557.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2562.0 7.02 2562.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2567.44 7.02 2567.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2572.88 7.02 2573.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2578.32 7.02 2578.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2583.76 7.02 2584.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2589.2 7.02 2589.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2594.64 7.02 2595.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2600.08 7.02 2600.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2605.52 7.02 2606.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2610.96 7.02 2611.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2616.4 7.02 2616.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2621.84 7.02 2622.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2627.28 7.02 2627.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2632.72 7.02 2633.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2638.16 7.02 2638.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2643.6 7.02 2644.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2649.04 7.02 2649.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2654.48 7.02 2654.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2659.92 7.02 2660.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2665.36 7.02 2665.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2670.8 7.02 2671.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2676.24 7.02 2676.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2681.68 7.02 2682.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2687.12 7.02 2687.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2692.56 7.02 2693.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2698.0 7.02 2698.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2703.44 7.02 2703.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2708.88 7.02 2709.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2714.32 7.02 2714.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2719.76 7.02 2720.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2725.2 7.02 2725.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2730.64 7.02 2731.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2736.08 7.02 2736.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2741.52 7.02 2742.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2746.96 7.02 2747.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2752.4 7.02 2752.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2757.84 7.02 2758.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2763.28 7.02 2763.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2768.72 7.02 2769.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2774.16 7.02 2774.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2779.6 7.02 2780.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2785.04 7.02 2785.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2790.48 7.02 2790.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2795.92 7.02 2796.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2801.36 7.02 2801.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2806.8 7.02 2807.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2812.24 7.02 2812.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2817.68 7.02 2818.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2823.12 7.02 2823.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2828.56 7.02 2829.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2834.0 7.02 2834.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2839.44 7.02 2839.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2844.88 7.02 2845.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2850.32 7.02 2850.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2855.76 7.02 2856.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2861.2 7.02 2861.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2866.64 7.02 2867.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2872.08 7.02 2872.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2877.52 7.02 2878.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2882.96 7.02 2883.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2888.4 7.02 2888.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2893.84 7.02 2894.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2899.28 7.02 2899.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2904.72 7.02 2905.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2910.16 7.02 2910.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2915.6 7.02 2916.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2921.04 7.02 2921.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2926.48 7.02 2926.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2931.92 7.02 2932.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2937.36 7.02 2937.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2942.8 7.02 2943.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2948.24 7.02 2948.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2953.68 7.02 2954.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2959.12 7.02 2959.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2964.56 7.02 2965.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2970.0 7.02 2970.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2975.44 7.02 2975.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2980.88 7.02 2981.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2986.32 7.02 2986.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2991.76 7.02 2992.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 2997.2 7.02 2997.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3002.64 7.02 3003.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3008.08 7.02 3008.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3013.52 7.02 3014.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3018.96 7.02 3019.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3024.4 7.02 3024.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3029.84 7.02 3030.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3035.28 7.02 3035.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3040.72 7.02 3041.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3046.16 7.02 3046.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3051.6 7.02 3052.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3057.04 7.02 3057.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3062.48 7.02 3062.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3067.92 7.02 3068.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3073.36 7.02 3073.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3078.8 7.02 3079.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3084.24 7.02 3084.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3089.68 7.02 3090.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3095.12 7.02 3095.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3100.56 7.02 3101.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3106.0 7.02 3106.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3111.44 7.02 3111.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3116.88 7.02 3117.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3122.32 7.02 3122.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3127.76 7.02 3128.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3133.2 7.02 3133.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3138.64 7.02 3139.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3144.08 7.02 3144.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3149.52 7.02 3150.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3154.96 7.02 3155.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3160.4 7.02 3160.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3165.84 7.02 3166.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3171.28 7.02 3171.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3176.72 7.02 3177.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3182.16 7.02 3182.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3187.6 7.02 3188.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3193.04 7.02 3193.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3198.48 7.02 3198.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3203.92 7.02 3204.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3209.36 7.02 3209.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3214.8 7.02 3215.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3220.24 7.02 3220.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3225.68 7.02 3226.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3231.12 7.02 3231.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3236.56 7.02 3237.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3242.0 7.02 3242.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3247.44 7.02 3247.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3252.88 7.02 3253.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3258.32 7.02 3258.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3263.76 7.02 3264.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3269.2 7.02 3269.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3274.64 7.02 3275.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3280.08 7.02 3280.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3285.52 7.02 3286.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3290.96 7.02 3291.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3296.4 7.02 3296.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3301.84 7.02 3302.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3307.28 7.02 3307.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3312.72 7.02 3313.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3318.16 7.02 3318.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3323.6 7.02 3324.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3329.04 7.02 3329.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3334.48 7.02 3334.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3339.92 7.02 3340.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3345.36 7.02 3345.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3350.8 7.02 3351.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3356.24 7.02 3356.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3361.68 7.02 3362.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3367.12 7.02 3367.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3372.56 7.02 3373.04) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3378.0 7.02 3378.48) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3383.44 7.02 3383.92) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3388.88 7.02 3389.36) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3394.32 7.02 3394.8) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3399.76 7.02 3400.24) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3405.2 7.02 3405.68) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3410.64 7.02 3411.12) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3416.08 7.02 3416.56) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3421.52 7.02 3422.0) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3426.96 7.02 3427.44) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3432.4 7.02 3432.88) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3437.84 7.02 3438.32) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3443.28 7.02 3443.76) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3448.72 7.02 3449.2) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3454.16 7.02 3454.64) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3459.6 7.02 3460.08) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3465.04 7.02 3465.52) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3470.48 7.02 3470.96) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3475.92 7.02 3476.4) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3481.36 7.02 3481.84) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3486.8 7.02 3487.28) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3492.24 7.02 3492.72) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3497.68 7.02 3498.16) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3503.12 7.02 3503.6) because the full width of met4 (3.0) is not covered by the overlap
[WARN] [PDNG-0041] No via added at (5.52 3508.56 7.02 3509.04) because the full width of met4 (3.0) is not covered by the overlap
[INFO] [PDNG-0010] Inserting macro grid for 1 macros
[INFO] [PDNG-0034] - grid for instance mprj
[WARN] [PDNG-0002] No shapes on layer met4_PIN_ver for POWER
[WARN] [PDNG-0002] No shapes on layer met4_PIN_ver for GROUND
[INFO] [PDNG-0015] Writing to database
[INFO]: Changing layout from /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def.macro_placement.def to /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def
[INFO]: Generating PDN...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Error: cannot open '/.openroad'.
Notice 0: Reading LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 439 library cells
Notice 0: Finished LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def
Notice 0: Design: user_project_wrapper
Notice 0: Created 638 pins.
Notice 0: Created 1 components and 638 component-terminals.
Notice 0: Created 2 special nets and 0 connections.
Notice 0: Created 636 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016] config: /home/jcyr/openlane/pdks/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_project_wrapper
[INFO] [PDNG-0009] Reading technology data
[ERROR] [PDNG-0037] Cannot find pin vccd2 on instance mprj (user_proj_example)
[ERROR] [PDNG-0037] Cannot find pin vssd2 on instance mprj (user_proj_example)
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
Core Rings
Layer: met4 - width: 3.000 spacing: 1.700 core_offset: 23.400
Layer: met5 - width: 3.000 spacing: 1.700 core_offset: 23.400
Stdcell Rails
Straps
Layer: met4 - width: 3.000 pitch: 180.000 offset: 18.000
Layer: met5 - width: 3.000 pitch: 180.000 offset: 18.000
Connect: {met4 met5}
Type: macro, macro_1
Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
Straps
Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[WARN] [PDNG-0040] No via added at (202.02 27.38 205.02 30.0) because the full height of met5 (3.0) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (382.02 27.38 385.02 30.0) because the full height of met5 (3.0) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (562.02 27.38 565.02 30.0) because the full height of met5 (3.0) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (742.02 27.38 745.02 30.0) because the full height of met5 (3.0) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (922.02 27.38 925.02 30.0) because the full height of met5 (3.0) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (1102.02 27.38 1105.02 30.0) because the full height of met5 (3.0) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (1282.02 27.38 1285.02 30.0) because the full height of met5 (3.0) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (1462.02 27.38 1465.02 30.0) because the full height of met5 (3.0) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (1642.02 27.38 1645.02 30.0) because the full height of met5 (3.0) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (1822.02 27.38 1825.02 30.0) because the full height of met5 (3.0) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (2002.02 27.38 2005.02 30.0) because the full height of met5 (3.0) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (2182.02 27.38 2185.02 30.0) because the full height of met5 (3.0) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (2362.02 27.38 2365.02 30.0) because the full height of met5 (3.0) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (2542.02 27.38 2545.02 30.0) because the full height of met5 (3.0) is not covered by the overlap
[WARN] [PDNG-0040] No via added at (2722.02 27.38 2725.02 30.0) because the full height of met5 (3.0) is not covered by the overlap
[INFO] [PDNG-0010] Inserting macro grid for 1 macros
[INFO] [PDNG-0034] - grid for instance mprj
[WARN] [PDNG-0002] No shapes on layer met4_PIN_ver for POWER
[WARN] [PDNG-0002] No shapes on layer met4_PIN_ver for GROUND
[INFO] [PDNG-0015] Writing to database
[INFO]: Changing layout from /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def to /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def
[INFO]: Generating PDN...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Error: cannot open '/.openroad'.
Notice 0: Reading LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 439 library cells
Notice 0: Finished LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def
Notice 0: Design: user_project_wrapper
Notice 0: Created 640 pins.
Notice 0: Created 1 components and 638 component-terminals.
Notice 0: Created 4 special nets and 0 connections.
Notice 0: Created 636 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016] config: /home/jcyr/openlane/pdks/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_project_wrapper
[INFO] [PDNG-0009] Reading technology data
[ERROR] [PDNG-0037] Cannot find pin vdda1 on instance mprj (user_proj_example)
[ERROR] [PDNG-0037] Cannot find pin vssa1 on instance mprj (user_proj_example)
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
Core Rings
Layer: met4 - width: 3.000 spacing: 1.700 core_offset: 32.800
Layer: met5 - width: 3.000 spacing: 1.700 core_offset: 32.800
Stdcell Rails
Straps
Layer: met4 - width: 3.000 pitch: 180.000 offset: 36.000
Layer: met5 - width: 3.000 pitch: 180.000 offset: 36.000
Connect: {met4 met5}
Type: macro, macro_1
Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
Straps
Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0010] Inserting macro grid for 1 macros
[INFO] [PDNG-0034] - grid for instance mprj
[WARN] [PDNG-0002] No shapes on layer met4_PIN_ver for POWER
[WARN] [PDNG-0002] No shapes on layer met4_PIN_ver for GROUND
[INFO] [PDNG-0015] Writing to database
[INFO]: Changing layout from /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def to /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def
[INFO]: Generating PDN...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Error: cannot open '/.openroad'.
Notice 0: Reading LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 439 library cells
Notice 0: Finished LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def
Notice 0: Design: user_project_wrapper
Notice 0: Created 642 pins.
Notice 0: Created 1 components and 638 component-terminals.
Notice 0: Created 6 special nets and 0 connections.
Notice 0: Created 636 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016] config: /home/jcyr/openlane/pdks/sky130A/libs.tech/openlane/common_pdn.tcl
[INFO] [PDNG-0008] Design Name is user_project_wrapper
[INFO] [PDNG-0009] Reading technology data
[ERROR] [PDNG-0037] Cannot find pin vdda2 on instance mprj (user_proj_example)
[ERROR] [PDNG-0037] Cannot find pin vssa2 on instance mprj (user_proj_example)
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
Core Rings
Layer: met4 - width: 3.000 spacing: 1.700 core_offset: 42.200
Layer: met5 - width: 3.000 spacing: 1.700 core_offset: 42.200
Stdcell Rails
Straps
Layer: met4 - width: 3.000 pitch: 180.000 offset: 54.000
Layer: met5 - width: 3.000 pitch: 180.000 offset: 54.000
Connect: {met4 met5}
Type: macro, macro_1
Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
Straps
Connect: {met4_PIN_ver met5}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0010] Inserting macro grid for 1 macros
[INFO] [PDNG-0034] - grid for instance mprj
[WARN] [PDNG-0002] No shapes on layer met4_PIN_ver for POWER
[WARN] [PDNG-0002] No shapes on layer met4_PIN_ver for GROUND
[INFO] [PDNG-0015] Writing to database
[INFO]: Changing layout from /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def to /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def
[INFO]: Running Placement...
[WARNING]: Performing Random Global Placement...
Notice 0: Reading LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 439 library cells
Notice 0: Finished LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def
Notice 0: Design: user_project_wrapper
Notice 0: Created 644 pins.
Notice 0: Created 1 components and 638 component-terminals.
Notice 0: Created 8 special nets and 0 connections.
Notice 0: Created 636 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def
Design name: user_project_wrapper
Core Area Boundaries: 5520 10880 2914100 3508800
Number of instances 1
Placed 0 instances
[INFO]: Changing layout from /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/pdn.def to /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/placement/replace.def
[INFO]: Running Detailed Placement...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Error: cannot open '/.openroad'.
Notice 0: Reading LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 439 library cells
Notice 0: Finished LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/placement/replace.def
Notice 0: Design: user_project_wrapper
Notice 0: Created 644 pins.
Notice 0: Created 1 components and 638 component-terminals.
Notice 0: Created 8 special nets and 0 connections.
Notice 0: Created 636 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/placement/replace.def
Design Stats
--------------------------------
total instances 1
multi row instances 0
fixed instances 1
nets 644
design area 10173980.2 u^2
fixed area 2844.4 u^2
movable area 0.0 u^2
utilization 0 %
utilization padded 0 %
rows 1286
row height 2.7 u
Placement Analysis
--------------------------------
total displacement 0.0 u
average displacement 0.0 u
max displacement 0.0 u
original HPWL 414567.9 u
legalized HPWL 414567.9 u
delta HPWL 0 %
[INFO]: Changing layout from /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/placement/replace.def to /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/placement/user_project_wrapper.placement.def
[INFO]: Changing layout from /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/placement/user_project_wrapper.placement.def to /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/placement/user_project_wrapper.placement.def
[INFO]: Routing...
[INFO]: Running Global Routing...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Error: cannot open '/.openroad'.
Warning: /home/jcyr/openlane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found.
Notice 0: Reading LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 439 library cells
Notice 0: Finished LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/placement/user_project_wrapper.placement.def
Notice 0: Design: user_project_wrapper
Notice 0: Created 644 pins.
Notice 0: Created 1 components and 638 component-terminals.
Notice 0: Created 8 special nets and 0 connections.
Notice 0: Created 636 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/placement/user_project_wrapper.placement.def
[PARAMS] Min routing layer: 2
[PARAMS] Max routing layer: 5
[PARAMS] Global adjustment: 0
[PARAMS] Unidirectional routing: 1
[PARAMS] Grid origin: (-1, -1)
[INFO] #DB Obstructions: 0
[INFO] #DB Obstacles: 652
[INFO] #DB Macros: 1
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vccd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vssd1 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vccd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vssd2 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vdda1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vssa1 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vdda2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[WARNING] Net vssa2 has wires outside die area
[INFO] Found 0 clock nets
[WARNING] Pin analog_io[0] is outside die area
[WARNING] Pin analog_io[10] is outside die area
[WARNING] Pin analog_io[11] is outside die area
[WARNING] Pin analog_io[12] is outside die area
[WARNING] Pin analog_io[13] is outside die area
[WARNING] Pin analog_io[14] is outside die area
[WARNING] Pin analog_io[15] is outside die area
[WARNING] Pin analog_io[16] is outside die area
[WARNING] Pin analog_io[17] is outside die area
[WARNING] Pin analog_io[18] is outside die area
[WARNING] Pin analog_io[19] is outside die area
[WARNING] Pin analog_io[1] is outside die area
[WARNING] Pin analog_io[20] is outside die area
[WARNING] Pin analog_io[21] is outside die area
[WARNING] Pin analog_io[22] is outside die area
[WARNING] Pin analog_io[23] is outside die area
[WARNING] Pin analog_io[24] is outside die area
[WARNING] Pin analog_io[25] is outside die area
[WARNING] Pin analog_io[26] is outside die area
[WARNING] Pin analog_io[27] is outside die area
[WARNING] Pin analog_io[28] is outside die area
[WARNING] Pin analog_io[29] is outside die area
[WARNING] Pin analog_io[2] is outside die area
[WARNING] Pin analog_io[30] is outside die area
[WARNING] Pin analog_io[3] is outside die area
[WARNING] Pin analog_io[4] is outside die area
[WARNING] Pin analog_io[5] is outside die area
[WARNING] Pin analog_io[6] is outside die area
[WARNING] Pin analog_io[7] is outside die area
[WARNING] Pin analog_io[8] is outside die area
[WARNING] Pin analog_io[9] is outside die area
[WARNING] Pin io_in[0] is outside die area
[WARNING] Pin io_in[10] is outside die area
[WARNING] Pin io_in[11] is outside die area
[WARNING] Pin io_in[12] is outside die area
[WARNING] Pin io_in[13] is outside die area
[WARNING] Pin io_in[14] is outside die area
[WARNING] Pin io_in[15] is outside die area
[WARNING] Pin io_in[16] is outside die area
[WARNING] Pin io_in[17] is outside die area
[WARNING] Pin io_in[18] is outside die area
[WARNING] Pin io_in[19] is outside die area
[WARNING] Pin io_in[1] is outside die area
[WARNING] Pin io_in[20] is outside die area
[WARNING] Pin io_in[21] is outside die area
[WARNING] Pin io_in[22] is outside die area
[WARNING] Pin io_in[23] is outside die area
[WARNING] Pin io_in[24] is outside die area
[WARNING] Pin io_in[25] is outside die area
[WARNING] Pin io_in[26] is outside die area
[WARNING] Pin io_in[27] is outside die area
[WARNING] Pin io_in[28] is outside die area
[WARNING] Pin io_in[29] is outside die area
[WARNING] Pin io_in[2] is outside die area
[WARNING] Pin io_in[30] is outside die area
[WARNING] Pin io_in[31] is outside die area
[WARNING] Pin io_in[32] is outside die area
[WARNING] Pin io_in[33] is outside die area
[WARNING] Pin io_in[34] is outside die area
[WARNING] Pin io_in[35] is outside die area
[WARNING] Pin io_in[36] is outside die area
[WARNING] Pin io_in[37] is outside die area
[WARNING] Pin io_in[3] is outside die area
[WARNING] Pin io_in[4] is outside die area
[WARNING] Pin io_in[5] is outside die area
[WARNING] Pin io_in[6] is outside die area
[WARNING] Pin io_in[7] is outside die area
[WARNING] Pin io_in[8] is outside die area
[WARNING] Pin io_in[9] is outside die area
[WARNING] Pin io_oeb[0] is outside die area
[WARNING] Pin io_oeb[10] is outside die area
[WARNING] Pin io_oeb[11] is outside die area
[WARNING] Pin io_oeb[12] is outside die area
[WARNING] Pin io_oeb[13] is outside die area
[WARNING] Pin io_oeb[14] is outside die area
[WARNING] Pin io_oeb[15] is outside die area
[WARNING] Pin io_oeb[16] is outside die area
[WARNING] Pin io_oeb[17] is outside die area
[WARNING] Pin io_oeb[18] is outside die area
[WARNING] Pin io_oeb[19] is outside die area
[WARNING] Pin io_oeb[1] is outside die area
[WARNING] Pin io_oeb[20] is outside die area
[WARNING] Pin io_oeb[21] is outside die area
[WARNING] Pin io_oeb[22] is outside die area
[WARNING] Pin io_oeb[23] is outside die area
[WARNING] Pin io_oeb[24] is outside die area
[WARNING] Pin io_oeb[25] is outside die area
[WARNING] Pin io_oeb[26] is outside die area
[WARNING] Pin io_oeb[27] is outside die area
[WARNING] Pin io_oeb[28] is outside die area
[WARNING] Pin io_oeb[29] is outside die area
[WARNING] Pin io_oeb[2] is outside die area
[WARNING] Pin io_oeb[30] is outside die area
[WARNING] Pin io_oeb[31] is outside die area
[WARNING] Pin io_oeb[32] is outside die area
[WARNING] Pin io_oeb[33] is outside die area
[WARNING] Pin io_oeb[34] is outside die area
[WARNING] Pin io_oeb[35] is outside die area
[WARNING] Pin io_oeb[36] is outside die area
[WARNING] Pin io_oeb[37] is outside die area
[WARNING] Pin io_oeb[3] is outside die area
[WARNING] Pin io_oeb[4] is outside die area
[WARNING] Pin io_oeb[5] is outside die area
[WARNING] Pin io_oeb[6] is outside die area
[WARNING] Pin io_oeb[7] is outside die area
[WARNING] Pin io_oeb[8] is outside die area
[WARNING] Pin io_oeb[9] is outside die area
[WARNING] Pin io_out[0] is outside die area
[WARNING] Pin io_out[10] is outside die area
[WARNING] Pin io_out[11] is outside die area
[WARNING] Pin io_out[12] is outside die area
[WARNING] Pin io_out[13] is outside die area
[WARNING] Pin io_out[14] is outside die area
[WARNING] Pin io_out[15] is outside die area
[WARNING] Pin io_out[16] is outside die area
[WARNING] Pin io_out[17] is outside die area
[WARNING] Pin io_out[18] is outside die area
[WARNING] Pin io_out[19] is outside die area
[WARNING] Pin io_out[1] is outside die area
[WARNING] Pin io_out[20] is outside die area
[WARNING] Pin io_out[21] is outside die area
[WARNING] Pin io_out[22] is outside die area
[WARNING] Pin io_out[23] is outside die area
[WARNING] Pin io_out[24] is outside die area
[WARNING] Pin io_out[25] is outside die area
[WARNING] Pin io_out[26] is outside die area
[WARNING] Pin io_out[27] is outside die area
[WARNING] Pin io_out[28] is outside die area
[WARNING] Pin io_out[29] is outside die area
[WARNING] Pin io_out[2] is outside die area
[WARNING] Pin io_out[30] is outside die area
[WARNING] Pin io_out[31] is outside die area
[WARNING] Pin io_out[32] is outside die area
[WARNING] Pin io_out[33] is outside die area
[WARNING] Pin io_out[34] is outside die area
[WARNING] Pin io_out[35] is outside die area
[WARNING] Pin io_out[36] is outside die area
[WARNING] Pin io_out[37] is outside die area
[WARNING] Pin io_out[3] is outside die area
[WARNING] Pin io_out[4] is outside die area
[WARNING] Pin io_out[5] is outside die area
[WARNING] Pin io_out[6] is outside die area
[WARNING] Pin io_out[7] is outside die area
[WARNING] Pin io_out[8] is outside die area
[WARNING] Pin io_out[9] is outside die area
[WARNING] Pin la_data_in[0] is outside die area
[WARNING] Pin la_data_in[100] is outside die area
[WARNING] Pin la_data_in[101] is outside die area
[WARNING] Pin la_data_in[102] is outside die area
[WARNING] Pin la_data_in[103] is outside die area
[WARNING] Pin la_data_in[104] is outside die area
[WARNING] Pin la_data_in[105] is outside die area
[WARNING] Pin la_data_in[106] is outside die area
[WARNING] Pin la_data_in[107] is outside die area
[WARNING] Pin la_data_in[108] is outside die area
[WARNING] Pin la_data_in[109] is outside die area
[WARNING] Pin la_data_in[10] is outside die area
[WARNING] Pin la_data_in[110] is outside die area
[WARNING] Pin la_data_in[111] is outside die area
[WARNING] Pin la_data_in[112] is outside die area
[WARNING] Pin la_data_in[113] is outside die area
[WARNING] Pin la_data_in[114] is outside die area
[WARNING] Pin la_data_in[115] is outside die area
[WARNING] Pin la_data_in[116] is outside die area
[WARNING] Pin la_data_in[117] is outside die area
[WARNING] Pin la_data_in[118] is outside die area
[WARNING] Pin la_data_in[119] is outside die area
[WARNING] Pin la_data_in[11] is outside die area
[WARNING] Pin la_data_in[120] is outside die area
[WARNING] Pin la_data_in[121] is outside die area
[WARNING] Pin la_data_in[122] is outside die area
[WARNING] Pin la_data_in[123] is outside die area
[WARNING] Pin la_data_in[124] is outside die area
[WARNING] Pin la_data_in[125] is outside die area
[WARNING] Pin la_data_in[126] is outside die area
[WARNING] Pin la_data_in[127] is outside die area
[WARNING] Pin la_data_in[12] is outside die area
[WARNING] Pin la_data_in[13] is outside die area
[WARNING] Pin la_data_in[14] is outside die area
[WARNING] Pin la_data_in[15] is outside die area
[WARNING] Pin la_data_in[16] is outside die area
[WARNING] Pin la_data_in[17] is outside die area
[WARNING] Pin la_data_in[18] is outside die area
[WARNING] Pin la_data_in[19] is outside die area
[WARNING] Pin la_data_in[1] is outside die area
[WARNING] Pin la_data_in[20] is outside die area
[WARNING] Pin la_data_in[21] is outside die area
[WARNING] Pin la_data_in[22] is outside die area
[WARNING] Pin la_data_in[23] is outside die area
[WARNING] Pin la_data_in[24] is outside die area
[WARNING] Pin la_data_in[25] is outside die area
[WARNING] Pin la_data_in[26] is outside die area
[WARNING] Pin la_data_in[27] is outside die area
[WARNING] Pin la_data_in[28] is outside die area
[WARNING] Pin la_data_in[29] is outside die area
[WARNING] Pin la_data_in[2] is outside die area
[WARNING] Pin la_data_in[30] is outside die area
[WARNING] Pin la_data_in[31] is outside die area
[WARNING] Pin la_data_in[32] is outside die area
[WARNING] Pin la_data_in[33] is outside die area
[WARNING] Pin la_data_in[34] is outside die area
[WARNING] Pin la_data_in[35] is outside die area
[WARNING] Pin la_data_in[36] is outside die area
[WARNING] Pin la_data_in[37] is outside die area
[WARNING] Pin la_data_in[38] is outside die area
[WARNING] Pin la_data_in[39] is outside die area
[WARNING] Pin la_data_in[3] is outside die area
[WARNING] Pin la_data_in[40] is outside die area
[WARNING] Pin la_data_in[41] is outside die area
[WARNING] Pin la_data_in[42] is outside die area
[WARNING] Pin la_data_in[43] is outside die area
[WARNING] Pin la_data_in[44] is outside die area
[WARNING] Pin la_data_in[45] is outside die area
[WARNING] Pin la_data_in[46] is outside die area
[WARNING] Pin la_data_in[47] is outside die area
[WARNING] Pin la_data_in[48] is outside die area
[WARNING] Pin la_data_in[49] is outside die area
[WARNING] Pin la_data_in[4] is outside die area
[WARNING] Pin la_data_in[50] is outside die area
[WARNING] Pin la_data_in[51] is outside die area
[WARNING] Pin la_data_in[52] is outside die area
[WARNING] Pin la_data_in[53] is outside die area
[WARNING] Pin la_data_in[54] is outside die area
[WARNING] Pin la_data_in[55] is outside die area
[WARNING] Pin la_data_in[56] is outside die area
[WARNING] Pin la_data_in[57] is outside die area
[WARNING] Pin la_data_in[58] is outside die area
[WARNING] Pin la_data_in[59] is outside die area
[WARNING] Pin la_data_in[5] is outside die area
[WARNING] Pin la_data_in[60] is outside die area
[WARNING] Pin la_data_in[61] is outside die area
[WARNING] Pin la_data_in[62] is outside die area
[WARNING] Pin la_data_in[63] is outside die area
[WARNING] Pin la_data_in[64] is outside die area
[WARNING] Pin la_data_in[65] is outside die area
[WARNING] Pin la_data_in[66] is outside die area
[WARNING] Pin la_data_in[67] is outside die area
[WARNING] Pin la_data_in[68] is outside die area
[WARNING] Pin la_data_in[69] is outside die area
[WARNING] Pin la_data_in[6] is outside die area
[WARNING] Pin la_data_in[70] is outside die area
[WARNING] Pin la_data_in[71] is outside die area
[WARNING] Pin la_data_in[72] is outside die area
[WARNING] Pin la_data_in[73] is outside die area
[WARNING] Pin la_data_in[74] is outside die area
[WARNING] Pin la_data_in[75] is outside die area
[WARNING] Pin la_data_in[76] is outside die area
[WARNING] Pin la_data_in[77] is outside die area
[WARNING] Pin la_data_in[78] is outside die area
[WARNING] Pin la_data_in[79] is outside die area
[WARNING] Pin la_data_in[7] is outside die area
[WARNING] Pin la_data_in[80] is outside die area
[WARNING] Pin la_data_in[81] is outside die area
[WARNING] Pin la_data_in[82] is outside die area
[WARNING] Pin la_data_in[83] is outside die area
[WARNING] Pin la_data_in[84] is outside die area
[WARNING] Pin la_data_in[85] is outside die area
[WARNING] Pin la_data_in[86] is outside die area
[WARNING] Pin la_data_in[87] is outside die area
[WARNING] Pin la_data_in[88] is outside die area
[WARNING] Pin la_data_in[89] is outside die area
[WARNING] Pin la_data_in[8] is outside die area
[WARNING] Pin la_data_in[90] is outside die area
[WARNING] Pin la_data_in[91] is outside die area
[WARNING] Pin la_data_in[92] is outside die area
[WARNING] Pin la_data_in[93] is outside die area
[WARNING] Pin la_data_in[94] is outside die area
[WARNING] Pin la_data_in[95] is outside die area
[WARNING] Pin la_data_in[96] is outside die area
[WARNING] Pin la_data_in[97] is outside die area
[WARNING] Pin la_data_in[98] is outside die area
[WARNING] Pin la_data_in[99] is outside die area
[WARNING] Pin la_data_in[9] is outside die area
[WARNING] Pin la_data_out[0] is outside die area
[WARNING] Pin la_data_out[100] is outside die area
[WARNING] Pin la_data_out[101] is outside die area
[WARNING] Pin la_data_out[102] is outside die area
[WARNING] Pin la_data_out[103] is outside die area
[WARNING] Pin la_data_out[104] is outside die area
[WARNING] Pin la_data_out[105] is outside die area
[WARNING] Pin la_data_out[106] is outside die area
[WARNING] Pin la_data_out[107] is outside die area
[WARNING] Pin la_data_out[108] is outside die area
[WARNING] Pin la_data_out[109] is outside die area
[WARNING] Pin la_data_out[10] is outside die area
[WARNING] Pin la_data_out[110] is outside die area
[WARNING] Pin la_data_out[111] is outside die area
[WARNING] Pin la_data_out[112] is outside die area
[WARNING] Pin la_data_out[113] is outside die area
[WARNING] Pin la_data_out[114] is outside die area
[WARNING] Pin la_data_out[115] is outside die area
[WARNING] Pin la_data_out[116] is outside die area
[WARNING] Pin la_data_out[117] is outside die area
[WARNING] Pin la_data_out[118] is outside die area
[WARNING] Pin la_data_out[119] is outside die area
[WARNING] Pin la_data_out[11] is outside die area
[WARNING] Pin la_data_out[120] is outside die area
[WARNING] Pin la_data_out[121] is outside die area
[WARNING] Pin la_data_out[122] is outside die area
[WARNING] Pin la_data_out[123] is outside die area
[WARNING] Pin la_data_out[124] is outside die area
[WARNING] Pin la_data_out[125] is outside die area
[WARNING] Pin la_data_out[126] is outside die area
[WARNING] Pin la_data_out[127] is outside die area
[WARNING] Pin la_data_out[12] is outside die area
[WARNING] Pin la_data_out[13] is outside die area
[WARNING] Pin la_data_out[14] is outside die area
[WARNING] Pin la_data_out[15] is outside die area
[WARNING] Pin la_data_out[16] is outside die area
[WARNING] Pin la_data_out[17] is outside die area
[WARNING] Pin la_data_out[18] is outside die area
[WARNING] Pin la_data_out[19] is outside die area
[WARNING] Pin la_data_out[1] is outside die area
[WARNING] Pin la_data_out[20] is outside die area
[WARNING] Pin la_data_out[21] is outside die area
[WARNING] Pin la_data_out[22] is outside die area
[WARNING] Pin la_data_out[23] is outside die area
[WARNING] Pin la_data_out[24] is outside die area
[WARNING] Pin la_data_out[25] is outside die area
[WARNING] Pin la_data_out[26] is outside die area
[WARNING] Pin la_data_out[27] is outside die area
[WARNING] Pin la_data_out[28] is outside die area
[WARNING] Pin la_data_out[29] is outside die area
[WARNING] Pin la_data_out[2] is outside die area
[WARNING] Pin la_data_out[30] is outside die area
[WARNING] Pin la_data_out[31] is outside die area
[WARNING] Pin la_data_out[32] is outside die area
[WARNING] Pin la_data_out[33] is outside die area
[WARNING] Pin la_data_out[34] is outside die area
[WARNING] Pin la_data_out[35] is outside die area
[WARNING] Pin la_data_out[36] is outside die area
[WARNING] Pin la_data_out[37] is outside die area
[WARNING] Pin la_data_out[38] is outside die area
[WARNING] Pin la_data_out[39] is outside die area
[WARNING] Pin la_data_out[3] is outside die area
[WARNING] Pin la_data_out[40] is outside die area
[WARNING] Pin la_data_out[41] is outside die area
[WARNING] Pin la_data_out[42] is outside die area
[WARNING] Pin la_data_out[43] is outside die area
[WARNING] Pin la_data_out[44] is outside die area
[WARNING] Pin la_data_out[45] is outside die area
[WARNING] Pin la_data_out[46] is outside die area
[WARNING] Pin la_data_out[47] is outside die area
[WARNING] Pin la_data_out[48] is outside die area
[WARNING] Pin la_data_out[49] is outside die area
[WARNING] Pin la_data_out[4] is outside die area
[WARNING] Pin la_data_out[50] is outside die area
[WARNING] Pin la_data_out[51] is outside die area
[WARNING] Pin la_data_out[52] is outside die area
[WARNING] Pin la_data_out[53] is outside die area
[WARNING] Pin la_data_out[54] is outside die area
[WARNING] Pin la_data_out[55] is outside die area
[WARNING] Pin la_data_out[56] is outside die area
[WARNING] Pin la_data_out[57] is outside die area
[WARNING] Pin la_data_out[58] is outside die area
[WARNING] Pin la_data_out[59] is outside die area
[WARNING] Pin la_data_out[5] is outside die area
[WARNING] Pin la_data_out[60] is outside die area
[WARNING] Pin la_data_out[61] is outside die area
[WARNING] Pin la_data_out[62] is outside die area
[WARNING] Pin la_data_out[63] is outside die area
[WARNING] Pin la_data_out[64] is outside die area
[WARNING] Pin la_data_out[65] is outside die area
[WARNING] Pin la_data_out[66] is outside die area
[WARNING] Pin la_data_out[67] is outside die area
[WARNING] Pin la_data_out[68] is outside die area
[WARNING] Pin la_data_out[69] is outside die area
[WARNING] Pin la_data_out[6] is outside die area
[WARNING] Pin la_data_out[70] is outside die area
[WARNING] Pin la_data_out[71] is outside die area
[WARNING] Pin la_data_out[72] is outside die area
[WARNING] Pin la_data_out[73] is outside die area
[WARNING] Pin la_data_out[74] is outside die area
[WARNING] Pin la_data_out[75] is outside die area
[WARNING] Pin la_data_out[76] is outside die area
[WARNING] Pin la_data_out[77] is outside die area
[WARNING] Pin la_data_out[78] is outside die area
[WARNING] Pin la_data_out[79] is outside die area
[WARNING] Pin la_data_out[7] is outside die area
[WARNING] Pin la_data_out[80] is outside die area
[WARNING] Pin la_data_out[81] is outside die area
[WARNING] Pin la_data_out[82] is outside die area
[WARNING] Pin la_data_out[83] is outside die area
[WARNING] Pin la_data_out[84] is outside die area
[WARNING] Pin la_data_out[85] is outside die area
[WARNING] Pin la_data_out[86] is outside die area
[WARNING] Pin la_data_out[87] is outside die area
[WARNING] Pin la_data_out[88] is outside die area
[WARNING] Pin la_data_out[89] is outside die area
[WARNING] Pin la_data_out[8] is outside die area
[WARNING] Pin la_data_out[90] is outside die area
[WARNING] Pin la_data_out[91] is outside die area
[WARNING] Pin la_data_out[92] is outside die area
[WARNING] Pin la_data_out[93] is outside die area
[WARNING] Pin la_data_out[94] is outside die area
[WARNING] Pin la_data_out[95] is outside die area
[WARNING] Pin la_data_out[96] is outside die area
[WARNING] Pin la_data_out[97] is outside die area
[WARNING] Pin la_data_out[98] is outside die area
[WARNING] Pin la_data_out[99] is outside die area
[WARNING] Pin la_data_out[9] is outside die area
[WARNING] Pin la_oen[0] is outside die area
[WARNING] Pin la_oen[100] is outside die area
[WARNING] Pin la_oen[101] is outside die area
[WARNING] Pin la_oen[102] is outside die area
[WARNING] Pin la_oen[103] is outside die area
[WARNING] Pin la_oen[104] is outside die area
[WARNING] Pin la_oen[105] is outside die area
[WARNING] Pin la_oen[106] is outside die area
[WARNING] Pin la_oen[107] is outside die area
[WARNING] Pin la_oen[108] is outside die area
[WARNING] Pin la_oen[109] is outside die area
[WARNING] Pin la_oen[10] is outside die area
[WARNING] Pin la_oen[110] is outside die area
[WARNING] Pin la_oen[111] is outside die area
[WARNING] Pin la_oen[112] is outside die area
[WARNING] Pin la_oen[113] is outside die area
[WARNING] Pin la_oen[114] is outside die area
[WARNING] Pin la_oen[115] is outside die area
[WARNING] Pin la_oen[116] is outside die area
[WARNING] Pin la_oen[117] is outside die area
[WARNING] Pin la_oen[118] is outside die area
[WARNING] Pin la_oen[119] is outside die area
[WARNING] Pin la_oen[11] is outside die area
[WARNING] Pin la_oen[120] is outside die area
[WARNING] Pin la_oen[121] is outside die area
[WARNING] Pin la_oen[122] is outside die area
[WARNING] Pin la_oen[123] is outside die area
[WARNING] Pin la_oen[124] is outside die area
[WARNING] Pin la_oen[125] is outside die area
[WARNING] Pin la_oen[126] is outside die area
[WARNING] Pin la_oen[127] is outside die area
[WARNING] Pin la_oen[12] is outside die area
[WARNING] Pin la_oen[13] is outside die area
[WARNING] Pin la_oen[14] is outside die area
[WARNING] Pin la_oen[15] is outside die area
[WARNING] Pin la_oen[16] is outside die area
[WARNING] Pin la_oen[17] is outside die area
[WARNING] Pin la_oen[18] is outside die area
[WARNING] Pin la_oen[19] is outside die area
[WARNING] Pin la_oen[1] is outside die area
[WARNING] Pin la_oen[20] is outside die area
[WARNING] Pin la_oen[21] is outside die area
[WARNING] Pin la_oen[22] is outside die area
[WARNING] Pin la_oen[23] is outside die area
[WARNING] Pin la_oen[24] is outside die area
[WARNING] Pin la_oen[25] is outside die area
[WARNING] Pin la_oen[26] is outside die area
[WARNING] Pin la_oen[27] is outside die area
[WARNING] Pin la_oen[28] is outside die area
[WARNING] Pin la_oen[29] is outside die area
[WARNING] Pin la_oen[2] is outside die area
[WARNING] Pin la_oen[30] is outside die area
[WARNING] Pin la_oen[31] is outside die area
[WARNING] Pin la_oen[32] is outside die area
[WARNING] Pin la_oen[33] is outside die area
[WARNING] Pin la_oen[34] is outside die area
[WARNING] Pin la_oen[35] is outside die area
[WARNING] Pin la_oen[36] is outside die area
[WARNING] Pin la_oen[37] is outside die area
[WARNING] Pin la_oen[38] is outside die area
[WARNING] Pin la_oen[39] is outside die area
[WARNING] Pin la_oen[3] is outside die area
[WARNING] Pin la_oen[40] is outside die area
[WARNING] Pin la_oen[41] is outside die area
[WARNING] Pin la_oen[42] is outside die area
[WARNING] Pin la_oen[43] is outside die area
[WARNING] Pin la_oen[44] is outside die area
[WARNING] Pin la_oen[45] is outside die area
[WARNING] Pin la_oen[46] is outside die area
[WARNING] Pin la_oen[47] is outside die area
[WARNING] Pin la_oen[48] is outside die area
[WARNING] Pin la_oen[49] is outside die area
[WARNING] Pin la_oen[4] is outside die area
[WARNING] Pin la_oen[50] is outside die area
[WARNING] Pin la_oen[51] is outside die area
[WARNING] Pin la_oen[52] is outside die area
[WARNING] Pin la_oen[53] is outside die area
[WARNING] Pin la_oen[54] is outside die area
[WARNING] Pin la_oen[55] is outside die area
[WARNING] Pin la_oen[56] is outside die area
[WARNING] Pin la_oen[57] is outside die area
[WARNING] Pin la_oen[58] is outside die area
[WARNING] Pin la_oen[59] is outside die area
[WARNING] Pin la_oen[5] is outside die area
[WARNING] Pin la_oen[60] is outside die area
[WARNING] Pin la_oen[61] is outside die area
[WARNING] Pin la_oen[62] is outside die area
[WARNING] Pin la_oen[63] is outside die area
[WARNING] Pin la_oen[64] is outside die area
[WARNING] Pin la_oen[65] is outside die area
[WARNING] Pin la_oen[66] is outside die area
[WARNING] Pin la_oen[67] is outside die area
[WARNING] Pin la_oen[68] is outside die area
[WARNING] Pin la_oen[69] is outside die area
[WARNING] Pin la_oen[6] is outside die area
[WARNING] Pin la_oen[70] is outside die area
[WARNING] Pin la_oen[71] is outside die area
[WARNING] Pin la_oen[72] is outside die area
[WARNING] Pin la_oen[73] is outside die area
[WARNING] Pin la_oen[74] is outside die area
[WARNING] Pin la_oen[75] is outside die area
[WARNING] Pin la_oen[76] is outside die area
[WARNING] Pin la_oen[77] is outside die area
[WARNING] Pin la_oen[78] is outside die area
[WARNING] Pin la_oen[79] is outside die area
[WARNING] Pin la_oen[7] is outside die area
[WARNING] Pin la_oen[80] is outside die area
[WARNING] Pin la_oen[81] is outside die area
[WARNING] Pin la_oen[82] is outside die area
[WARNING] Pin la_oen[83] is outside die area
[WARNING] Pin la_oen[84] is outside die area
[WARNING] Pin la_oen[85] is outside die area
[WARNING] Pin la_oen[86] is outside die area
[WARNING] Pin la_oen[87] is outside die area
[WARNING] Pin la_oen[88] is outside die area
[WARNING] Pin la_oen[89] is outside die area
[WARNING] Pin la_oen[8] is outside die area
[WARNING] Pin la_oen[90] is outside die area
[WARNING] Pin la_oen[91] is outside die area
[WARNING] Pin la_oen[92] is outside die area
[WARNING] Pin la_oen[93] is outside die area
[WARNING] Pin la_oen[94] is outside die area
[WARNING] Pin la_oen[95] is outside die area
[WARNING] Pin la_oen[96] is outside die area
[WARNING] Pin la_oen[97] is outside die area
[WARNING] Pin la_oen[98] is outside die area
[WARNING] Pin la_oen[99] is outside die area
[WARNING] Pin la_oen[9] is outside die area
[WARNING] Pin user_clock2 is outside die area
[WARNING] Pin wb_clk_i is outside die area
[WARNING] Pin wb_rst_i is outside die area
[WARNING] Pin wbs_ack_o is outside die area
[WARNING] Pin wbs_adr_i[0] is outside die area
[WARNING] Pin wbs_adr_i[10] is outside die area
[WARNING] Pin wbs_adr_i[11] is outside die area
[WARNING] Pin wbs_adr_i[12] is outside die area
[WARNING] Pin wbs_adr_i[13] is outside die area
[WARNING] Pin wbs_adr_i[14] is outside die area
[WARNING] Pin wbs_adr_i[15] is outside die area
[WARNING] Pin wbs_adr_i[16] is outside die area
[WARNING] Pin wbs_adr_i[17] is outside die area
[WARNING] Pin wbs_adr_i[18] is outside die area
[WARNING] Pin wbs_adr_i[19] is outside die area
[WARNING] Pin wbs_adr_i[1] is outside die area
[WARNING] Pin wbs_adr_i[20] is outside die area
[WARNING] Pin wbs_adr_i[21] is outside die area
[WARNING] Pin wbs_adr_i[22] is outside die area
[WARNING] Pin wbs_adr_i[23] is outside die area
[WARNING] Pin wbs_adr_i[24] is outside die area
[WARNING] Pin wbs_adr_i[25] is outside die area
[WARNING] Pin wbs_adr_i[26] is outside die area
[WARNING] Pin wbs_adr_i[27] is outside die area
[WARNING] Pin wbs_adr_i[28] is outside die area
[WARNING] Pin wbs_adr_i[29] is outside die area
[WARNING] Pin wbs_adr_i[2] is outside die area
[WARNING] Pin wbs_adr_i[30] is outside die area
[WARNING] Pin wbs_adr_i[31] is outside die area
[WARNING] Pin wbs_adr_i[3] is outside die area
[WARNING] Pin wbs_adr_i[4] is outside die area
[WARNING] Pin wbs_adr_i[5] is outside die area
[WARNING] Pin wbs_adr_i[6] is outside die area
[WARNING] Pin wbs_adr_i[7] is outside die area
[WARNING] Pin wbs_adr_i[8] is outside die area
[WARNING] Pin wbs_adr_i[9] is outside die area
[WARNING] Pin wbs_cyc_i is outside die area
[WARNING] Pin wbs_dat_i[0] is outside die area
[WARNING] Pin wbs_dat_i[10] is outside die area
[WARNING] Pin wbs_dat_i[11] is outside die area
[WARNING] Pin wbs_dat_i[12] is outside die area
[WARNING] Pin wbs_dat_i[13] is outside die area
[WARNING] Pin wbs_dat_i[14] is outside die area
[WARNING] Pin wbs_dat_i[15] is outside die area
[WARNING] Pin wbs_dat_i[16] is outside die area
[WARNING] Pin wbs_dat_i[17] is outside die area
[WARNING] Pin wbs_dat_i[18] is outside die area
[WARNING] Pin wbs_dat_i[19] is outside die area
[WARNING] Pin wbs_dat_i[1] is outside die area
[WARNING] Pin wbs_dat_i[20] is outside die area
[WARNING] Pin wbs_dat_i[21] is outside die area
[WARNING] Pin wbs_dat_i[22] is outside die area
[WARNING] Pin wbs_dat_i[23] is outside die area
[WARNING] Pin wbs_dat_i[24] is outside die area
[WARNING] Pin wbs_dat_i[25] is outside die area
[WARNING] Pin wbs_dat_i[26] is outside die area
[WARNING] Pin wbs_dat_i[27] is outside die area
[WARNING] Pin wbs_dat_i[28] is outside die area
[WARNING] Pin wbs_dat_i[29] is outside die area
[WARNING] Pin wbs_dat_i[2] is outside die area
[WARNING] Pin wbs_dat_i[30] is outside die area
[WARNING] Pin wbs_dat_i[31] is outside die area
[WARNING] Pin wbs_dat_i[3] is outside die area
[WARNING] Pin wbs_dat_i[4] is outside die area
[WARNING] Pin wbs_dat_i[5] is outside die area
[WARNING] Pin wbs_dat_i[6] is outside die area
[WARNING] Pin wbs_dat_i[7] is outside die area
[WARNING] Pin wbs_dat_i[8] is outside die area
[WARNING] Pin wbs_dat_i[9] is outside die area
[WARNING] Pin wbs_dat_o[0] is outside die area
[WARNING] Pin wbs_dat_o[10] is outside die area
[WARNING] Pin wbs_dat_o[11] is outside die area
[WARNING] Pin wbs_dat_o[12] is outside die area
[WARNING] Pin wbs_dat_o[13] is outside die area
[WARNING] Pin wbs_dat_o[14] is outside die area
[WARNING] Pin wbs_dat_o[15] is outside die area
[WARNING] Pin wbs_dat_o[16] is outside die area
[WARNING] Pin wbs_dat_o[17] is outside die area
[WARNING] Pin wbs_dat_o[18] is outside die area
[WARNING] Pin wbs_dat_o[19] is outside die area
[WARNING] Pin wbs_dat_o[1] is outside die area
[WARNING] Pin wbs_dat_o[20] is outside die area
[WARNING] Pin wbs_dat_o[21] is outside die area
[WARNING] Pin wbs_dat_o[22] is outside die area
[WARNING] Pin wbs_dat_o[23] is outside die area
[WARNING] Pin wbs_dat_o[24] is outside die area
[WARNING] Pin wbs_dat_o[25] is outside die area
[WARNING] Pin wbs_dat_o[26] is outside die area
[WARNING] Pin wbs_dat_o[27] is outside die area
[WARNING] Pin wbs_dat_o[28] is outside die area
[WARNING] Pin wbs_dat_o[29] is outside die area
[WARNING] Pin wbs_dat_o[2] is outside die area
[WARNING] Pin wbs_dat_o[30] is outside die area
[WARNING] Pin wbs_dat_o[31] is outside die area
[WARNING] Pin wbs_dat_o[3] is outside die area
[WARNING] Pin wbs_dat_o[4] is outside die area
[WARNING] Pin wbs_dat_o[5] is outside die area
[WARNING] Pin wbs_dat_o[6] is outside die area
[WARNING] Pin wbs_dat_o[7] is outside die area
[WARNING] Pin wbs_dat_o[8] is outside die area
[WARNING] Pin wbs_dat_o[9] is outside die area
[WARNING] Pin wbs_sel_i[0] is outside die area
[WARNING] Pin wbs_sel_i[1] is outside die area
[WARNING] Pin wbs_sel_i[2] is outside die area
[WARNING] Pin wbs_sel_i[3] is outside die area
[WARNING] Pin wbs_stb_i is outside die area
[WARNING] Pin wbs_we_i is outside die area
[INFO] Minimum degree: 2
[INFO] Maximum degree: 2
[INFO] Processing 1 obstacles on layer 1
[INFO] Processing 2560 obstacles on layer 2
[INFO] Processing 1228 obstacles on layer 3
[INFO] Processing 21 obstacles on layer 4
[INFO] Processing 347 obstacles on layer 5
[INFO] Reducing resources of layer 1 by 99%
[INFO] WIRELEN : 57825, WIRELEN1 : 0
[INFO] NumSeg : 604
[INFO] NumShift: 0
First L Route
[INFO] WIRELEN : 57825, WIRELEN1 : 57825
[INFO] NumSeg : 604
[INFO] NumShift: 0
[Overflow Report] Total hCap : 358500
[Overflow Report] Total vCap : 345118
[Overflow Report] Total Usage : 57825
[Overflow Report] Max H Overflow: 5
[Overflow Report] Max V Overflow: 1
[Overflow Report] Max Overflow : 5
[Overflow Report] Num Overflow e: 26302
[Overflow Report] H Overflow : 17508
[Overflow Report] V Overflow : 9869
[Overflow Report] Final Overflow: 27377
Second L Route
[Overflow Report] Total hCap : 358500
[Overflow Report] Total vCap : 345118
[Overflow Report] Total Usage : 57825
[Overflow Report] Max H Overflow: 4
[Overflow Report] Max V Overflow: 1
[Overflow Report] Max Overflow : 4
[Overflow Report] Num Overflow e: 26088
[Overflow Report] H Overflow : 17509
[Overflow Report] V Overflow : 9440
[Overflow Report] Final Overflow: 26949
First Z Route
[Overflow Report] Total hCap : 358500
[Overflow Report] Total vCap : 345118
[Overflow Report] Total Usage : 57825
[Overflow Report] Max H Overflow: 1
[Overflow Report] Max V Overflow: 10
[Overflow Report] Max Overflow : 10
[Overflow Report] Num Overflow e: 1510
[Overflow Report] H Overflow : 1237
[Overflow Report] V Overflow : 786
[Overflow Report] Final Overflow: 2023
[INFO] LV routing round 0, enlarge 10
[INFO] 10 threshold, 10 expand
[Overflow Report] total Usage : 57831
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H Overflow : 0
[Overflow Report] V Overflow : 0
[Overflow Report] Final Overflow: 0
[INFO] LV routing round 1, enlarge 15
[INFO] 5 threshold, 15 expand
[Overflow Report] total Usage : 57831
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H Overflow : 0
[Overflow Report] V Overflow : 0
[Overflow Report] Final Overflow: 0
[INFO] LV routing round 2, enlarge 20
[INFO] 1 threshold, 20 expand
[Overflow Report] total Usage : 57831
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H Overflow : 0
[Overflow Report] V Overflow : 0
[Overflow Report] Final Overflow: 0
Usage checked
Maze routing finished
[INFO] P3 runtime: 0.010000 sec
[INFO] Final 2D results:
[Overflow Report] total Usage : 57831
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H Overflow : 0
[Overflow Report] V Overflow : 0
[Overflow Report] Final Overflow: 0
Layer Assignment Begins
Layer assignment finished
[INFO] 2D + Layer Assignment Runtime: 0.150000 sec
Post Processing Begins
Post Processsing finished
Starting via filling
[INFO] Via related to pin nodes 1643
[INFO] Via related stiner nodes 0
Via filling finished
Final usage/overflow report:
[INFO] Usage per layer:
Layer 1 usage: 0
Layer 2 usage: 28763
Layer 3 usage: 23560
Layer 4 usage: 5488
Layer 5 usage: 20
[INFO] Capacity per layer:
Layer 1 capacity: 0
Layer 2 capacity: 212282
Layer 3 capacity: 195432
Layer 4 capacity: 146218
Layer 5 capacity: 149686
[INFO] Use percentage per layer:
Layer 1 use percentage: 0.0%
Layer 2 use percentage: 13.55%
Layer 3 use percentage: 12.06%
Layer 4 use percentage: 3.75%
Layer 5 use percentage: 0.01%
[INFO] Overflow per layer:
Layer 1 overflow: 0
Layer 2 overflow: 0
Layer 3 overflow: 0
Layer 4 overflow: 0
Layer 5 overflow: 0
[Overflow Report] Total Usage : 57831
[Overflow Report] Total Capacity: 703618
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow : 0
[Overflow Report] H Overflow : 0
[Overflow Report] V Overflow : 0
[Overflow Report] Final Overflow: 0
[INFO] Final usage : 57831
[INFO] Final number of vias : 2594
[INFO] Final usage 3D : 65613
[INFO] Total wirelength: 434693 um
[INFO] Num routed nets: 604
Warning: /home/jcyr/openlane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found.
Warning: /home/jcyr/openlane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found.
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load $cap_load [all_outputs]
[INFO]: Changing layout from /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/placement/user_project_wrapper.placement.def to /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/routing/fastroute.def
[INFO]: Current Def is /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/routing/fastroute.def
[INFO]: Running Fill Insertion...
[INFO]: Changing layout from /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/routing/fastroute.def to /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/routing/addspacers.def
[INFO]: Writing Verilog...
OpenROAD 0.9.0 d03ebfc244
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Error: cannot open '/.openroad'.
Notice 0: Reading LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0: Created 13 technology layers
Notice 0: Created 25 technology vias
Notice 0: Created 439 library cells
Notice 0: Finished LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
Notice 0:
Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/routing/addspacers.def
Notice 0: Design: user_project_wrapper
Notice 0: Created 644 pins.
Notice 0: Created 1 components and 638 component-terminals.
Notice 0: Created 8 special nets and 0 connections.
Notice 0: Created 636 nets and 604 connections.
Notice 0: Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/routing/addspacers.def
[INFO]: Changing netlist from /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/synthesis/user_project_wrapper.synthesis.v to /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/synthesis/user_project_wrapper.synthesis_preroute.v
[INFO]: Running Detailed Routing...
reading lef ...
units: 1000
#layers: 13
#macros: 439
#vias: 25
#viarulegen: 25
reading def ...
defIn read 1000 pins
design: user_project_wrapper
die area: ( 0 0 ) ( 2920000 3520000 )
trackPts: 12
defvias: 4
#components: 1
#terminals: 1081
#snets: 8
#nets: 636
reading guide ...
#guides: 4205
Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
done initConstraintLayerIdx
List of default vias:
Layer mcon
default via: L1M1_PR_MR
Layer via
default via: M1M2_PR
Layer via2
default via: via2_FR
Layer via3
default via: M3M4_PR_M
Layer via4
default via: via4_FR
Writing reference output def...
libcell analysis ...
instance analysis ...
#unique instances = 1
init region query ...
complete FR_MASTERSLICE
complete FR_VIA
complete li1
complete mcon
complete met1
complete via
complete met2
complete via2
complete met3
complete via3
complete met4
complete via4
complete met5
FR_MASTERSLICE shape region query size = 0
FR_VIA shape region query size = 0
li1 shape region query size = 1
mcon shape region query size = 0
met1 shape region query size = 2800
via shape region query size = 2160
met2 shape region query size = 2235
via2 shape region query size = 1680
met3 shape region query size = 610
via3 shape region query size = 1680
met4 shape region query size = 1540
via4 shape region query size = 1360
met5 shape region query size = 1024
start pin access
complete 100 pins
complete 200 pins
complete 300 pins
complete 400 pins
complete 500 pins
complete 600 pins
complete 636 pins
complete 0 unique inst patterns
complete 0 groups
Expt1 runtime (pin-level access point gen): 0.560931
Expt2 runtime (design-level access pattern gen): 7.72e-06
#scanned instances = 1
#unique instances = 1
#stdCellGenAp = 0
#stdCellValidPlanarAp = 0
#stdCellValidViaAp = 0
#stdCellPinNoAp = 0
#stdCellPinCnt = 0
#instTermValidViaApCnt = 0
#macroGenAp = 3785
#macroValidPlanarAp = 3785
#macroValidViaAp = 0
#macroNoAp = 0
complete pin access
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 19.66 (MB), peak = 19.76 (MB)
post process guides ...
GCELLGRID X -1 DO 510 STEP 6900 ;
GCELLGRID Y -1 DO 423 STEP 6900 ;
complete FR_MASTERSLICE
complete FR_VIA
complete li1
complete mcon
complete met1
complete via
complete met2
complete via2
complete met3
complete via3
complete met4
complete via4
complete met5
building cmap ...
init guide query ...
complete FR_MASTERSLICE (guide)
complete FR_VIA (guide)
complete li1 (guide)
complete mcon (guide)
complete met1 (guide)
complete via (guide)
complete met2 (guide)
complete via2 (guide)
complete met3 (guide)
complete via3 (guide)
complete met4 (guide)
complete via4 (guide)
complete met5 (guide)
FR_MASTERSLICE guide region query size = 0
FR_VIA guide region query size = 0
li1 guide region query size = 0
mcon guide region query size = 0
met1 guide region query size = 854
via guide region query size = 0
met2 guide region query size = 1611
via2 guide region query size = 0
met3 guide region query size = 108
via3 guide region query size = 0
met4 guide region query size = 5
via4 guide region query size = 0
met5 guide region query size = 0
init gr pin query ...
start track assignment
Done with 1616 vertical wires in 9 frboxes and 962 horizontal wires in 11 frboxes.
Done with 108 vertical wires in 9 frboxes and 46 horizontal wires in 11 frboxes.
complete track assignment
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 124.22 (MB), peak = 126.36 (MB)
post processing ...
start routing data preparation
initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1)
initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0)
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 129.38 (MB), peak = 129.49 (MB)
start detail routing ...
start 0th optimization iteration ...
completing 10% with 0 violations
elapsed time = 00:00:02, memory = 193.09 (MB)
completing 20% with 0 violations
elapsed time = 00:00:05, memory = 230.55 (MB)
completing 30% with 3177 violations
elapsed time = 00:00:07, memory = 187.06 (MB)
completing 40% with 3177 violations
elapsed time = 00:00:09, memory = 214.81 (MB)
completing 50% with 3074 violations
elapsed time = 00:00:12, memory = 172.06 (MB)
completing 60% with 2945 violations
elapsed time = 00:00:14, memory = 198.37 (MB)
completing 70% with 2945 violations
elapsed time = 00:00:17, memory = 232.68 (MB)
completing 80% with 1695 violations
elapsed time = 00:00:19, memory = 184.24 (MB)
completing 90% with 1695 violations
elapsed time = 00:00:22, memory = 212.35 (MB)
completing 100% with 630 violations
elapsed time = 00:00:24, memory = 159.77 (MB)
number of violations = 630
cpu time = 00:01:37, elapsed time = 00:00:24, memory = 159.77 (MB), peak = 474.04 (MB)
total wire length = 412987 um
total wire length on LAYER li1 = 184 um
total wire length on LAYER met1 = 197643 um
total wire length on LAYER met2 = 175141 um
total wire length on LAYER met3 = 39932 um
total wire length on LAYER met4 = 85 um
total wire length on LAYER met5 = 0 um
total number of vias = 2003
up-via summary (total 2003):
-----------------------
FR_MASTERSLICE 0
li1 164
met1 1664
met2 165
met3 10
met4 0
-----------------------
2003
start 1st optimization iteration ...
completing 10% with 630 violations
elapsed time = 00:00:02, memory = 205.39 (MB)
completing 20% with 630 violations
elapsed time = 00:00:04, memory = 240.46 (MB)
completing 30% with 421 violations
elapsed time = 00:00:07, memory = 182.12 (MB)
completing 40% with 421 violations
elapsed time = 00:00:09, memory = 211.18 (MB)
completing 50% with 421 violations
elapsed time = 00:00:11, memory = 174.80 (MB)
completing 60% with 421 violations
elapsed time = 00:00:13, memory = 206.89 (MB)
completing 70% with 421 violations
elapsed time = 00:00:16, memory = 234.75 (MB)
completing 80% with 225 violations
elapsed time = 00:00:18, memory = 182.39 (MB)
completing 90% with 225 violations
elapsed time = 00:00:20, memory = 212.04 (MB)
completing 100% with 224 violations
elapsed time = 00:00:22, memory = 180.09 (MB)
number of violations = 224
cpu time = 00:01:31, elapsed time = 00:00:23, memory = 180.09 (MB), peak = 494.36 (MB)
total wire length = 413300 um
total wire length on LAYER li1 = 342 um
total wire length on LAYER met1 = 196828 um
total wire length on LAYER met2 = 175200 um
total wire length on LAYER met3 = 40713 um
total wire length on LAYER met4 = 216 um
total wire length on LAYER met5 = 0 um
total number of vias = 2259
up-via summary (total 2259):
-----------------------
FR_MASTERSLICE 0
li1 242
met1 1686
met2 205
met3 126
met4 0
-----------------------
2259
start 2nd optimization iteration ...
completing 10% with 224 violations
elapsed time = 00:00:00, memory = 183.70 (MB)
completing 20% with 224 violations
elapsed time = 00:00:00, memory = 186.02 (MB)
completing 30% with 419 violations
elapsed time = 00:00:00, memory = 186.28 (MB)
completing 40% with 419 violations
elapsed time = 00:00:00, memory = 186.46 (MB)
completing 50% with 399 violations
elapsed time = 00:00:00, memory = 186.46 (MB)
completing 60% with 399 violations
elapsed time = 00:00:01, memory = 186.67 (MB)
completing 70% with 399 violations
elapsed time = 00:00:01, memory = 186.67 (MB)
completing 80% with 276 violations
elapsed time = 00:00:01, memory = 186.67 (MB)
completing 90% with 276 violations
elapsed time = 00:00:01, memory = 186.67 (MB)
completing 100% with 259 violations
elapsed time = 00:00:01, memory = 186.67 (MB)
number of violations = 259
cpu time = 00:00:05, elapsed time = 00:00:01, memory = 186.67 (MB), peak = 499.65 (MB)
total wire length = 413421 um
total wire length on LAYER li1 = 368 um
total wire length on LAYER met1 = 196880 um
total wire length on LAYER met2 = 175208 um
total wire length on LAYER met3 = 40751 um
total wire length on LAYER met4 = 214 um
total wire length on LAYER met5 = 0 um
total number of vias = 2275
up-via summary (total 2275):
-----------------------
FR_MASTERSLICE 0
li1 270
met1 1676
met2 189
met3 140
met4 0
-----------------------
2275
start 3rd optimization iteration ...
completing 10% with 259 violations
elapsed time = 00:00:00, memory = 186.67 (MB)
completing 20% with 259 violations
elapsed time = 00:00:00, memory = 187.18 (MB)
completing 30% with 250 violations
elapsed time = 00:00:01, memory = 187.43 (MB)
completing 40% with 250 violations
elapsed time = 00:00:01, memory = 187.43 (MB)
completing 50% with 233 violations
elapsed time = 00:00:01, memory = 187.43 (MB)
completing 60% with 232 violations
elapsed time = 00:00:01, memory = 187.43 (MB)
completing 70% with 232 violations
elapsed time = 00:00:01, memory = 187.43 (MB)
completing 80% with 211 violations
elapsed time = 00:00:02, memory = 187.43 (MB)
completing 90% with 211 violations
elapsed time = 00:00:02, memory = 187.43 (MB)
completing 100% with 120 violations
elapsed time = 00:00:03, memory = 188.72 (MB)
number of violations = 120
cpu time = 00:00:10, elapsed time = 00:00:03, memory = 188.72 (MB), peak = 501.44 (MB)
total wire length = 413529 um
total wire length on LAYER li1 = 432 um
total wire length on LAYER met1 = 196771 um
total wire length on LAYER met2 = 175207 um
total wire length on LAYER met3 = 40727 um
total wire length on LAYER met4 = 390 um
total wire length on LAYER met5 = 0 um
total number of vias = 2479
up-via summary (total 2479):
-----------------------
FR_MASTERSLICE 0
li1 374
met1 1684
met2 195
met3 226
met4 0
-----------------------
2479
start 4th optimization iteration ...
completing 10% with 120 violations
elapsed time = 00:00:00, memory = 188.98 (MB)
completing 20% with 120 violations
elapsed time = 00:00:00, memory = 189.03 (MB)
completing 30% with 93 violations
elapsed time = 00:00:01, memory = 189.03 (MB)
completing 40% with 93 violations
elapsed time = 00:00:01, memory = 189.03 (MB)
completing 50% with 81 violations
elapsed time = 00:00:01, memory = 189.03 (MB)
completing 60% with 81 violations
elapsed time = 00:00:01, memory = 189.03 (MB)
completing 70% with 81 violations
elapsed time = 00:00:01, memory = 189.03 (MB)
completing 80% with 57 violations
elapsed time = 00:00:01, memory = 189.03 (MB)
completing 90% with 57 violations
elapsed time = 00:00:01, memory = 189.03 (MB)
completing 100% with 53 violations
elapsed time = 00:00:01, memory = 189.03 (MB)
number of violations = 53
cpu time = 00:00:04, elapsed time = 00:00:02, memory = 189.03 (MB), peak = 501.75 (MB)
total wire length = 413591 um
total wire length on LAYER li1 = 466 um
total wire length on LAYER met1 = 196762 um
total wire length on LAYER met2 = 175201 um
total wire length on LAYER met3 = 40626 um
total wire length on LAYER met4 = 451 um
total wire length on LAYER met5 = 81 um
total number of vias = 2547
up-via summary (total 2547):
-----------------------
FR_MASTERSLICE 0
li1 402
met1 1684
met2 195
met3 262
met4 4
-----------------------
2547
start 5th optimization iteration ...
completing 10% with 53 violations
elapsed time = 00:00:00, memory = 189.03 (MB)
completing 20% with 53 violations
elapsed time = 00:00:00, memory = 189.03 (MB)
completing 30% with 28 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 40% with 28 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 50% with 28 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 60% with 28 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 70% with 28 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 80% with 10 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 90% with 10 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 100% with 10 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
number of violations = 10
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 189.16 (MB), peak = 501.89 (MB)
total wire length = 413609 um
total wire length on LAYER li1 = 482 um
total wire length on LAYER met1 = 196759 um
total wire length on LAYER met2 = 175191 um
total wire length on LAYER met3 = 40620 um
total wire length on LAYER met4 = 472 um
total wire length on LAYER met5 = 81 um
total number of vias = 2565
up-via summary (total 2565):
-----------------------
FR_MASTERSLICE 0
li1 414
met1 1684
met2 195
met3 268
met4 4
-----------------------
2565
start 6th optimization iteration ...
completing 10% with 10 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 20% with 10 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 30% with 5 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 40% with 5 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 50% with 5 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 60% with 5 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 70% with 5 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 80% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 90% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 100% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
number of violations = 2
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 189.16 (MB), peak = 501.89 (MB)
total wire length = 413610 um
total wire length on LAYER li1 = 484 um
total wire length on LAYER met1 = 196759 um
total wire length on LAYER met2 = 175191 um
total wire length on LAYER met3 = 40620 um
total wire length on LAYER met4 = 472 um
total wire length on LAYER met5 = 81 um
total number of vias = 2565
up-via summary (total 2565):
-----------------------
FR_MASTERSLICE 0
li1 414
met1 1684
met2 195
met3 268
met4 4
-----------------------
2565
start 7th optimization iteration ...
completing 10% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 20% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 30% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 40% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 50% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 60% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 70% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 80% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 90% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 100% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
number of violations = 2
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 189.16 (MB), peak = 501.89 (MB)
total wire length = 413610 um
total wire length on LAYER li1 = 484 um
total wire length on LAYER met1 = 196759 um
total wire length on LAYER met2 = 175191 um
total wire length on LAYER met3 = 40620 um
total wire length on LAYER met4 = 472 um
total wire length on LAYER met5 = 81 um
total number of vias = 2565
up-via summary (total 2565):
-----------------------
FR_MASTERSLICE 0
li1 414
met1 1684
met2 195
met3 268
met4 4
-----------------------
2565
start 8th optimization iteration ...
completing 10% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 20% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 30% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 40% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 50% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 60% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 70% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 80% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 90% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 100% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
number of violations = 2
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 189.16 (MB), peak = 501.89 (MB)
total wire length = 413610 um
total wire length on LAYER li1 = 484 um
total wire length on LAYER met1 = 196759 um
total wire length on LAYER met2 = 175191 um
total wire length on LAYER met3 = 40620 um
total wire length on LAYER met4 = 472 um
total wire length on LAYER met5 = 81 um
total number of vias = 2565
up-via summary (total 2565):
-----------------------
FR_MASTERSLICE 0
li1 414
met1 1684
met2 195
met3 268
met4 4
-----------------------
2565
start 9th optimization iteration ...
completing 10% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 20% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 30% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 40% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 50% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 60% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 70% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 80% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 90% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 100% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
number of violations = 2
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 189.16 (MB), peak = 501.89 (MB)
total wire length = 413610 um
total wire length on LAYER li1 = 484 um
total wire length on LAYER met1 = 196759 um
total wire length on LAYER met2 = 175191 um
total wire length on LAYER met3 = 40620 um
total wire length on LAYER met4 = 472 um
total wire length on LAYER met5 = 81 um
total number of vias = 2565
up-via summary (total 2565):
-----------------------
FR_MASTERSLICE 0
li1 414
met1 1684
met2 195
met3 268
met4 4
-----------------------
2565
start 10th optimization iteration ...
completing 10% with 2 violations
elapsed time = 00:00:00, memory = 189.16 (MB)
completing 20% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 30% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 40% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 50% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 60% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 70% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 80% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 90% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 100% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
number of violations = 2
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 189.17 (MB), peak = 501.89 (MB)
total wire length = 413610 um
total wire length on LAYER li1 = 484 um
total wire length on LAYER met1 = 196754 um
total wire length on LAYER met2 = 175191 um
total wire length on LAYER met3 = 40625 um
total wire length on LAYER met4 = 472 um
total wire length on LAYER met5 = 81 um
total number of vias = 2565
up-via summary (total 2565):
-----------------------
FR_MASTERSLICE 0
li1 414
met1 1684
met2 195
met3 268
met4 4
-----------------------
2565
start 11th optimization iteration ...
completing 10% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 20% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 30% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 40% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 50% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 60% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 70% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 80% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 90% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 100% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
number of violations = 2
cpu time = 00:00:01, elapsed time = 00:00:00, memory = 189.17 (MB), peak = 501.89 (MB)
total wire length = 413610 um
total wire length on LAYER li1 = 484 um
total wire length on LAYER met1 = 196759 um
total wire length on LAYER met2 = 175191 um
total wire length on LAYER met3 = 40620 um
total wire length on LAYER met4 = 472 um
total wire length on LAYER met5 = 81 um
total number of vias = 2565
up-via summary (total 2565):
-----------------------
FR_MASTERSLICE 0
li1 414
met1 1684
met2 195
met3 268
met4 4
-----------------------
2565
start 12th optimization iteration ...
completing 10% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 20% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 30% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 40% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 50% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 60% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 70% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 80% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 90% with 2 violations
elapsed time = 00:00:00, memory = 189.17 (MB)
completing 100% with 2 violations