blob: 2e527cfeb7b45f67d9c89b2d7a02ad7ff5fc725c [file] [log] [blame]
module Caravel_RAM_24KB_wb (
// Wishbone Interface
input wb_clk_i,
input wb_rst_i,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
output wb_ack_o,
output [31:0] wb_dat_o,
// Memory Interface
output [3:0] WE,
output EN,
output [31:0] Di,
input [31:0] Do,
output [12:0] A
);
wire valid;
wire ram_wen;
wire [3:0] wen; // write enable
assign valid = wb_cyc_i & wb_stb_i;
assign ram_wen = wb_we_i && valid;
assign wen = wb_sel_i & {4{ram_wen}} ;
/*
Ack Generation
- write transaction: asserted upon receiving adr_i & dat_i
- read transaction : asserted one clock cycle after receiving the adr_i & dat_i
*/
reg wb_ack_read;
reg wb_ack_o;
always @(posedge wb_clk_i) begin
if (wb_rst_i == 1'b 1) begin
wb_ack_read <= 1'b0;
wb_ack_o <= 1'b0;
end else begin
wb_ack_o <= wb_we_i? (valid & !wb_ack_o): wb_ack_read;
wb_ack_read <= (valid & !wb_ack_o) & !wb_ack_read;
end
end
assign wb_dat_o = Do;
// Memory Interface
assign WE = wen;
assign EN = valid;
assign Di = wb_dat_i;
assign A = wb_adr_i[14:2];
endmodule