blob: aa3cddd328ec70ea28b0627ec202659d889bd405 [file] [log] [blame]
module user_project_wrapper (user_clock2,
vccd1,
vccd2,
vdda1,
vdda2,
vssa1,
vssa2,
vssd1,
vssd2,
wb_clk_i,
wb_rst_i,
wbs_ack_o,
wbs_cyc_i,
wbs_stb_i,
wbs_we_i,
analog_io,
io_in,
io_oeb,
io_out,
la_data_in,
la_data_out,
la_oenb,
user_irq,
wbs_adr_i,
wbs_dat_i,
wbs_dat_o,
wbs_sel_i);
input user_clock2;
input vccd1;
input vccd2;
input vdda1;
input vdda2;
input vssa1;
input vssa2;
input vssd1;
input vssd2;
input wb_clk_i;
input wb_rst_i;
output wbs_ack_o;
input wbs_cyc_i;
input wbs_stb_i;
input wbs_we_i;
inout [28:0] analog_io;
input [37:0] io_in;
output [37:0] io_oeb;
output [37:0] io_out;
input [127:0] la_data_in;
output [127:0] la_data_out;
input [127:0] la_oenb;
output [2:0] user_irq;
input [31:0] wbs_adr_i;
input [31:0] wbs_dat_i;
output [31:0] wbs_dat_o;
input [3:0] wbs_sel_i;
wire \bist_correct[0] ;
wire \bist_correct[1] ;
wire \bist_correct[2] ;
wire \bist_correct[3] ;
wire \bist_correct_rp[0] ;
wire \bist_correct_rp[1] ;
wire \bist_correct_rp[2] ;
wire \bist_correct_rp[3] ;
wire bist_done;
wire bist_done_rp;
wire bist_en;
wire bist_en_rp;
wire \bist_error[0] ;
wire \bist_error[1] ;
wire \bist_error[2] ;
wire \bist_error[3] ;
wire \bist_error_cnt0[0] ;
wire \bist_error_cnt0[1] ;
wire \bist_error_cnt0[2] ;
wire \bist_error_cnt0[3] ;
wire \bist_error_cnt0_rp[0] ;
wire \bist_error_cnt0_rp[1] ;
wire \bist_error_cnt0_rp[2] ;
wire \bist_error_cnt0_rp[3] ;
wire \bist_error_cnt1[0] ;
wire \bist_error_cnt1[1] ;
wire \bist_error_cnt1[2] ;
wire \bist_error_cnt1[3] ;
wire \bist_error_cnt1_rp[0] ;
wire \bist_error_cnt1_rp[1] ;
wire \bist_error_cnt1_rp[2] ;
wire \bist_error_cnt1_rp[3] ;
wire \bist_error_cnt2[0] ;
wire \bist_error_cnt2[1] ;
wire \bist_error_cnt2[2] ;
wire \bist_error_cnt2[3] ;
wire \bist_error_cnt2_rp[0] ;
wire \bist_error_cnt2_rp[1] ;
wire \bist_error_cnt2_rp[2] ;
wire \bist_error_cnt2_rp[3] ;
wire \bist_error_cnt3[0] ;
wire \bist_error_cnt3[1] ;
wire \bist_error_cnt3[2] ;
wire \bist_error_cnt3[3] ;
wire \bist_error_cnt3_rp[0] ;
wire \bist_error_cnt3_rp[1] ;
wire \bist_error_cnt3_rp[2] ;
wire \bist_error_cnt3_rp[3] ;
wire \bist_error_rp[0] ;
wire \bist_error_rp[1] ;
wire \bist_error_rp[2] ;
wire \bist_error_rp[3] ;
wire bist_load;
wire bist_load_rp;
wire bist_run;
wire bist_run_rp;
wire bist_sdi;
wire bist_sdi_rp;
wire bist_sdo;
wire bist_sdo_rp;
wire bist_shift;
wire bist_shift_rp;
wire \cfg_boot_remap[0] ;
wire \cfg_boot_remap[1] ;
wire \cfg_boot_remap[2] ;
wire \cfg_boot_remap[3] ;
wire \cfg_clk_ctrl1[0] ;
wire \cfg_clk_ctrl1[10] ;
wire \cfg_clk_ctrl1[11] ;
wire \cfg_clk_ctrl1[12] ;
wire \cfg_clk_ctrl1[13] ;
wire \cfg_clk_ctrl1[14] ;
wire \cfg_clk_ctrl1[15] ;
wire \cfg_clk_ctrl1[16] ;
wire \cfg_clk_ctrl1[17] ;
wire \cfg_clk_ctrl1[18] ;
wire \cfg_clk_ctrl1[19] ;
wire \cfg_clk_ctrl1[1] ;
wire \cfg_clk_ctrl1[20] ;
wire \cfg_clk_ctrl1[21] ;
wire \cfg_clk_ctrl1[22] ;
wire \cfg_clk_ctrl1[23] ;
wire \cfg_clk_ctrl1[24] ;
wire \cfg_clk_ctrl1[25] ;
wire \cfg_clk_ctrl1[26] ;
wire \cfg_clk_ctrl1[27] ;
wire \cfg_clk_ctrl1[28] ;
wire \cfg_clk_ctrl1[29] ;
wire \cfg_clk_ctrl1[2] ;
wire \cfg_clk_ctrl1[30] ;
wire \cfg_clk_ctrl1[31] ;
wire \cfg_clk_ctrl1[3] ;
wire \cfg_clk_ctrl1[4] ;
wire \cfg_clk_ctrl1[5] ;
wire \cfg_clk_ctrl1[6] ;
wire \cfg_clk_ctrl1[7] ;
wire \cfg_clk_ctrl1[8] ;
wire \cfg_clk_ctrl1[9] ;
wire \cfg_clk_ctrl2[0] ;
wire \cfg_clk_ctrl2[10] ;
wire \cfg_clk_ctrl2[11] ;
wire \cfg_clk_ctrl2[12] ;
wire \cfg_clk_ctrl2[13] ;
wire \cfg_clk_ctrl2[14] ;
wire \cfg_clk_ctrl2[15] ;
wire \cfg_clk_ctrl2[16] ;
wire \cfg_clk_ctrl2[17] ;
wire \cfg_clk_ctrl2[18] ;
wire \cfg_clk_ctrl2[19] ;
wire \cfg_clk_ctrl2[1] ;
wire \cfg_clk_ctrl2[20] ;
wire \cfg_clk_ctrl2[21] ;
wire \cfg_clk_ctrl2[22] ;
wire \cfg_clk_ctrl2[23] ;
wire \cfg_clk_ctrl2[24] ;
wire \cfg_clk_ctrl2[25] ;
wire \cfg_clk_ctrl2[26] ;
wire \cfg_clk_ctrl2[27] ;
wire \cfg_clk_ctrl2[28] ;
wire \cfg_clk_ctrl2[29] ;
wire \cfg_clk_ctrl2[2] ;
wire \cfg_clk_ctrl2[30] ;
wire \cfg_clk_ctrl2[31] ;
wire \cfg_clk_ctrl2[3] ;
wire \cfg_clk_ctrl2[4] ;
wire \cfg_clk_ctrl2[5] ;
wire \cfg_clk_ctrl2[6] ;
wire \cfg_clk_ctrl2[7] ;
wire \cfg_clk_ctrl2[8] ;
wire \cfg_clk_ctrl2[9] ;
wire \cfg_colbits[0] ;
wire \cfg_colbits[1] ;
wire \cfg_cska_glbl_rp[0] ;
wire \cfg_cska_glbl_rp[1] ;
wire \cfg_cska_glbl_rp[2] ;
wire \cfg_cska_glbl_rp[3] ;
wire \cfg_cska_mbist_rp[0] ;
wire \cfg_cska_mbist_rp[1] ;
wire \cfg_cska_mbist_rp[2] ;
wire \cfg_cska_mbist_rp[3] ;
wire \cfg_cska_riscv_rp[0] ;
wire \cfg_cska_riscv_rp[1] ;
wire \cfg_cska_riscv_rp[2] ;
wire \cfg_cska_riscv_rp[3] ;
wire \cfg_cska_sd_ci_rp[0] ;
wire \cfg_cska_sd_ci_rp[1] ;
wire \cfg_cska_sd_ci_rp[2] ;
wire \cfg_cska_sd_ci_rp[3] ;
wire \cfg_cska_sd_co_rp[0] ;
wire \cfg_cska_sd_co_rp[1] ;
wire \cfg_cska_sd_co_rp[2] ;
wire \cfg_cska_sd_co_rp[3] ;
wire \cfg_cska_sdram_rp[0] ;
wire \cfg_cska_sdram_rp[1] ;
wire \cfg_cska_sdram_rp[2] ;
wire \cfg_cska_sdram_rp[3] ;
wire \cfg_cska_sp_co_rp[0] ;
wire \cfg_cska_sp_co_rp[1] ;
wire \cfg_cska_sp_co_rp[2] ;
wire \cfg_cska_sp_co_rp[3] ;
wire \cfg_cska_spi_rp[0] ;
wire \cfg_cska_spi_rp[1] ;
wire \cfg_cska_spi_rp[2] ;
wire \cfg_cska_spi_rp[3] ;
wire \cfg_cska_uart_rp[0] ;
wire \cfg_cska_uart_rp[1] ;
wire \cfg_cska_uart_rp[2] ;
wire \cfg_cska_uart_rp[3] ;
wire \cfg_req_depth[0] ;
wire \cfg_req_depth[1] ;
wire \cfg_sdr_cas[0] ;
wire \cfg_sdr_cas[1] ;
wire \cfg_sdr_cas[2] ;
wire cfg_sdr_en;
wire \cfg_sdr_mode_reg[0] ;
wire \cfg_sdr_mode_reg[10] ;
wire \cfg_sdr_mode_reg[11] ;
wire \cfg_sdr_mode_reg[12] ;
wire \cfg_sdr_mode_reg[1] ;
wire \cfg_sdr_mode_reg[2] ;
wire \cfg_sdr_mode_reg[3] ;
wire \cfg_sdr_mode_reg[4] ;
wire \cfg_sdr_mode_reg[5] ;
wire \cfg_sdr_mode_reg[6] ;
wire \cfg_sdr_mode_reg[7] ;
wire \cfg_sdr_mode_reg[8] ;
wire \cfg_sdr_mode_reg[9] ;
wire \cfg_sdr_rfmax[0] ;
wire \cfg_sdr_rfmax[1] ;
wire \cfg_sdr_rfmax[2] ;
wire \cfg_sdr_rfsh[0] ;
wire \cfg_sdr_rfsh[10] ;
wire \cfg_sdr_rfsh[11] ;
wire \cfg_sdr_rfsh[1] ;
wire \cfg_sdr_rfsh[2] ;
wire \cfg_sdr_rfsh[3] ;
wire \cfg_sdr_rfsh[4] ;
wire \cfg_sdr_rfsh[5] ;
wire \cfg_sdr_rfsh[6] ;
wire \cfg_sdr_rfsh[7] ;
wire \cfg_sdr_rfsh[8] ;
wire \cfg_sdr_rfsh[9] ;
wire \cfg_sdr_tras_d[0] ;
wire \cfg_sdr_tras_d[1] ;
wire \cfg_sdr_tras_d[2] ;
wire \cfg_sdr_tras_d[3] ;
wire \cfg_sdr_trcar_d[0] ;
wire \cfg_sdr_trcar_d[1] ;
wire \cfg_sdr_trcar_d[2] ;
wire \cfg_sdr_trcar_d[3] ;
wire \cfg_sdr_trcd_d[0] ;
wire \cfg_sdr_trcd_d[1] ;
wire \cfg_sdr_trcd_d[2] ;
wire \cfg_sdr_trcd_d[3] ;
wire \cfg_sdr_trp_d[0] ;
wire \cfg_sdr_trp_d[1] ;
wire \cfg_sdr_trp_d[2] ;
wire \cfg_sdr_trp_d[3] ;
wire \cfg_sdr_twr_d[0] ;
wire \cfg_sdr_twr_d[1] ;
wire \cfg_sdr_twr_d[2] ;
wire \cfg_sdr_twr_d[3] ;
wire \cfg_sdr_width[0] ;
wire \cfg_sdr_width[1] ;
wire cpu_clk;
wire cpu_rst_n;
wire \fuse_mhartid[0] ;
wire \fuse_mhartid[10] ;
wire \fuse_mhartid[11] ;
wire \fuse_mhartid[12] ;
wire \fuse_mhartid[13] ;
wire \fuse_mhartid[14] ;
wire \fuse_mhartid[15] ;
wire \fuse_mhartid[16] ;
wire \fuse_mhartid[17] ;
wire \fuse_mhartid[18] ;
wire \fuse_mhartid[19] ;
wire \fuse_mhartid[1] ;
wire \fuse_mhartid[20] ;
wire \fuse_mhartid[21] ;
wire \fuse_mhartid[22] ;
wire \fuse_mhartid[23] ;
wire \fuse_mhartid[24] ;
wire \fuse_mhartid[25] ;
wire \fuse_mhartid[26] ;
wire \fuse_mhartid[27] ;
wire \fuse_mhartid[28] ;
wire \fuse_mhartid[29] ;
wire \fuse_mhartid[2] ;
wire \fuse_mhartid[30] ;
wire \fuse_mhartid[31] ;
wire \fuse_mhartid[3] ;
wire \fuse_mhartid[4] ;
wire \fuse_mhartid[5] ;
wire \fuse_mhartid[6] ;
wire \fuse_mhartid[7] ;
wire \fuse_mhartid[8] ;
wire \fuse_mhartid[9] ;
wire \fuse_mhartid_rp[0] ;
wire \fuse_mhartid_rp[10] ;
wire \fuse_mhartid_rp[11] ;
wire \fuse_mhartid_rp[12] ;
wire \fuse_mhartid_rp[13] ;
wire \fuse_mhartid_rp[14] ;
wire \fuse_mhartid_rp[15] ;
wire \fuse_mhartid_rp[16] ;
wire \fuse_mhartid_rp[17] ;
wire \fuse_mhartid_rp[18] ;
wire \fuse_mhartid_rp[19] ;
wire \fuse_mhartid_rp[1] ;
wire \fuse_mhartid_rp[20] ;
wire \fuse_mhartid_rp[21] ;
wire \fuse_mhartid_rp[22] ;
wire \fuse_mhartid_rp[23] ;
wire \fuse_mhartid_rp[24] ;
wire \fuse_mhartid_rp[25] ;
wire \fuse_mhartid_rp[26] ;
wire \fuse_mhartid_rp[27] ;
wire \fuse_mhartid_rp[28] ;
wire \fuse_mhartid_rp[29] ;
wire \fuse_mhartid_rp[2] ;
wire \fuse_mhartid_rp[30] ;
wire \fuse_mhartid_rp[31] ;
wire \fuse_mhartid_rp[3] ;
wire \fuse_mhartid_rp[4] ;
wire \fuse_mhartid_rp[5] ;
wire \fuse_mhartid_rp[6] ;
wire \fuse_mhartid_rp[7] ;
wire \fuse_mhartid_rp[8] ;
wire \fuse_mhartid_rp[9] ;
wire i2c_rst_n;
wire \irq_lines[0] ;
wire \irq_lines[10] ;
wire \irq_lines[11] ;
wire \irq_lines[12] ;
wire \irq_lines[13] ;
wire \irq_lines[14] ;
wire \irq_lines[15] ;
wire \irq_lines[1] ;
wire \irq_lines[2] ;
wire \irq_lines[3] ;
wire \irq_lines[4] ;
wire \irq_lines[5] ;
wire \irq_lines[6] ;
wire \irq_lines[7] ;
wire \irq_lines[8] ;
wire \irq_lines[9] ;
wire \irq_lines_rp[0] ;
wire \irq_lines_rp[10] ;
wire \irq_lines_rp[11] ;
wire \irq_lines_rp[12] ;
wire \irq_lines_rp[13] ;
wire \irq_lines_rp[14] ;
wire \irq_lines_rp[15] ;
wire \irq_lines_rp[1] ;
wire \irq_lines_rp[2] ;
wire \irq_lines_rp[3] ;
wire \irq_lines_rp[4] ;
wire \irq_lines_rp[5] ;
wire \irq_lines_rp[6] ;
wire \irq_lines_rp[7] ;
wire \irq_lines_rp[8] ;
wire \irq_lines_rp[9] ;
wire mbist_rst_n;
wire \mem0_addr_a[10] ;
wire \mem0_addr_a[2] ;
wire \mem0_addr_a[3] ;
wire \mem0_addr_a[4] ;
wire \mem0_addr_a[5] ;
wire \mem0_addr_a[6] ;
wire \mem0_addr_a[7] ;
wire \mem0_addr_a[8] ;
wire \mem0_addr_a[9] ;
wire \mem0_addr_b[10] ;
wire \mem0_addr_b[2] ;
wire \mem0_addr_b[3] ;
wire \mem0_addr_b[4] ;
wire \mem0_addr_b[5] ;
wire \mem0_addr_b[6] ;
wire \mem0_addr_b[7] ;
wire \mem0_addr_b[8] ;
wire \mem0_addr_b[9] ;
wire \mem0_din_a[0] ;
wire \mem0_din_a[10] ;
wire \mem0_din_a[11] ;
wire \mem0_din_a[12] ;
wire \mem0_din_a[13] ;
wire \mem0_din_a[14] ;
wire \mem0_din_a[15] ;
wire \mem0_din_a[16] ;
wire \mem0_din_a[17] ;
wire \mem0_din_a[18] ;
wire \mem0_din_a[19] ;
wire \mem0_din_a[1] ;
wire \mem0_din_a[20] ;
wire \mem0_din_a[21] ;
wire \mem0_din_a[22] ;
wire \mem0_din_a[23] ;
wire \mem0_din_a[24] ;
wire \mem0_din_a[25] ;
wire \mem0_din_a[26] ;
wire \mem0_din_a[27] ;
wire \mem0_din_a[28] ;
wire \mem0_din_a[29] ;
wire \mem0_din_a[2] ;
wire \mem0_din_a[30] ;
wire \mem0_din_a[31] ;
wire \mem0_din_a[3] ;
wire \mem0_din_a[4] ;
wire \mem0_din_a[5] ;
wire \mem0_din_a[6] ;
wire \mem0_din_a[7] ;
wire \mem0_din_a[8] ;
wire \mem0_din_a[9] ;
wire \mem0_dout_a[0] ;
wire \mem0_dout_a[10] ;
wire \mem0_dout_a[11] ;
wire \mem0_dout_a[12] ;
wire \mem0_dout_a[13] ;
wire \mem0_dout_a[14] ;
wire \mem0_dout_a[15] ;
wire \mem0_dout_a[16] ;
wire \mem0_dout_a[17] ;
wire \mem0_dout_a[18] ;
wire \mem0_dout_a[19] ;
wire \mem0_dout_a[1] ;
wire \mem0_dout_a[20] ;
wire \mem0_dout_a[21] ;
wire \mem0_dout_a[22] ;
wire \mem0_dout_a[23] ;
wire \mem0_dout_a[24] ;
wire \mem0_dout_a[25] ;
wire \mem0_dout_a[26] ;
wire \mem0_dout_a[27] ;
wire \mem0_dout_a[28] ;
wire \mem0_dout_a[29] ;
wire \mem0_dout_a[2] ;
wire \mem0_dout_a[30] ;
wire \mem0_dout_a[31] ;
wire \mem0_dout_a[3] ;
wire \mem0_dout_a[4] ;
wire \mem0_dout_a[5] ;
wire \mem0_dout_a[6] ;
wire \mem0_dout_a[7] ;
wire \mem0_dout_a[8] ;
wire \mem0_dout_a[9] ;
wire \mem0_mask_a[0] ;
wire \mem0_mask_a[1] ;
wire \mem0_mask_a[2] ;
wire \mem0_mask_a[3] ;
wire \mem1_addr_a[10] ;
wire \mem1_addr_a[2] ;
wire \mem1_addr_a[3] ;
wire \mem1_addr_a[4] ;
wire \mem1_addr_a[5] ;
wire \mem1_addr_a[6] ;
wire \mem1_addr_a[7] ;
wire \mem1_addr_a[8] ;
wire \mem1_addr_a[9] ;
wire \mem1_addr_b[10] ;
wire \mem1_addr_b[2] ;
wire \mem1_addr_b[3] ;
wire \mem1_addr_b[4] ;
wire \mem1_addr_b[5] ;
wire \mem1_addr_b[6] ;
wire \mem1_addr_b[7] ;
wire \mem1_addr_b[8] ;
wire \mem1_addr_b[9] ;
wire \mem1_din_a[0] ;
wire \mem1_din_a[10] ;
wire \mem1_din_a[11] ;
wire \mem1_din_a[12] ;
wire \mem1_din_a[13] ;
wire \mem1_din_a[14] ;
wire \mem1_din_a[15] ;
wire \mem1_din_a[16] ;
wire \mem1_din_a[17] ;
wire \mem1_din_a[18] ;
wire \mem1_din_a[19] ;
wire \mem1_din_a[1] ;
wire \mem1_din_a[20] ;
wire \mem1_din_a[21] ;
wire \mem1_din_a[22] ;
wire \mem1_din_a[23] ;
wire \mem1_din_a[24] ;
wire \mem1_din_a[25] ;
wire \mem1_din_a[26] ;
wire \mem1_din_a[27] ;
wire \mem1_din_a[28] ;
wire \mem1_din_a[29] ;
wire \mem1_din_a[2] ;
wire \mem1_din_a[30] ;
wire \mem1_din_a[31] ;
wire \mem1_din_a[3] ;
wire \mem1_din_a[4] ;
wire \mem1_din_a[5] ;
wire \mem1_din_a[6] ;
wire \mem1_din_a[7] ;
wire \mem1_din_a[8] ;
wire \mem1_din_a[9] ;
wire \mem1_dout_a[0] ;
wire \mem1_dout_a[10] ;
wire \mem1_dout_a[11] ;
wire \mem1_dout_a[12] ;
wire \mem1_dout_a[13] ;
wire \mem1_dout_a[14] ;
wire \mem1_dout_a[15] ;
wire \mem1_dout_a[16] ;
wire \mem1_dout_a[17] ;
wire \mem1_dout_a[18] ;
wire \mem1_dout_a[19] ;
wire \mem1_dout_a[1] ;
wire \mem1_dout_a[20] ;
wire \mem1_dout_a[21] ;
wire \mem1_dout_a[22] ;
wire \mem1_dout_a[23] ;
wire \mem1_dout_a[24] ;
wire \mem1_dout_a[25] ;
wire \mem1_dout_a[26] ;
wire \mem1_dout_a[27] ;
wire \mem1_dout_a[28] ;
wire \mem1_dout_a[29] ;
wire \mem1_dout_a[2] ;
wire \mem1_dout_a[30] ;
wire \mem1_dout_a[31] ;
wire \mem1_dout_a[3] ;
wire \mem1_dout_a[4] ;
wire \mem1_dout_a[5] ;
wire \mem1_dout_a[6] ;
wire \mem1_dout_a[7] ;
wire \mem1_dout_a[8] ;
wire \mem1_dout_a[9] ;
wire \mem1_mask_a[0] ;
wire \mem1_mask_a[1] ;
wire \mem1_mask_a[2] ;
wire \mem1_mask_a[3] ;
wire \mem2_addr_a[10] ;
wire \mem2_addr_a[2] ;
wire \mem2_addr_a[3] ;
wire \mem2_addr_a[4] ;
wire \mem2_addr_a[5] ;
wire \mem2_addr_a[6] ;
wire \mem2_addr_a[7] ;
wire \mem2_addr_a[8] ;
wire \mem2_addr_a[9] ;
wire \mem2_addr_b[10] ;
wire \mem2_addr_b[2] ;
wire \mem2_addr_b[3] ;
wire \mem2_addr_b[4] ;
wire \mem2_addr_b[5] ;
wire \mem2_addr_b[6] ;
wire \mem2_addr_b[7] ;
wire \mem2_addr_b[8] ;
wire \mem2_addr_b[9] ;
wire \mem2_din_a[0] ;
wire \mem2_din_a[10] ;
wire \mem2_din_a[11] ;
wire \mem2_din_a[12] ;
wire \mem2_din_a[13] ;
wire \mem2_din_a[14] ;
wire \mem2_din_a[15] ;
wire \mem2_din_a[16] ;
wire \mem2_din_a[17] ;
wire \mem2_din_a[18] ;
wire \mem2_din_a[19] ;
wire \mem2_din_a[1] ;
wire \mem2_din_a[20] ;
wire \mem2_din_a[21] ;
wire \mem2_din_a[22] ;
wire \mem2_din_a[23] ;
wire \mem2_din_a[24] ;
wire \mem2_din_a[25] ;
wire \mem2_din_a[26] ;
wire \mem2_din_a[27] ;
wire \mem2_din_a[28] ;
wire \mem2_din_a[29] ;
wire \mem2_din_a[2] ;
wire \mem2_din_a[30] ;
wire \mem2_din_a[31] ;
wire \mem2_din_a[3] ;
wire \mem2_din_a[4] ;
wire \mem2_din_a[5] ;
wire \mem2_din_a[6] ;
wire \mem2_din_a[7] ;
wire \mem2_din_a[8] ;
wire \mem2_din_a[9] ;
wire \mem2_dout_a[0] ;
wire \mem2_dout_a[10] ;
wire \mem2_dout_a[11] ;
wire \mem2_dout_a[12] ;
wire \mem2_dout_a[13] ;
wire \mem2_dout_a[14] ;
wire \mem2_dout_a[15] ;
wire \mem2_dout_a[16] ;
wire \mem2_dout_a[17] ;
wire \mem2_dout_a[18] ;
wire \mem2_dout_a[19] ;
wire \mem2_dout_a[1] ;
wire \mem2_dout_a[20] ;
wire \mem2_dout_a[21] ;
wire \mem2_dout_a[22] ;
wire \mem2_dout_a[23] ;
wire \mem2_dout_a[24] ;
wire \mem2_dout_a[25] ;
wire \mem2_dout_a[26] ;
wire \mem2_dout_a[27] ;
wire \mem2_dout_a[28] ;
wire \mem2_dout_a[29] ;
wire \mem2_dout_a[2] ;
wire \mem2_dout_a[30] ;
wire \mem2_dout_a[31] ;
wire \mem2_dout_a[3] ;
wire \mem2_dout_a[4] ;
wire \mem2_dout_a[5] ;
wire \mem2_dout_a[6] ;
wire \mem2_dout_a[7] ;
wire \mem2_dout_a[8] ;
wire \mem2_dout_a[9] ;
wire \mem2_mask_a[0] ;
wire \mem2_mask_a[1] ;
wire \mem2_mask_a[2] ;
wire \mem2_mask_a[3] ;
wire \mem3_addr_a[10] ;
wire \mem3_addr_a[2] ;
wire \mem3_addr_a[3] ;
wire \mem3_addr_a[4] ;
wire \mem3_addr_a[5] ;
wire \mem3_addr_a[6] ;
wire \mem3_addr_a[7] ;
wire \mem3_addr_a[8] ;
wire \mem3_addr_a[9] ;
wire \mem3_addr_b[10] ;
wire \mem3_addr_b[2] ;
wire \mem3_addr_b[3] ;
wire \mem3_addr_b[4] ;
wire \mem3_addr_b[5] ;
wire \mem3_addr_b[6] ;
wire \mem3_addr_b[7] ;
wire \mem3_addr_b[8] ;
wire \mem3_addr_b[9] ;
wire \mem3_din_a[0] ;
wire \mem3_din_a[10] ;
wire \mem3_din_a[11] ;
wire \mem3_din_a[12] ;
wire \mem3_din_a[13] ;
wire \mem3_din_a[14] ;
wire \mem3_din_a[15] ;
wire \mem3_din_a[16] ;
wire \mem3_din_a[17] ;
wire \mem3_din_a[18] ;
wire \mem3_din_a[19] ;
wire \mem3_din_a[1] ;
wire \mem3_din_a[20] ;
wire \mem3_din_a[21] ;
wire \mem3_din_a[22] ;
wire \mem3_din_a[23] ;
wire \mem3_din_a[24] ;
wire \mem3_din_a[25] ;
wire \mem3_din_a[26] ;
wire \mem3_din_a[27] ;
wire \mem3_din_a[28] ;
wire \mem3_din_a[29] ;
wire \mem3_din_a[2] ;
wire \mem3_din_a[30] ;
wire \mem3_din_a[31] ;
wire \mem3_din_a[3] ;
wire \mem3_din_a[4] ;
wire \mem3_din_a[5] ;
wire \mem3_din_a[6] ;
wire \mem3_din_a[7] ;
wire \mem3_din_a[8] ;
wire \mem3_din_a[9] ;
wire \mem3_dout_a[0] ;
wire \mem3_dout_a[10] ;
wire \mem3_dout_a[11] ;
wire \mem3_dout_a[12] ;
wire \mem3_dout_a[13] ;
wire \mem3_dout_a[14] ;
wire \mem3_dout_a[15] ;
wire \mem3_dout_a[16] ;
wire \mem3_dout_a[17] ;
wire \mem3_dout_a[18] ;
wire \mem3_dout_a[19] ;
wire \mem3_dout_a[1] ;
wire \mem3_dout_a[20] ;
wire \mem3_dout_a[21] ;
wire \mem3_dout_a[22] ;
wire \mem3_dout_a[23] ;
wire \mem3_dout_a[24] ;
wire \mem3_dout_a[25] ;
wire \mem3_dout_a[26] ;
wire \mem3_dout_a[27] ;
wire \mem3_dout_a[28] ;
wire \mem3_dout_a[29] ;
wire \mem3_dout_a[2] ;
wire \mem3_dout_a[30] ;
wire \mem3_dout_a[31] ;
wire \mem3_dout_a[3] ;
wire \mem3_dout_a[4] ;
wire \mem3_dout_a[5] ;
wire \mem3_dout_a[6] ;
wire \mem3_dout_a[7] ;
wire \mem3_dout_a[8] ;
wire \mem3_dout_a[9] ;
wire \mem3_mask_a[0] ;
wire \mem3_mask_a[1] ;
wire \mem3_mask_a[2] ;
wire \mem3_mask_a[3] ;
wire \mem_cen_a[0] ;
wire \mem_cen_a[1] ;
wire \mem_cen_a[2] ;
wire \mem_cen_a[3] ;
wire \mem_cen_b[0] ;
wire \mem_cen_b[1] ;
wire \mem_cen_b[2] ;
wire \mem_cen_b[3] ;
wire \mem_clk_a[0] ;
wire \mem_clk_a[1] ;
wire \mem_clk_a[2] ;
wire \mem_clk_a[3] ;
wire \mem_clk_b[0] ;
wire \mem_clk_b[1] ;
wire \mem_clk_b[2] ;
wire \mem_clk_b[3] ;
wire \mem_web_a[0] ;
wire \mem_web_a[1] ;
wire \mem_web_a[2] ;
wire \mem_web_a[3] ;
wire rtc_clk;
wire sdr_init_done;
wire sdram_clk;
wire sdram_rst_n;
wire soft_irq;
wire soft_irq_rp;
wire spi_rst_n;
wire \sram0_addr0[0] ;
wire \sram0_addr0[1] ;
wire \sram0_addr0[2] ;
wire \sram0_addr0[3] ;
wire \sram0_addr0[4] ;
wire \sram0_addr0[5] ;
wire \sram0_addr0[6] ;
wire \sram0_addr0[7] ;
wire \sram0_addr0[8] ;
wire \sram0_addr1[0] ;
wire \sram0_addr1[1] ;
wire \sram0_addr1[2] ;
wire \sram0_addr1[3] ;
wire \sram0_addr1[4] ;
wire \sram0_addr1[5] ;
wire \sram0_addr1[6] ;
wire \sram0_addr1[7] ;
wire \sram0_addr1[8] ;
wire sram0_clk0;
wire sram0_clk1;
wire sram0_csb0;
wire sram0_csb1;
wire \sram0_din0[0] ;
wire \sram0_din0[10] ;
wire \sram0_din0[11] ;
wire \sram0_din0[12] ;
wire \sram0_din0[13] ;
wire \sram0_din0[14] ;
wire \sram0_din0[15] ;
wire \sram0_din0[16] ;
wire \sram0_din0[17] ;
wire \sram0_din0[18] ;
wire \sram0_din0[19] ;
wire \sram0_din0[1] ;
wire \sram0_din0[20] ;
wire \sram0_din0[21] ;
wire \sram0_din0[22] ;
wire \sram0_din0[23] ;
wire \sram0_din0[24] ;
wire \sram0_din0[25] ;
wire \sram0_din0[26] ;
wire \sram0_din0[27] ;
wire \sram0_din0[28] ;
wire \sram0_din0[29] ;
wire \sram0_din0[2] ;
wire \sram0_din0[30] ;
wire \sram0_din0[31] ;
wire \sram0_din0[3] ;
wire \sram0_din0[4] ;
wire \sram0_din0[5] ;
wire \sram0_din0[6] ;
wire \sram0_din0[7] ;
wire \sram0_din0[8] ;
wire \sram0_din0[9] ;
wire \sram0_dout0[0] ;
wire \sram0_dout0[10] ;
wire \sram0_dout0[11] ;
wire \sram0_dout0[12] ;
wire \sram0_dout0[13] ;
wire \sram0_dout0[14] ;
wire \sram0_dout0[15] ;
wire \sram0_dout0[16] ;
wire \sram0_dout0[17] ;
wire \sram0_dout0[18] ;
wire \sram0_dout0[19] ;
wire \sram0_dout0[1] ;
wire \sram0_dout0[20] ;
wire \sram0_dout0[21] ;
wire \sram0_dout0[22] ;
wire \sram0_dout0[23] ;
wire \sram0_dout0[24] ;
wire \sram0_dout0[25] ;
wire \sram0_dout0[26] ;
wire \sram0_dout0[27] ;
wire \sram0_dout0[28] ;
wire \sram0_dout0[29] ;
wire \sram0_dout0[2] ;
wire \sram0_dout0[30] ;
wire \sram0_dout0[31] ;
wire \sram0_dout0[3] ;
wire \sram0_dout0[4] ;
wire \sram0_dout0[5] ;
wire \sram0_dout0[6] ;
wire \sram0_dout0[7] ;
wire \sram0_dout0[8] ;
wire \sram0_dout0[9] ;
wire \sram0_dout1[0] ;
wire \sram0_dout1[10] ;
wire \sram0_dout1[11] ;
wire \sram0_dout1[12] ;
wire \sram0_dout1[13] ;
wire \sram0_dout1[14] ;
wire \sram0_dout1[15] ;
wire \sram0_dout1[16] ;
wire \sram0_dout1[17] ;
wire \sram0_dout1[18] ;
wire \sram0_dout1[19] ;
wire \sram0_dout1[1] ;
wire \sram0_dout1[20] ;
wire \sram0_dout1[21] ;
wire \sram0_dout1[22] ;
wire \sram0_dout1[23] ;
wire \sram0_dout1[24] ;
wire \sram0_dout1[25] ;
wire \sram0_dout1[26] ;
wire \sram0_dout1[27] ;
wire \sram0_dout1[28] ;
wire \sram0_dout1[29] ;
wire \sram0_dout1[2] ;
wire \sram0_dout1[30] ;
wire \sram0_dout1[31] ;
wire \sram0_dout1[3] ;
wire \sram0_dout1[4] ;
wire \sram0_dout1[5] ;
wire \sram0_dout1[6] ;
wire \sram0_dout1[7] ;
wire \sram0_dout1[8] ;
wire \sram0_dout1[9] ;
wire sram0_web0;
wire \sram0_wmask0[0] ;
wire \sram0_wmask0[1] ;
wire \sram0_wmask0[2] ;
wire \sram0_wmask0[3] ;
wire \sram1_addr0[0] ;
wire \sram1_addr0[1] ;
wire \sram1_addr0[2] ;
wire \sram1_addr0[3] ;
wire \sram1_addr0[4] ;
wire \sram1_addr0[5] ;
wire \sram1_addr0[6] ;
wire \sram1_addr0[7] ;
wire \sram1_addr0[8] ;
wire \sram1_addr1[0] ;
wire \sram1_addr1[1] ;
wire \sram1_addr1[2] ;
wire \sram1_addr1[3] ;
wire \sram1_addr1[4] ;
wire \sram1_addr1[5] ;
wire \sram1_addr1[6] ;
wire \sram1_addr1[7] ;
wire \sram1_addr1[8] ;
wire sram1_clk0;
wire sram1_clk1;
wire sram1_csb0;
wire sram1_csb1;
wire \sram1_din0[0] ;
wire \sram1_din0[10] ;
wire \sram1_din0[11] ;
wire \sram1_din0[12] ;
wire \sram1_din0[13] ;
wire \sram1_din0[14] ;
wire \sram1_din0[15] ;
wire \sram1_din0[16] ;
wire \sram1_din0[17] ;
wire \sram1_din0[18] ;
wire \sram1_din0[19] ;
wire \sram1_din0[1] ;
wire \sram1_din0[20] ;
wire \sram1_din0[21] ;
wire \sram1_din0[22] ;
wire \sram1_din0[23] ;
wire \sram1_din0[24] ;
wire \sram1_din0[25] ;
wire \sram1_din0[26] ;
wire \sram1_din0[27] ;
wire \sram1_din0[28] ;
wire \sram1_din0[29] ;
wire \sram1_din0[2] ;
wire \sram1_din0[30] ;
wire \sram1_din0[31] ;
wire \sram1_din0[3] ;
wire \sram1_din0[4] ;
wire \sram1_din0[5] ;
wire \sram1_din0[6] ;
wire \sram1_din0[7] ;
wire \sram1_din0[8] ;
wire \sram1_din0[9] ;
wire \sram1_dout0[0] ;
wire \sram1_dout0[10] ;
wire \sram1_dout0[11] ;
wire \sram1_dout0[12] ;
wire \sram1_dout0[13] ;
wire \sram1_dout0[14] ;
wire \sram1_dout0[15] ;
wire \sram1_dout0[16] ;
wire \sram1_dout0[17] ;
wire \sram1_dout0[18] ;
wire \sram1_dout0[19] ;
wire \sram1_dout0[1] ;
wire \sram1_dout0[20] ;
wire \sram1_dout0[21] ;
wire \sram1_dout0[22] ;
wire \sram1_dout0[23] ;
wire \sram1_dout0[24] ;
wire \sram1_dout0[25] ;
wire \sram1_dout0[26] ;
wire \sram1_dout0[27] ;
wire \sram1_dout0[28] ;
wire \sram1_dout0[29] ;
wire \sram1_dout0[2] ;
wire \sram1_dout0[30] ;
wire \sram1_dout0[31] ;
wire \sram1_dout0[3] ;
wire \sram1_dout0[4] ;
wire \sram1_dout0[5] ;
wire \sram1_dout0[6] ;
wire \sram1_dout0[7] ;
wire \sram1_dout0[8] ;
wire \sram1_dout0[9] ;
wire \sram1_dout1[0] ;
wire \sram1_dout1[10] ;
wire \sram1_dout1[11] ;
wire \sram1_dout1[12] ;
wire \sram1_dout1[13] ;
wire \sram1_dout1[14] ;
wire \sram1_dout1[15] ;
wire \sram1_dout1[16] ;
wire \sram1_dout1[17] ;
wire \sram1_dout1[18] ;
wire \sram1_dout1[19] ;
wire \sram1_dout1[1] ;
wire \sram1_dout1[20] ;
wire \sram1_dout1[21] ;
wire \sram1_dout1[22] ;
wire \sram1_dout1[23] ;
wire \sram1_dout1[24] ;
wire \sram1_dout1[25] ;
wire \sram1_dout1[26] ;
wire \sram1_dout1[27] ;
wire \sram1_dout1[28] ;
wire \sram1_dout1[29] ;
wire \sram1_dout1[2] ;
wire \sram1_dout1[30] ;
wire \sram1_dout1[31] ;
wire \sram1_dout1[3] ;
wire \sram1_dout1[4] ;
wire \sram1_dout1[5] ;
wire \sram1_dout1[6] ;
wire \sram1_dout1[7] ;
wire \sram1_dout1[8] ;
wire \sram1_dout1[9] ;
wire sram1_web0;
wire \sram1_wmask0[0] ;
wire \sram1_wmask0[1] ;
wire \sram1_wmask0[2] ;
wire \sram1_wmask0[3] ;
wire \uart_i2c_usb_sel[0] ;
wire \uart_i2c_usb_sel[1] ;
wire uart_rst_n;
wire usb_clk;
wire wbd_clk_glbl_rp;
wire wbd_clk_glbl_skew;
wire wbd_clk_int;
wire wbd_clk_mbist_rp;
wire wbd_clk_mbist_skew;
wire wbd_clk_riscv;
wire wbd_clk_riscv_rp;
wire wbd_clk_sdram_skew;
wire wbd_clk_sdrc_rp;
wire wbd_clk_spi_skew;
wire wbd_clk_spim_rp;
wire wbd_clk_uart_rp;
wire wbd_clk_uart_skew;
wire wbd_clk_wh;
wire wbd_clk_wi_skew;
wire wbd_glbl_ack_i;
wire \wbd_glbl_adr_o[0] ;
wire \wbd_glbl_adr_o[1] ;
wire \wbd_glbl_adr_o[2] ;
wire \wbd_glbl_adr_o[3] ;
wire \wbd_glbl_adr_o[4] ;
wire \wbd_glbl_adr_o[5] ;
wire \wbd_glbl_adr_o[6] ;
wire \wbd_glbl_adr_o[7] ;
wire wbd_glbl_cyc_o;
wire \wbd_glbl_dat_i[0] ;
wire \wbd_glbl_dat_i[10] ;
wire \wbd_glbl_dat_i[11] ;
wire \wbd_glbl_dat_i[12] ;
wire \wbd_glbl_dat_i[13] ;
wire \wbd_glbl_dat_i[14] ;
wire \wbd_glbl_dat_i[15] ;
wire \wbd_glbl_dat_i[16] ;
wire \wbd_glbl_dat_i[17] ;
wire \wbd_glbl_dat_i[18] ;
wire \wbd_glbl_dat_i[19] ;
wire \wbd_glbl_dat_i[1] ;
wire \wbd_glbl_dat_i[20] ;
wire \wbd_glbl_dat_i[21] ;
wire \wbd_glbl_dat_i[22] ;
wire \wbd_glbl_dat_i[23] ;
wire \wbd_glbl_dat_i[24] ;
wire \wbd_glbl_dat_i[25] ;
wire \wbd_glbl_dat_i[26] ;
wire \wbd_glbl_dat_i[27] ;
wire \wbd_glbl_dat_i[28] ;
wire \wbd_glbl_dat_i[29] ;
wire \wbd_glbl_dat_i[2] ;
wire \wbd_glbl_dat_i[30] ;
wire \wbd_glbl_dat_i[31] ;
wire \wbd_glbl_dat_i[3] ;
wire \wbd_glbl_dat_i[4] ;
wire \wbd_glbl_dat_i[5] ;
wire \wbd_glbl_dat_i[6] ;
wire \wbd_glbl_dat_i[7] ;
wire \wbd_glbl_dat_i[8] ;
wire \wbd_glbl_dat_i[9] ;
wire \wbd_glbl_dat_o[0] ;
wire \wbd_glbl_dat_o[10] ;
wire \wbd_glbl_dat_o[11] ;
wire \wbd_glbl_dat_o[12] ;
wire \wbd_glbl_dat_o[13] ;
wire \wbd_glbl_dat_o[14] ;
wire \wbd_glbl_dat_o[15] ;
wire \wbd_glbl_dat_o[16] ;
wire \wbd_glbl_dat_o[17] ;
wire \wbd_glbl_dat_o[18] ;
wire \wbd_glbl_dat_o[19] ;
wire \wbd_glbl_dat_o[1] ;
wire \wbd_glbl_dat_o[20] ;
wire \wbd_glbl_dat_o[21] ;
wire \wbd_glbl_dat_o[22] ;
wire \wbd_glbl_dat_o[23] ;
wire \wbd_glbl_dat_o[24] ;
wire \wbd_glbl_dat_o[25] ;
wire \wbd_glbl_dat_o[26] ;
wire \wbd_glbl_dat_o[27] ;
wire \wbd_glbl_dat_o[28] ;
wire \wbd_glbl_dat_o[29] ;
wire \wbd_glbl_dat_o[2] ;
wire \wbd_glbl_dat_o[30] ;
wire \wbd_glbl_dat_o[31] ;
wire \wbd_glbl_dat_o[3] ;
wire \wbd_glbl_dat_o[4] ;
wire \wbd_glbl_dat_o[5] ;
wire \wbd_glbl_dat_o[6] ;
wire \wbd_glbl_dat_o[7] ;
wire \wbd_glbl_dat_o[8] ;
wire \wbd_glbl_dat_o[9] ;
wire \wbd_glbl_sel_o[0] ;
wire \wbd_glbl_sel_o[1] ;
wire \wbd_glbl_sel_o[2] ;
wire \wbd_glbl_sel_o[3] ;
wire wbd_glbl_stb_o;
wire wbd_glbl_we_o;
wire wbd_int_ack_o;
wire \wbd_int_adr_i[0] ;
wire \wbd_int_adr_i[10] ;
wire \wbd_int_adr_i[11] ;
wire \wbd_int_adr_i[12] ;
wire \wbd_int_adr_i[13] ;
wire \wbd_int_adr_i[14] ;
wire \wbd_int_adr_i[15] ;
wire \wbd_int_adr_i[16] ;
wire \wbd_int_adr_i[17] ;
wire \wbd_int_adr_i[18] ;
wire \wbd_int_adr_i[19] ;
wire \wbd_int_adr_i[1] ;
wire \wbd_int_adr_i[20] ;
wire \wbd_int_adr_i[21] ;
wire \wbd_int_adr_i[22] ;
wire \wbd_int_adr_i[23] ;
wire \wbd_int_adr_i[24] ;
wire \wbd_int_adr_i[25] ;
wire \wbd_int_adr_i[26] ;
wire \wbd_int_adr_i[27] ;
wire \wbd_int_adr_i[28] ;
wire \wbd_int_adr_i[29] ;
wire \wbd_int_adr_i[2] ;
wire \wbd_int_adr_i[30] ;
wire \wbd_int_adr_i[31] ;
wire \wbd_int_adr_i[3] ;
wire \wbd_int_adr_i[4] ;
wire \wbd_int_adr_i[5] ;
wire \wbd_int_adr_i[6] ;
wire \wbd_int_adr_i[7] ;
wire \wbd_int_adr_i[8] ;
wire \wbd_int_adr_i[9] ;
wire wbd_int_cyc_i;
wire \wbd_int_dat_i[0] ;
wire \wbd_int_dat_i[10] ;
wire \wbd_int_dat_i[11] ;
wire \wbd_int_dat_i[12] ;
wire \wbd_int_dat_i[13] ;
wire \wbd_int_dat_i[14] ;
wire \wbd_int_dat_i[15] ;
wire \wbd_int_dat_i[16] ;
wire \wbd_int_dat_i[17] ;
wire \wbd_int_dat_i[18] ;
wire \wbd_int_dat_i[19] ;
wire \wbd_int_dat_i[1] ;
wire \wbd_int_dat_i[20] ;
wire \wbd_int_dat_i[21] ;
wire \wbd_int_dat_i[22] ;
wire \wbd_int_dat_i[23] ;
wire \wbd_int_dat_i[24] ;
wire \wbd_int_dat_i[25] ;
wire \wbd_int_dat_i[26] ;
wire \wbd_int_dat_i[27] ;
wire \wbd_int_dat_i[28] ;
wire \wbd_int_dat_i[29] ;
wire \wbd_int_dat_i[2] ;
wire \wbd_int_dat_i[30] ;
wire \wbd_int_dat_i[31] ;
wire \wbd_int_dat_i[3] ;
wire \wbd_int_dat_i[4] ;
wire \wbd_int_dat_i[5] ;
wire \wbd_int_dat_i[6] ;
wire \wbd_int_dat_i[7] ;
wire \wbd_int_dat_i[8] ;
wire \wbd_int_dat_i[9] ;
wire \wbd_int_dat_o[0] ;
wire \wbd_int_dat_o[10] ;
wire \wbd_int_dat_o[11] ;
wire \wbd_int_dat_o[12] ;
wire \wbd_int_dat_o[13] ;
wire \wbd_int_dat_o[14] ;
wire \wbd_int_dat_o[15] ;
wire \wbd_int_dat_o[16] ;
wire \wbd_int_dat_o[17] ;
wire \wbd_int_dat_o[18] ;
wire \wbd_int_dat_o[19] ;
wire \wbd_int_dat_o[1] ;
wire \wbd_int_dat_o[20] ;
wire \wbd_int_dat_o[21] ;
wire \wbd_int_dat_o[22] ;
wire \wbd_int_dat_o[23] ;
wire \wbd_int_dat_o[24] ;
wire \wbd_int_dat_o[25] ;
wire \wbd_int_dat_o[26] ;
wire \wbd_int_dat_o[27] ;
wire \wbd_int_dat_o[28] ;
wire \wbd_int_dat_o[29] ;
wire \wbd_int_dat_o[2] ;
wire \wbd_int_dat_o[30] ;
wire \wbd_int_dat_o[31] ;
wire \wbd_int_dat_o[3] ;
wire \wbd_int_dat_o[4] ;
wire \wbd_int_dat_o[5] ;
wire \wbd_int_dat_o[6] ;
wire \wbd_int_dat_o[7] ;
wire \wbd_int_dat_o[8] ;
wire \wbd_int_dat_o[9] ;
wire wbd_int_err_o;
wire wbd_int_rst_n;
wire \wbd_int_sel_i[0] ;
wire \wbd_int_sel_i[1] ;
wire \wbd_int_sel_i[2] ;
wire \wbd_int_sel_i[3] ;
wire wbd_int_stb_i;
wire wbd_int_we_i;
wire wbd_mbist_ack_i;
wire \wbd_mbist_adr_o[0] ;
wire \wbd_mbist_adr_o[10] ;
wire \wbd_mbist_adr_o[11] ;
wire \wbd_mbist_adr_o[12] ;
wire \wbd_mbist_adr_o[1] ;
wire \wbd_mbist_adr_o[2] ;
wire \wbd_mbist_adr_o[3] ;
wire \wbd_mbist_adr_o[4] ;
wire \wbd_mbist_adr_o[5] ;
wire \wbd_mbist_adr_o[6] ;
wire \wbd_mbist_adr_o[7] ;
wire \wbd_mbist_adr_o[8] ;
wire \wbd_mbist_adr_o[9] ;
wire wbd_mbist_cyc_o;
wire \wbd_mbist_dat_i[0] ;
wire \wbd_mbist_dat_i[10] ;
wire \wbd_mbist_dat_i[11] ;
wire \wbd_mbist_dat_i[12] ;
wire \wbd_mbist_dat_i[13] ;
wire \wbd_mbist_dat_i[14] ;
wire \wbd_mbist_dat_i[15] ;
wire \wbd_mbist_dat_i[16] ;
wire \wbd_mbist_dat_i[17] ;
wire \wbd_mbist_dat_i[18] ;
wire \wbd_mbist_dat_i[19] ;
wire \wbd_mbist_dat_i[1] ;
wire \wbd_mbist_dat_i[20] ;
wire \wbd_mbist_dat_i[21] ;
wire \wbd_mbist_dat_i[22] ;
wire \wbd_mbist_dat_i[23] ;
wire \wbd_mbist_dat_i[24] ;
wire \wbd_mbist_dat_i[25] ;
wire \wbd_mbist_dat_i[26] ;
wire \wbd_mbist_dat_i[27] ;
wire \wbd_mbist_dat_i[28] ;
wire \wbd_mbist_dat_i[29] ;
wire \wbd_mbist_dat_i[2] ;
wire \wbd_mbist_dat_i[30] ;
wire \wbd_mbist_dat_i[31] ;
wire \wbd_mbist_dat_i[3] ;
wire \wbd_mbist_dat_i[4] ;
wire \wbd_mbist_dat_i[5] ;
wire \wbd_mbist_dat_i[6] ;
wire \wbd_mbist_dat_i[7] ;
wire \wbd_mbist_dat_i[8] ;
wire \wbd_mbist_dat_i[9] ;
wire \wbd_mbist_dat_o[0] ;
wire \wbd_mbist_dat_o[10] ;
wire \wbd_mbist_dat_o[11] ;
wire \wbd_mbist_dat_o[12] ;
wire \wbd_mbist_dat_o[13] ;
wire \wbd_mbist_dat_o[14] ;
wire \wbd_mbist_dat_o[15] ;
wire \wbd_mbist_dat_o[16] ;
wire \wbd_mbist_dat_o[17] ;
wire \wbd_mbist_dat_o[18] ;
wire \wbd_mbist_dat_o[19] ;
wire \wbd_mbist_dat_o[1] ;
wire \wbd_mbist_dat_o[20] ;
wire \wbd_mbist_dat_o[21] ;
wire \wbd_mbist_dat_o[22] ;
wire \wbd_mbist_dat_o[23] ;
wire \wbd_mbist_dat_o[24] ;
wire \wbd_mbist_dat_o[25] ;
wire \wbd_mbist_dat_o[26] ;
wire \wbd_mbist_dat_o[27] ;
wire \wbd_mbist_dat_o[28] ;
wire \wbd_mbist_dat_o[29] ;
wire \wbd_mbist_dat_o[2] ;
wire \wbd_mbist_dat_o[30] ;
wire \wbd_mbist_dat_o[31] ;
wire \wbd_mbist_dat_o[3] ;
wire \wbd_mbist_dat_o[4] ;
wire \wbd_mbist_dat_o[5] ;
wire \wbd_mbist_dat_o[6] ;
wire \wbd_mbist_dat_o[7] ;
wire \wbd_mbist_dat_o[8] ;
wire \wbd_mbist_dat_o[9] ;
wire \wbd_mbist_sel_o[0] ;
wire \wbd_mbist_sel_o[1] ;
wire \wbd_mbist_sel_o[2] ;
wire \wbd_mbist_sel_o[3] ;
wire wbd_mbist_stb_o;
wire wbd_mbist_we_o;
wire wbd_riscv_dmem_ack_o;
wire \wbd_riscv_dmem_adr_i[0] ;
wire \wbd_riscv_dmem_adr_i[10] ;
wire \wbd_riscv_dmem_adr_i[11] ;
wire \wbd_riscv_dmem_adr_i[12] ;
wire \wbd_riscv_dmem_adr_i[13] ;
wire \wbd_riscv_dmem_adr_i[14] ;
wire \wbd_riscv_dmem_adr_i[15] ;
wire \wbd_riscv_dmem_adr_i[16] ;
wire \wbd_riscv_dmem_adr_i[17] ;
wire \wbd_riscv_dmem_adr_i[18] ;
wire \wbd_riscv_dmem_adr_i[19] ;
wire \wbd_riscv_dmem_adr_i[1] ;
wire \wbd_riscv_dmem_adr_i[20] ;
wire \wbd_riscv_dmem_adr_i[21] ;
wire \wbd_riscv_dmem_adr_i[22] ;
wire \wbd_riscv_dmem_adr_i[23] ;
wire \wbd_riscv_dmem_adr_i[24] ;
wire \wbd_riscv_dmem_adr_i[25] ;
wire \wbd_riscv_dmem_adr_i[26] ;
wire \wbd_riscv_dmem_adr_i[27] ;
wire \wbd_riscv_dmem_adr_i[28] ;
wire \wbd_riscv_dmem_adr_i[29] ;
wire \wbd_riscv_dmem_adr_i[2] ;
wire \wbd_riscv_dmem_adr_i[30] ;
wire \wbd_riscv_dmem_adr_i[31] ;
wire \wbd_riscv_dmem_adr_i[3] ;
wire \wbd_riscv_dmem_adr_i[4] ;
wire \wbd_riscv_dmem_adr_i[5] ;
wire \wbd_riscv_dmem_adr_i[6] ;
wire \wbd_riscv_dmem_adr_i[7] ;
wire \wbd_riscv_dmem_adr_i[8] ;
wire \wbd_riscv_dmem_adr_i[9] ;
wire \wbd_riscv_dmem_dat_i[0] ;
wire \wbd_riscv_dmem_dat_i[10] ;
wire \wbd_riscv_dmem_dat_i[11] ;
wire \wbd_riscv_dmem_dat_i[12] ;
wire \wbd_riscv_dmem_dat_i[13] ;
wire \wbd_riscv_dmem_dat_i[14] ;
wire \wbd_riscv_dmem_dat_i[15] ;
wire \wbd_riscv_dmem_dat_i[16] ;
wire \wbd_riscv_dmem_dat_i[17] ;
wire \wbd_riscv_dmem_dat_i[18] ;
wire \wbd_riscv_dmem_dat_i[19] ;
wire \wbd_riscv_dmem_dat_i[1] ;
wire \wbd_riscv_dmem_dat_i[20] ;
wire \wbd_riscv_dmem_dat_i[21] ;
wire \wbd_riscv_dmem_dat_i[22] ;
wire \wbd_riscv_dmem_dat_i[23] ;
wire \wbd_riscv_dmem_dat_i[24] ;
wire \wbd_riscv_dmem_dat_i[25] ;
wire \wbd_riscv_dmem_dat_i[26] ;
wire \wbd_riscv_dmem_dat_i[27] ;
wire \wbd_riscv_dmem_dat_i[28] ;
wire \wbd_riscv_dmem_dat_i[29] ;
wire \wbd_riscv_dmem_dat_i[2] ;
wire \wbd_riscv_dmem_dat_i[30] ;
wire \wbd_riscv_dmem_dat_i[31] ;
wire \wbd_riscv_dmem_dat_i[3] ;
wire \wbd_riscv_dmem_dat_i[4] ;
wire \wbd_riscv_dmem_dat_i[5] ;
wire \wbd_riscv_dmem_dat_i[6] ;
wire \wbd_riscv_dmem_dat_i[7] ;
wire \wbd_riscv_dmem_dat_i[8] ;
wire \wbd_riscv_dmem_dat_i[9] ;
wire \wbd_riscv_dmem_dat_o[0] ;
wire \wbd_riscv_dmem_dat_o[10] ;
wire \wbd_riscv_dmem_dat_o[11] ;
wire \wbd_riscv_dmem_dat_o[12] ;
wire \wbd_riscv_dmem_dat_o[13] ;
wire \wbd_riscv_dmem_dat_o[14] ;
wire \wbd_riscv_dmem_dat_o[15] ;
wire \wbd_riscv_dmem_dat_o[16] ;
wire \wbd_riscv_dmem_dat_o[17] ;
wire \wbd_riscv_dmem_dat_o[18] ;
wire \wbd_riscv_dmem_dat_o[19] ;
wire \wbd_riscv_dmem_dat_o[1] ;
wire \wbd_riscv_dmem_dat_o[20] ;
wire \wbd_riscv_dmem_dat_o[21] ;
wire \wbd_riscv_dmem_dat_o[22] ;
wire \wbd_riscv_dmem_dat_o[23] ;
wire \wbd_riscv_dmem_dat_o[24] ;
wire \wbd_riscv_dmem_dat_o[25] ;
wire \wbd_riscv_dmem_dat_o[26] ;
wire \wbd_riscv_dmem_dat_o[27] ;
wire \wbd_riscv_dmem_dat_o[28] ;
wire \wbd_riscv_dmem_dat_o[29] ;
wire \wbd_riscv_dmem_dat_o[2] ;
wire \wbd_riscv_dmem_dat_o[30] ;
wire \wbd_riscv_dmem_dat_o[31] ;
wire \wbd_riscv_dmem_dat_o[3] ;
wire \wbd_riscv_dmem_dat_o[4] ;
wire \wbd_riscv_dmem_dat_o[5] ;
wire \wbd_riscv_dmem_dat_o[6] ;
wire \wbd_riscv_dmem_dat_o[7] ;
wire \wbd_riscv_dmem_dat_o[8] ;
wire \wbd_riscv_dmem_dat_o[9] ;
wire wbd_riscv_dmem_err_o;
wire \wbd_riscv_dmem_sel_i[0] ;
wire \wbd_riscv_dmem_sel_i[1] ;
wire \wbd_riscv_dmem_sel_i[2] ;
wire \wbd_riscv_dmem_sel_i[3] ;
wire wbd_riscv_dmem_stb_i;
wire wbd_riscv_dmem_we_i;
wire wbd_riscv_imem_ack_o;
wire \wbd_riscv_imem_adr_i[0] ;
wire \wbd_riscv_imem_adr_i[10] ;
wire \wbd_riscv_imem_adr_i[11] ;
wire \wbd_riscv_imem_adr_i[12] ;
wire \wbd_riscv_imem_adr_i[13] ;
wire \wbd_riscv_imem_adr_i[14] ;
wire \wbd_riscv_imem_adr_i[15] ;
wire \wbd_riscv_imem_adr_i[16] ;
wire \wbd_riscv_imem_adr_i[17] ;
wire \wbd_riscv_imem_adr_i[18] ;
wire \wbd_riscv_imem_adr_i[19] ;
wire \wbd_riscv_imem_adr_i[1] ;
wire \wbd_riscv_imem_adr_i[20] ;
wire \wbd_riscv_imem_adr_i[21] ;
wire \wbd_riscv_imem_adr_i[22] ;
wire \wbd_riscv_imem_adr_i[23] ;
wire \wbd_riscv_imem_adr_i[24] ;
wire \wbd_riscv_imem_adr_i[25] ;
wire \wbd_riscv_imem_adr_i[26] ;
wire \wbd_riscv_imem_adr_i[27] ;
wire \wbd_riscv_imem_adr_i[28] ;
wire \wbd_riscv_imem_adr_i[29] ;
wire \wbd_riscv_imem_adr_i[2] ;
wire \wbd_riscv_imem_adr_i[30] ;
wire \wbd_riscv_imem_adr_i[31] ;
wire \wbd_riscv_imem_adr_i[3] ;
wire \wbd_riscv_imem_adr_i[4] ;
wire \wbd_riscv_imem_adr_i[5] ;
wire \wbd_riscv_imem_adr_i[6] ;
wire \wbd_riscv_imem_adr_i[7] ;
wire \wbd_riscv_imem_adr_i[8] ;
wire \wbd_riscv_imem_adr_i[9] ;
wire \wbd_riscv_imem_dat_i[0] ;
wire \wbd_riscv_imem_dat_i[10] ;
wire \wbd_riscv_imem_dat_i[11] ;
wire \wbd_riscv_imem_dat_i[12] ;
wire \wbd_riscv_imem_dat_i[13] ;
wire \wbd_riscv_imem_dat_i[14] ;
wire \wbd_riscv_imem_dat_i[15] ;
wire \wbd_riscv_imem_dat_i[16] ;
wire \wbd_riscv_imem_dat_i[17] ;
wire \wbd_riscv_imem_dat_i[18] ;
wire \wbd_riscv_imem_dat_i[19] ;
wire \wbd_riscv_imem_dat_i[1] ;
wire \wbd_riscv_imem_dat_i[20] ;
wire \wbd_riscv_imem_dat_i[21] ;
wire \wbd_riscv_imem_dat_i[22] ;
wire \wbd_riscv_imem_dat_i[23] ;
wire \wbd_riscv_imem_dat_i[24] ;
wire \wbd_riscv_imem_dat_i[25] ;
wire \wbd_riscv_imem_dat_i[26] ;
wire \wbd_riscv_imem_dat_i[27] ;
wire \wbd_riscv_imem_dat_i[28] ;
wire \wbd_riscv_imem_dat_i[29] ;
wire \wbd_riscv_imem_dat_i[2] ;
wire \wbd_riscv_imem_dat_i[30] ;
wire \wbd_riscv_imem_dat_i[31] ;
wire \wbd_riscv_imem_dat_i[3] ;
wire \wbd_riscv_imem_dat_i[4] ;
wire \wbd_riscv_imem_dat_i[5] ;
wire \wbd_riscv_imem_dat_i[6] ;
wire \wbd_riscv_imem_dat_i[7] ;
wire \wbd_riscv_imem_dat_i[8] ;
wire \wbd_riscv_imem_dat_i[9] ;
wire \wbd_riscv_imem_dat_o[0] ;
wire \wbd_riscv_imem_dat_o[10] ;
wire \wbd_riscv_imem_dat_o[11] ;
wire \wbd_riscv_imem_dat_o[12] ;
wire \wbd_riscv_imem_dat_o[13] ;
wire \wbd_riscv_imem_dat_o[14] ;
wire \wbd_riscv_imem_dat_o[15] ;
wire \wbd_riscv_imem_dat_o[16] ;
wire \wbd_riscv_imem_dat_o[17] ;
wire \wbd_riscv_imem_dat_o[18] ;
wire \wbd_riscv_imem_dat_o[19] ;
wire \wbd_riscv_imem_dat_o[1] ;
wire \wbd_riscv_imem_dat_o[20] ;
wire \wbd_riscv_imem_dat_o[21] ;
wire \wbd_riscv_imem_dat_o[22] ;
wire \wbd_riscv_imem_dat_o[23] ;
wire \wbd_riscv_imem_dat_o[24] ;
wire \wbd_riscv_imem_dat_o[25] ;
wire \wbd_riscv_imem_dat_o[26] ;
wire \wbd_riscv_imem_dat_o[27] ;
wire \wbd_riscv_imem_dat_o[28] ;
wire \wbd_riscv_imem_dat_o[29] ;
wire \wbd_riscv_imem_dat_o[2] ;
wire \wbd_riscv_imem_dat_o[30] ;
wire \wbd_riscv_imem_dat_o[31] ;
wire \wbd_riscv_imem_dat_o[3] ;
wire \wbd_riscv_imem_dat_o[4] ;
wire \wbd_riscv_imem_dat_o[5] ;
wire \wbd_riscv_imem_dat_o[6] ;
wire \wbd_riscv_imem_dat_o[7] ;
wire \wbd_riscv_imem_dat_o[8] ;
wire \wbd_riscv_imem_dat_o[9] ;
wire wbd_riscv_imem_err_o;
wire \wbd_riscv_imem_sel_i[0] ;
wire \wbd_riscv_imem_sel_i[1] ;
wire \wbd_riscv_imem_sel_i[2] ;
wire \wbd_riscv_imem_sel_i[3] ;
wire wbd_riscv_imem_stb_i;
wire wbd_riscv_imem_we_i;
wire wbd_sdram_ack_i;
wire \wbd_sdram_adr_o[0] ;
wire \wbd_sdram_adr_o[10] ;
wire \wbd_sdram_adr_o[11] ;
wire \wbd_sdram_adr_o[12] ;
wire \wbd_sdram_adr_o[13] ;
wire \wbd_sdram_adr_o[14] ;
wire \wbd_sdram_adr_o[15] ;
wire \wbd_sdram_adr_o[16] ;
wire \wbd_sdram_adr_o[17] ;
wire \wbd_sdram_adr_o[18] ;
wire \wbd_sdram_adr_o[19] ;
wire \wbd_sdram_adr_o[1] ;
wire \wbd_sdram_adr_o[20] ;
wire \wbd_sdram_adr_o[21] ;
wire \wbd_sdram_adr_o[22] ;
wire \wbd_sdram_adr_o[23] ;
wire \wbd_sdram_adr_o[24] ;
wire \wbd_sdram_adr_o[25] ;
wire \wbd_sdram_adr_o[26] ;
wire \wbd_sdram_adr_o[27] ;
wire \wbd_sdram_adr_o[28] ;
wire \wbd_sdram_adr_o[29] ;
wire \wbd_sdram_adr_o[2] ;
wire \wbd_sdram_adr_o[30] ;
wire \wbd_sdram_adr_o[31] ;
wire \wbd_sdram_adr_o[3] ;
wire \wbd_sdram_adr_o[4] ;
wire \wbd_sdram_adr_o[5] ;
wire \wbd_sdram_adr_o[6] ;
wire \wbd_sdram_adr_o[7] ;
wire \wbd_sdram_adr_o[8] ;
wire \wbd_sdram_adr_o[9] ;
wire wbd_sdram_cyc_o;
wire \wbd_sdram_dat_i[0] ;
wire \wbd_sdram_dat_i[10] ;
wire \wbd_sdram_dat_i[11] ;
wire \wbd_sdram_dat_i[12] ;
wire \wbd_sdram_dat_i[13] ;
wire \wbd_sdram_dat_i[14] ;
wire \wbd_sdram_dat_i[15] ;
wire \wbd_sdram_dat_i[16] ;
wire \wbd_sdram_dat_i[17] ;
wire \wbd_sdram_dat_i[18] ;
wire \wbd_sdram_dat_i[19] ;
wire \wbd_sdram_dat_i[1] ;
wire \wbd_sdram_dat_i[20] ;
wire \wbd_sdram_dat_i[21] ;
wire \wbd_sdram_dat_i[22] ;
wire \wbd_sdram_dat_i[23] ;
wire \wbd_sdram_dat_i[24] ;
wire \wbd_sdram_dat_i[25] ;
wire \wbd_sdram_dat_i[26] ;
wire \wbd_sdram_dat_i[27] ;
wire \wbd_sdram_dat_i[28] ;
wire \wbd_sdram_dat_i[29] ;
wire \wbd_sdram_dat_i[2] ;
wire \wbd_sdram_dat_i[30] ;
wire \wbd_sdram_dat_i[31] ;
wire \wbd_sdram_dat_i[3] ;
wire \wbd_sdram_dat_i[4] ;
wire \wbd_sdram_dat_i[5] ;
wire \wbd_sdram_dat_i[6] ;
wire \wbd_sdram_dat_i[7] ;
wire \wbd_sdram_dat_i[8] ;
wire \wbd_sdram_dat_i[9] ;
wire \wbd_sdram_dat_o[0] ;
wire \wbd_sdram_dat_o[10] ;
wire \wbd_sdram_dat_o[11] ;
wire \wbd_sdram_dat_o[12] ;
wire \wbd_sdram_dat_o[13] ;
wire \wbd_sdram_dat_o[14] ;
wire \wbd_sdram_dat_o[15] ;
wire \wbd_sdram_dat_o[16] ;
wire \wbd_sdram_dat_o[17] ;
wire \wbd_sdram_dat_o[18] ;
wire \wbd_sdram_dat_o[19] ;
wire \wbd_sdram_dat_o[1] ;
wire \wbd_sdram_dat_o[20] ;
wire \wbd_sdram_dat_o[21] ;
wire \wbd_sdram_dat_o[22] ;
wire \wbd_sdram_dat_o[23] ;
wire \wbd_sdram_dat_o[24] ;
wire \wbd_sdram_dat_o[25] ;
wire \wbd_sdram_dat_o[26] ;
wire \wbd_sdram_dat_o[27] ;
wire \wbd_sdram_dat_o[28] ;
wire \wbd_sdram_dat_o[29] ;
wire \wbd_sdram_dat_o[2] ;
wire \wbd_sdram_dat_o[30] ;
wire \wbd_sdram_dat_o[31] ;
wire \wbd_sdram_dat_o[3] ;
wire \wbd_sdram_dat_o[4] ;
wire \wbd_sdram_dat_o[5] ;
wire \wbd_sdram_dat_o[6] ;
wire \wbd_sdram_dat_o[7] ;
wire \wbd_sdram_dat_o[8] ;
wire \wbd_sdram_dat_o[9] ;
wire \wbd_sdram_sel_o[0] ;
wire \wbd_sdram_sel_o[1] ;
wire \wbd_sdram_sel_o[2] ;
wire \wbd_sdram_sel_o[3] ;
wire wbd_sdram_stb_o;
wire wbd_sdram_we_o;
wire wbd_spim_ack_i;
wire \wbd_spim_adr_o[0] ;
wire \wbd_spim_adr_o[10] ;
wire \wbd_spim_adr_o[11] ;
wire \wbd_spim_adr_o[12] ;
wire \wbd_spim_adr_o[13] ;
wire \wbd_spim_adr_o[14] ;
wire \wbd_spim_adr_o[15] ;
wire \wbd_spim_adr_o[16] ;
wire \wbd_spim_adr_o[17] ;
wire \wbd_spim_adr_o[18] ;
wire \wbd_spim_adr_o[19] ;
wire \wbd_spim_adr_o[1] ;
wire \wbd_spim_adr_o[20] ;
wire \wbd_spim_adr_o[21] ;
wire \wbd_spim_adr_o[22] ;
wire \wbd_spim_adr_o[23] ;
wire \wbd_spim_adr_o[24] ;
wire \wbd_spim_adr_o[25] ;
wire \wbd_spim_adr_o[26] ;
wire \wbd_spim_adr_o[27] ;
wire \wbd_spim_adr_o[28] ;
wire \wbd_spim_adr_o[29] ;
wire \wbd_spim_adr_o[2] ;
wire \wbd_spim_adr_o[30] ;
wire \wbd_spim_adr_o[31] ;
wire \wbd_spim_adr_o[3] ;
wire \wbd_spim_adr_o[4] ;
wire \wbd_spim_adr_o[5] ;
wire \wbd_spim_adr_o[6] ;
wire \wbd_spim_adr_o[7] ;
wire \wbd_spim_adr_o[8] ;
wire \wbd_spim_adr_o[9] ;
wire wbd_spim_cyc_o;
wire \wbd_spim_dat_i[0] ;
wire \wbd_spim_dat_i[10] ;
wire \wbd_spim_dat_i[11] ;
wire \wbd_spim_dat_i[12] ;
wire \wbd_spim_dat_i[13] ;
wire \wbd_spim_dat_i[14] ;
wire \wbd_spim_dat_i[15] ;
wire \wbd_spim_dat_i[16] ;
wire \wbd_spim_dat_i[17] ;
wire \wbd_spim_dat_i[18] ;
wire \wbd_spim_dat_i[19] ;
wire \wbd_spim_dat_i[1] ;
wire \wbd_spim_dat_i[20] ;
wire \wbd_spim_dat_i[21] ;
wire \wbd_spim_dat_i[22] ;
wire \wbd_spim_dat_i[23] ;
wire \wbd_spim_dat_i[24] ;
wire \wbd_spim_dat_i[25] ;
wire \wbd_spim_dat_i[26] ;
wire \wbd_spim_dat_i[27] ;
wire \wbd_spim_dat_i[28] ;
wire \wbd_spim_dat_i[29] ;
wire \wbd_spim_dat_i[2] ;
wire \wbd_spim_dat_i[30] ;
wire \wbd_spim_dat_i[31] ;
wire \wbd_spim_dat_i[3] ;
wire \wbd_spim_dat_i[4] ;
wire \wbd_spim_dat_i[5] ;
wire \wbd_spim_dat_i[6] ;
wire \wbd_spim_dat_i[7] ;
wire \wbd_spim_dat_i[8] ;
wire \wbd_spim_dat_i[9] ;
wire \wbd_spim_dat_o[0] ;
wire \wbd_spim_dat_o[10] ;
wire \wbd_spim_dat_o[11] ;
wire \wbd_spim_dat_o[12] ;
wire \wbd_spim_dat_o[13] ;
wire \wbd_spim_dat_o[14] ;
wire \wbd_spim_dat_o[15] ;
wire \wbd_spim_dat_o[16] ;
wire \wbd_spim_dat_o[17] ;
wire \wbd_spim_dat_o[18] ;
wire \wbd_spim_dat_o[19] ;
wire \wbd_spim_dat_o[1] ;
wire \wbd_spim_dat_o[20] ;
wire \wbd_spim_dat_o[21] ;
wire \wbd_spim_dat_o[22] ;
wire \wbd_spim_dat_o[23] ;
wire \wbd_spim_dat_o[24] ;
wire \wbd_spim_dat_o[25] ;
wire \wbd_spim_dat_o[26] ;
wire \wbd_spim_dat_o[27] ;
wire \wbd_spim_dat_o[28] ;
wire \wbd_spim_dat_o[29] ;
wire \wbd_spim_dat_o[2] ;
wire \wbd_spim_dat_o[30] ;
wire \wbd_spim_dat_o[31] ;
wire \wbd_spim_dat_o[3] ;
wire \wbd_spim_dat_o[4] ;
wire \wbd_spim_dat_o[5] ;
wire \wbd_spim_dat_o[6] ;
wire \wbd_spim_dat_o[7] ;
wire \wbd_spim_dat_o[8] ;
wire \wbd_spim_dat_o[9] ;
wire wbd_spim_err_i;
wire \wbd_spim_sel_o[0] ;
wire \wbd_spim_sel_o[1] ;
wire \wbd_spim_sel_o[2] ;
wire \wbd_spim_sel_o[3] ;
wire wbd_spim_stb_o;
wire wbd_spim_we_o;
wire wbd_uart_ack_i;
wire \wbd_uart_adr_o[0] ;
wire \wbd_uart_adr_o[1] ;
wire \wbd_uart_adr_o[2] ;
wire \wbd_uart_adr_o[3] ;
wire \wbd_uart_adr_o[4] ;
wire \wbd_uart_adr_o[5] ;
wire \wbd_uart_adr_o[6] ;
wire \wbd_uart_adr_o[7] ;
wire wbd_uart_cyc_o;
wire \wbd_uart_dat_i[0] ;
wire \wbd_uart_dat_i[10] ;
wire \wbd_uart_dat_i[11] ;
wire \wbd_uart_dat_i[12] ;
wire \wbd_uart_dat_i[13] ;
wire \wbd_uart_dat_i[14] ;
wire \wbd_uart_dat_i[15] ;
wire \wbd_uart_dat_i[16] ;
wire \wbd_uart_dat_i[17] ;
wire \wbd_uart_dat_i[18] ;
wire \wbd_uart_dat_i[19] ;
wire \wbd_uart_dat_i[1] ;
wire \wbd_uart_dat_i[20] ;
wire \wbd_uart_dat_i[21] ;
wire \wbd_uart_dat_i[22] ;
wire \wbd_uart_dat_i[23] ;
wire \wbd_uart_dat_i[24] ;
wire \wbd_uart_dat_i[25] ;
wire \wbd_uart_dat_i[26] ;
wire \wbd_uart_dat_i[27] ;
wire \wbd_uart_dat_i[28] ;
wire \wbd_uart_dat_i[29] ;
wire \wbd_uart_dat_i[2] ;
wire \wbd_uart_dat_i[30] ;
wire \wbd_uart_dat_i[31] ;
wire \wbd_uart_dat_i[3] ;
wire \wbd_uart_dat_i[4] ;
wire \wbd_uart_dat_i[5] ;
wire \wbd_uart_dat_i[6] ;
wire \wbd_uart_dat_i[7] ;
wire \wbd_uart_dat_i[8] ;
wire \wbd_uart_dat_i[9] ;
wire \wbd_uart_dat_o[0] ;
wire \wbd_uart_dat_o[10] ;
wire \wbd_uart_dat_o[11] ;
wire \wbd_uart_dat_o[12] ;
wire \wbd_uart_dat_o[13] ;
wire \wbd_uart_dat_o[14] ;
wire \wbd_uart_dat_o[15] ;
wire \wbd_uart_dat_o[16] ;
wire \wbd_uart_dat_o[17] ;
wire \wbd_uart_dat_o[18] ;
wire \wbd_uart_dat_o[19] ;
wire \wbd_uart_dat_o[1] ;
wire \wbd_uart_dat_o[20] ;
wire \wbd_uart_dat_o[21] ;
wire \wbd_uart_dat_o[22] ;
wire \wbd_uart_dat_o[23] ;
wire \wbd_uart_dat_o[24] ;
wire \wbd_uart_dat_o[25] ;
wire \wbd_uart_dat_o[26] ;
wire \wbd_uart_dat_o[27] ;
wire \wbd_uart_dat_o[28] ;
wire \wbd_uart_dat_o[29] ;
wire \wbd_uart_dat_o[2] ;
wire \wbd_uart_dat_o[30] ;
wire \wbd_uart_dat_o[31] ;
wire \wbd_uart_dat_o[3] ;
wire \wbd_uart_dat_o[4] ;
wire \wbd_uart_dat_o[5] ;
wire \wbd_uart_dat_o[6] ;
wire \wbd_uart_dat_o[7] ;
wire \wbd_uart_dat_o[8] ;
wire \wbd_uart_dat_o[9] ;
wire \wbd_uart_sel_o[0] ;
wire \wbd_uart_sel_o[1] ;
wire \wbd_uart_sel_o[2] ;
wire \wbd_uart_sel_o[3] ;
wire wbd_uart_stb_o;
wire wbd_uart_we_o;
glbl_cfg u_glbl_cfg (.bist_done(bist_done_rp),
.bist_en(bist_en),
.bist_load(bist_load),
.bist_run(bist_run),
.bist_sdi(bist_sdi),
.bist_sdo(bist_sdo_rp),
.bist_shift(bist_shift),
.cfg_sdr_en(cfg_sdr_en),
.mclk(wbd_clk_glbl_skew),
.reg_ack(wbd_glbl_ack_i),
.reg_cs(wbd_glbl_stb_o),
.reg_wr(wbd_glbl_we_o),
.reset_n(wbd_int_rst_n),
.sdr_init_done(sdr_init_done),
.soft_irq(soft_irq),
.vccd1(vccd1),
.vssd1(vssd1),
.wbd_clk_glbl(wbd_clk_glbl_skew),
.wbd_clk_int(wbd_clk_glbl_rp),
.bist_correct({\bist_correct_rp[3] ,
\bist_correct_rp[2] ,
\bist_correct_rp[1] ,
\bist_correct_rp[0] }),
.bist_error({\bist_error_rp[3] ,
\bist_error_rp[2] ,
\bist_error_rp[1] ,
\bist_error_rp[0] }),
.bist_error_cnt0({\bist_error_cnt0_rp[3] ,
\bist_error_cnt0_rp[2] ,
\bist_error_cnt0_rp[1] ,
\bist_error_cnt0_rp[0] }),
.bist_error_cnt1({\bist_error_cnt1_rp[3] ,
\bist_error_cnt1_rp[2] ,
\bist_error_cnt1_rp[1] ,
\bist_error_cnt1_rp[0] }),
.bist_error_cnt2({\bist_error_cnt2_rp[3] ,
\bist_error_cnt2_rp[2] ,
\bist_error_cnt2_rp[1] ,
\bist_error_cnt2_rp[0] }),
.bist_error_cnt3({\bist_error_cnt3_rp[3] ,
\bist_error_cnt3_rp[2] ,
\bist_error_cnt3_rp[1] ,
\bist_error_cnt3_rp[0] }),
.cfg_colbits({\cfg_colbits[1] ,
\cfg_colbits[0] }),
.cfg_cska_glbl({\cfg_cska_glbl_rp[3] ,
\cfg_cska_glbl_rp[2] ,
\cfg_cska_glbl_rp[1] ,
\cfg_cska_glbl_rp[0] }),
.cfg_req_depth({\cfg_req_depth[1] ,
\cfg_req_depth[0] }),
.cfg_sdr_cas({\cfg_sdr_cas[2] ,
\cfg_sdr_cas[1] ,
\cfg_sdr_cas[0] }),
.cfg_sdr_mode_reg({\cfg_sdr_mode_reg[12] ,
\cfg_sdr_mode_reg[11] ,
\cfg_sdr_mode_reg[10] ,
\cfg_sdr_mode_reg[9] ,
\cfg_sdr_mode_reg[8] ,
\cfg_sdr_mode_reg[7] ,
\cfg_sdr_mode_reg[6] ,
\cfg_sdr_mode_reg[5] ,
\cfg_sdr_mode_reg[4] ,
\cfg_sdr_mode_reg[3] ,
\cfg_sdr_mode_reg[2] ,
\cfg_sdr_mode_reg[1] ,
\cfg_sdr_mode_reg[0] }),
.cfg_sdr_rfmax({\cfg_sdr_rfmax[2] ,
\cfg_sdr_rfmax[1] ,
\cfg_sdr_rfmax[0] }),
.cfg_sdr_rfsh({\cfg_sdr_rfsh[11] ,
\cfg_sdr_rfsh[10] ,
\cfg_sdr_rfsh[9] ,
\cfg_sdr_rfsh[8] ,
\cfg_sdr_rfsh[7] ,
\cfg_sdr_rfsh[6] ,
\cfg_sdr_rfsh[5] ,
\cfg_sdr_rfsh[4] ,
\cfg_sdr_rfsh[3] ,
\cfg_sdr_rfsh[2] ,
\cfg_sdr_rfsh[1] ,
\cfg_sdr_rfsh[0] }),
.cfg_sdr_tras_d({\cfg_sdr_tras_d[3] ,
\cfg_sdr_tras_d[2] ,
\cfg_sdr_tras_d[1] ,
\cfg_sdr_tras_d[0] }),
.cfg_sdr_trcar_d({\cfg_sdr_trcar_d[3] ,
\cfg_sdr_trcar_d[2] ,
\cfg_sdr_trcar_d[1] ,
\cfg_sdr_trcar_d[0] }),
.cfg_sdr_trcd_d({\cfg_sdr_trcd_d[3] ,
\cfg_sdr_trcd_d[2] ,
\cfg_sdr_trcd_d[1] ,
\cfg_sdr_trcd_d[0] }),
.cfg_sdr_trp_d({\cfg_sdr_trp_d[3] ,
\cfg_sdr_trp_d[2] ,
\cfg_sdr_trp_d[1] ,
\cfg_sdr_trp_d[0] }),
.cfg_sdr_twr_d({\cfg_sdr_twr_d[3] ,
\cfg_sdr_twr_d[2] ,
\cfg_sdr_twr_d[1] ,
\cfg_sdr_twr_d[0] }),
.cfg_sdr_width({\cfg_sdr_width[1] ,
\cfg_sdr_width[0] }),
.fuse_mhartid({\fuse_mhartid[31] ,
\fuse_mhartid[30] ,
\fuse_mhartid[29] ,
\fuse_mhartid[28] ,
\fuse_mhartid[27] ,
\fuse_mhartid[26] ,
\fuse_mhartid[25] ,
\fuse_mhartid[24] ,
\fuse_mhartid[23] ,
\fuse_mhartid[22] ,
\fuse_mhartid[21] ,
\fuse_mhartid[20] ,
\fuse_mhartid[19] ,
\fuse_mhartid[18] ,
\fuse_mhartid[17] ,
\fuse_mhartid[16] ,
\fuse_mhartid[15] ,
\fuse_mhartid[14] ,
\fuse_mhartid[13] ,
\fuse_mhartid[12] ,
\fuse_mhartid[11] ,
\fuse_mhartid[10] ,
\fuse_mhartid[9] ,
\fuse_mhartid[8] ,
\fuse_mhartid[7] ,
\fuse_mhartid[6] ,
\fuse_mhartid[5] ,
\fuse_mhartid[4] ,
\fuse_mhartid[3] ,
\fuse_mhartid[2] ,
\fuse_mhartid[1] ,
\fuse_mhartid[0] }),
.irq_lines({\irq_lines[15] ,
\irq_lines[14] ,
\irq_lines[13] ,
\irq_lines[12] ,
\irq_lines[11] ,
\irq_lines[10] ,
\irq_lines[9] ,
\irq_lines[8] ,
\irq_lines[7] ,
\irq_lines[6] ,
\irq_lines[5] ,
\irq_lines[4] ,
\irq_lines[3] ,
\irq_lines[2] ,
\irq_lines[1] ,
\irq_lines[0] }),
.reg_addr({\wbd_glbl_adr_o[7] ,
\wbd_glbl_adr_o[6] ,
\wbd_glbl_adr_o[5] ,
\wbd_glbl_adr_o[4] ,
\wbd_glbl_adr_o[3] ,
\wbd_glbl_adr_o[2] ,
\wbd_glbl_adr_o[1] ,
\wbd_glbl_adr_o[0] }),
.reg_be({\wbd_glbl_sel_o[3] ,
\wbd_glbl_sel_o[2] ,
\wbd_glbl_sel_o[1] ,
\wbd_glbl_sel_o[0] }),
.reg_rdata({\wbd_glbl_dat_i[31] ,
\wbd_glbl_dat_i[30] ,
\wbd_glbl_dat_i[29] ,
\wbd_glbl_dat_i[28] ,
\wbd_glbl_dat_i[27] ,
\wbd_glbl_dat_i[26] ,
\wbd_glbl_dat_i[25] ,
\wbd_glbl_dat_i[24] ,
\wbd_glbl_dat_i[23] ,
\wbd_glbl_dat_i[22] ,
\wbd_glbl_dat_i[21] ,
\wbd_glbl_dat_i[20] ,
\wbd_glbl_dat_i[19] ,
\wbd_glbl_dat_i[18] ,
\wbd_glbl_dat_i[17] ,
\wbd_glbl_dat_i[16] ,
\wbd_glbl_dat_i[15] ,
\wbd_glbl_dat_i[14] ,
\wbd_glbl_dat_i[13] ,
\wbd_glbl_dat_i[12] ,
\wbd_glbl_dat_i[11] ,
\wbd_glbl_dat_i[10] ,
\wbd_glbl_dat_i[9] ,
\wbd_glbl_dat_i[8] ,
\wbd_glbl_dat_i[7] ,
\wbd_glbl_dat_i[6] ,
\wbd_glbl_dat_i[5] ,
\wbd_glbl_dat_i[4] ,
\wbd_glbl_dat_i[3] ,
\wbd_glbl_dat_i[2] ,
\wbd_glbl_dat_i[1] ,
\wbd_glbl_dat_i[0] }),
.reg_wdata({\wbd_glbl_dat_o[31] ,
\wbd_glbl_dat_o[30] ,
\wbd_glbl_dat_o[29] ,
\wbd_glbl_dat_o[28] ,
\wbd_glbl_dat_o[27] ,
\wbd_glbl_dat_o[26] ,
\wbd_glbl_dat_o[25] ,
\wbd_glbl_dat_o[24] ,
\wbd_glbl_dat_o[23] ,
\wbd_glbl_dat_o[22] ,
\wbd_glbl_dat_o[21] ,
\wbd_glbl_dat_o[20] ,
\wbd_glbl_dat_o[19] ,
\wbd_glbl_dat_o[18] ,
\wbd_glbl_dat_o[17] ,
\wbd_glbl_dat_o[16] ,
\wbd_glbl_dat_o[15] ,
\wbd_glbl_dat_o[14] ,
\wbd_glbl_dat_o[13] ,
\wbd_glbl_dat_o[12] ,
\wbd_glbl_dat_o[11] ,
\wbd_glbl_dat_o[10] ,
\wbd_glbl_dat_o[9] ,
\wbd_glbl_dat_o[8] ,
\wbd_glbl_dat_o[7] ,
\wbd_glbl_dat_o[6] ,
\wbd_glbl_dat_o[5] ,
\wbd_glbl_dat_o[4] ,
\wbd_glbl_dat_o[3] ,
\wbd_glbl_dat_o[2] ,
\wbd_glbl_dat_o[1] ,
\wbd_glbl_dat_o[0] }),
.user_irq({user_irq[2],
user_irq[1],
user_irq[0]}));
wb_interconnect u_intercon (.clk_i(wbd_clk_wi_skew),
.m0_wbd_ack_o(wbd_int_ack_o),
.m0_wbd_cyc_i(wbd_int_cyc_i),
.m0_wbd_err_o(wbd_int_err_o),
.m0_wbd_stb_i(wbd_int_stb_i),
.m0_wbd_we_i(wbd_int_we_i),
.m1_wbd_ack_o(wbd_riscv_imem_ack_o),
.m1_wbd_cyc_i(wbd_riscv_imem_stb_i),
.m1_wbd_err_o(wbd_riscv_imem_err_o),
.m1_wbd_stb_i(wbd_riscv_imem_stb_i),
.m1_wbd_we_i(wbd_riscv_imem_we_i),
.m2_wbd_ack_o(wbd_riscv_dmem_ack_o),
.m2_wbd_cyc_i(wbd_riscv_dmem_stb_i),
.m2_wbd_err_o(wbd_riscv_dmem_err_o),
.m2_wbd_stb_i(wbd_riscv_dmem_stb_i),
.m2_wbd_we_i(wbd_riscv_dmem_we_i),
.rst_n(wbd_int_rst_n),
.s0_wbd_ack_i(wbd_spim_ack_i),
.s0_wbd_cyc_o(wbd_spim_cyc_o),
.s0_wbd_stb_o(wbd_spim_stb_o),
.s0_wbd_we_o(wbd_spim_we_o),
.s1_wbd_ack_i(wbd_sdram_ack_i),
.s1_wbd_cyc_o(wbd_sdram_cyc_o),
.s1_wbd_stb_o(wbd_sdram_stb_o),
.s1_wbd_we_o(wbd_sdram_we_o),
.s2_wbd_ack_i(wbd_glbl_ack_i),
.s2_wbd_cyc_o(wbd_glbl_cyc_o),
.s2_wbd_stb_o(wbd_glbl_stb_o),
.s2_wbd_we_o(wbd_glbl_we_o),
.s3_wbd_ack_i(wbd_uart_ack_i),
.s3_wbd_cyc_o(wbd_uart_cyc_o),
.s3_wbd_stb_o(wbd_uart_stb_o),
.s3_wbd_we_o(wbd_uart_we_o),
.s4_wbd_ack_i(wbd_mbist_ack_i),
.s4_wbd_cyc_o(wbd_mbist_cyc_o),
.s4_wbd_stb_o(wbd_mbist_stb_o),
.s4_wbd_we_o(wbd_mbist_we_o),
.vccd1(vccd1),
.vssd1(vssd1),
.wbd_clk_int(wbd_clk_int),
.wbd_clk_wi(wbd_clk_wi_skew),
.boot_remap({\cfg_boot_remap[3] ,
\cfg_boot_remap[2] ,
\cfg_boot_remap[1] ,
\cfg_boot_remap[0] }),
.cfg_cska_wi({\cfg_clk_ctrl1[3] ,
\cfg_clk_ctrl1[2] ,
\cfg_clk_ctrl1[1] ,
\cfg_clk_ctrl1[0] }),
.ch_clk_in({wbd_clk_int,
wbd_clk_int,
wbd_clk_int,
wbd_clk_int,
wbd_clk_int,
wbd_clk_int}),
.ch_clk_out({wbd_clk_mbist_rp,
wbd_clk_glbl_rp,
wbd_clk_uart_rp,
wbd_clk_sdrc_rp,
wbd_clk_spim_rp,
wbd_clk_riscv_rp}),
.ch_data_in({\bist_error_cnt3[3] ,
\bist_error_cnt3[2] ,
\bist_error_cnt3[1] ,
\bist_error_cnt3[0] ,
\bist_correct[3] ,
\bist_error[3] ,
\bist_error_cnt2[3] ,
\bist_error_cnt2[2] ,
\bist_error_cnt2[1] ,
\bist_error_cnt2[0] ,
\bist_correct[2] ,
\bist_error[2] ,
\bist_error_cnt1[3] ,
\bist_error_cnt1[2] ,
\bist_error_cnt1[1] ,
\bist_error_cnt1[0] ,
\bist_correct[1] ,
\bist_error[1] ,
\bist_error_cnt0[3] ,
\bist_error_cnt0[2] ,
\bist_error_cnt0[1] ,
\bist_error_cnt0[0] ,
\bist_correct[0] ,
\bist_error[0] ,
bist_done,
bist_sdo,
bist_shift,
bist_sdi,
bist_load,
bist_run,
bist_en,
soft_irq,
\irq_lines[15] ,
\irq_lines[14] ,
\irq_lines[13] ,
\irq_lines[12] ,
\irq_lines[11] ,
\irq_lines[10] ,
\irq_lines[9] ,
\irq_lines[8] ,
\irq_lines[7] ,
\irq_lines[6] ,
\irq_lines[5] ,
\irq_lines[4] ,
\irq_lines[3] ,
\irq_lines[2] ,
\irq_lines[1] ,
\irq_lines[0] ,
\fuse_mhartid[31] ,
\fuse_mhartid[30] ,
\fuse_mhartid[29] ,
\fuse_mhartid[28] ,
\fuse_mhartid[27] ,
\fuse_mhartid[26] ,
\fuse_mhartid[25] ,
\fuse_mhartid[24] ,
\fuse_mhartid[23] ,
\fuse_mhartid[22] ,
\fuse_mhartid[21] ,
\fuse_mhartid[20] ,
\fuse_mhartid[19] ,
\fuse_mhartid[18] ,
\fuse_mhartid[17] ,
\fuse_mhartid[16] ,
\fuse_mhartid[15] ,
\fuse_mhartid[14] ,
\fuse_mhartid[13] ,
\fuse_mhartid[12] ,
\fuse_mhartid[11] ,
\fuse_mhartid[10] ,
\fuse_mhartid[9] ,
\fuse_mhartid[8] ,
\fuse_mhartid[7] ,
\fuse_mhartid[6] ,
\fuse_mhartid[5] ,
\fuse_mhartid[4] ,
\fuse_mhartid[3] ,
\fuse_mhartid[2] ,
\fuse_mhartid[1] ,
\fuse_mhartid[0] ,
\cfg_clk_ctrl2[11] ,
\cfg_clk_ctrl2[10] ,
\cfg_clk_ctrl2[9] ,
\cfg_clk_ctrl2[8] ,
\cfg_clk_ctrl2[7] ,
\cfg_clk_ctrl2[6] ,
\cfg_clk_ctrl2[5] ,
\cfg_clk_ctrl2[4] ,
\cfg_clk_ctrl2[3] ,
\cfg_clk_ctrl2[2] ,
\cfg_clk_ctrl2[1] ,
\cfg_clk_ctrl2[0] ,
\cfg_clk_ctrl1[27] ,
\cfg_clk_ctrl1[26] ,
\cfg_clk_ctrl1[25] ,
\cfg_clk_ctrl1[24] ,
\cfg_clk_ctrl1[23] ,
\cfg_clk_ctrl1[22] ,
\cfg_clk_ctrl1[21] ,
\cfg_clk_ctrl1[20] ,
\cfg_clk_ctrl1[19] ,
\cfg_clk_ctrl1[18] ,
\cfg_clk_ctrl1[17] ,
\cfg_clk_ctrl1[16] ,
\cfg_clk_ctrl1[15] ,
\cfg_clk_ctrl1[14] ,
\cfg_clk_ctrl1[13] ,
\cfg_clk_ctrl1[12] ,
\cfg_clk_ctrl1[11] ,
\cfg_clk_ctrl1[10] ,
\cfg_clk_ctrl1[9] ,
\cfg_clk_ctrl1[8] ,
\cfg_clk_ctrl1[7] ,
\cfg_clk_ctrl1[6] ,
\cfg_clk_ctrl1[5] ,
\cfg_clk_ctrl1[4] }),
.ch_data_out({\bist_error_cnt3_rp[3] ,
\bist_error_cnt3_rp[2] ,
\bist_error_cnt3_rp[1] ,
\bist_error_cnt3_rp[0] ,
\bist_correct_rp[3] ,
\bist_error_rp[3] ,
\bist_error_cnt2_rp[3] ,
\bist_error_cnt2_rp[2] ,
\bist_error_cnt2_rp[1] ,
\bist_error_cnt2_rp[0] ,
\bist_correct_rp[2] ,
\bist_error_rp[2] ,
\bist_error_cnt1_rp[3] ,
\bist_error_cnt1_rp[2] ,
\bist_error_cnt1_rp[1] ,
\bist_error_cnt1_rp[0] ,
\bist_correct_rp[1] ,
\bist_error_rp[1] ,
\bist_error_cnt0_rp[3] ,
\bist_error_cnt0_rp[2] ,
\bist_error_cnt0_rp[1] ,
\bist_error_cnt0_rp[0] ,
\bist_correct_rp[0] ,
\bist_error_rp[0] ,
bist_done_rp,
bist_sdo_rp,
bist_shift_rp,
bist_sdi_rp,
bist_load_rp,
bist_run_rp,
bist_en_rp,
soft_irq_rp,
\irq_lines_rp[15] ,
\irq_lines_rp[14] ,
\irq_lines_rp[13] ,
\irq_lines_rp[12] ,
\irq_lines_rp[11] ,
\irq_lines_rp[10] ,
\irq_lines_rp[9] ,
\irq_lines_rp[8] ,
\irq_lines_rp[7] ,
\irq_lines_rp[6] ,
\irq_lines_rp[5] ,
\irq_lines_rp[4] ,
\irq_lines_rp[3] ,
\irq_lines_rp[2] ,
\irq_lines_rp[1] ,
\irq_lines_rp[0] ,
\fuse_mhartid_rp[31] ,
\fuse_mhartid_rp[30] ,
\fuse_mhartid_rp[29] ,
\fuse_mhartid_rp[28] ,
\fuse_mhartid_rp[27] ,
\fuse_mhartid_rp[26] ,
\fuse_mhartid_rp[25] ,
\fuse_mhartid_rp[24] ,
\fuse_mhartid_rp[23] ,
\fuse_mhartid_rp[22] ,
\fuse_mhartid_rp[21] ,
\fuse_mhartid_rp[20] ,
\fuse_mhartid_rp[19] ,
\fuse_mhartid_rp[18] ,
\fuse_mhartid_rp[17] ,
\fuse_mhartid_rp[16] ,
\fuse_mhartid_rp[15] ,
\fuse_mhartid_rp[14] ,
\fuse_mhartid_rp[13] ,
\fuse_mhartid_rp[12] ,
\fuse_mhartid_rp[11] ,
\fuse_mhartid_rp[10] ,
\fuse_mhartid_rp[9] ,
\fuse_mhartid_rp[8] ,
\fuse_mhartid_rp[7] ,
\fuse_mhartid_rp[6] ,
\fuse_mhartid_rp[5] ,
\fuse_mhartid_rp[4] ,
\fuse_mhartid_rp[3] ,
\fuse_mhartid_rp[2] ,
\fuse_mhartid_rp[1] ,
\fuse_mhartid_rp[0] ,
\cfg_cska_sp_co_rp[3] ,
\cfg_cska_sp_co_rp[2] ,
\cfg_cska_sp_co_rp[1] ,
\cfg_cska_sp_co_rp[0] ,
\cfg_cska_sd_ci_rp[3] ,
\cfg_cska_sd_ci_rp[2] ,
\cfg_cska_sd_ci_rp[1] ,
\cfg_cska_sd_ci_rp[0] ,
\cfg_cska_sd_co_rp[3] ,
\cfg_cska_sd_co_rp[2] ,
\cfg_cska_sd_co_rp[1] ,
\cfg_cska_sd_co_rp[0] ,
\cfg_cska_mbist_rp[3] ,
\cfg_cska_mbist_rp[2] ,
\cfg_cska_mbist_rp[1] ,
\cfg_cska_mbist_rp[0] ,
\cfg_cska_glbl_rp[3] ,
\cfg_cska_glbl_rp[2] ,
\cfg_cska_glbl_rp[1] ,
\cfg_cska_glbl_rp[0] ,
\cfg_cska_uart_rp[3] ,
\cfg_cska_uart_rp[2] ,
\cfg_cska_uart_rp[1] ,
\cfg_cska_uart_rp[0] ,
\cfg_cska_sdram_rp[3] ,
\cfg_cska_sdram_rp[2] ,
\cfg_cska_sdram_rp[1] ,
\cfg_cska_sdram_rp[0] ,
\cfg_cska_spi_rp[3] ,
\cfg_cska_spi_rp[2] ,
\cfg_cska_spi_rp[1] ,
\cfg_cska_spi_rp[0] ,
\cfg_cska_riscv_rp[3] ,
\cfg_cska_riscv_rp[2] ,
\cfg_cska_riscv_rp[1] ,
\cfg_cska_riscv_rp[0] }),
.m0_wbd_adr_i({\wbd_int_adr_i[31] ,
\wbd_int_adr_i[30] ,
\wbd_int_adr_i[29] ,
\wbd_int_adr_i[28] ,
\wbd_int_adr_i[27] ,
\wbd_int_adr_i[26] ,
\wbd_int_adr_i[25] ,
\wbd_int_adr_i[24] ,
\wbd_int_adr_i[23] ,
\wbd_int_adr_i[22] ,
\wbd_int_adr_i[21] ,
\wbd_int_adr_i[20] ,
\wbd_int_adr_i[19] ,
\wbd_int_adr_i[18] ,
\wbd_int_adr_i[17] ,
\wbd_int_adr_i[16] ,
\wbd_int_adr_i[15] ,
\wbd_int_adr_i[14] ,
\wbd_int_adr_i[13] ,
\wbd_int_adr_i[12] ,
\wbd_int_adr_i[11] ,
\wbd_int_adr_i[10] ,
\wbd_int_adr_i[9] ,
\wbd_int_adr_i[8] ,
\wbd_int_adr_i[7] ,
\wbd_int_adr_i[6] ,
\wbd_int_adr_i[5] ,
\wbd_int_adr_i[4] ,
\wbd_int_adr_i[3] ,
\wbd_int_adr_i[2] ,
\wbd_int_adr_i[1] ,
\wbd_int_adr_i[0] }),
.m0_wbd_dat_i({\wbd_int_dat_i[31] ,
\wbd_int_dat_i[30] ,
\wbd_int_dat_i[29] ,
\wbd_int_dat_i[28] ,
\wbd_int_dat_i[27] ,
\wbd_int_dat_i[26] ,
\wbd_int_dat_i[25] ,
\wbd_int_dat_i[24] ,
\wbd_int_dat_i[23] ,
\wbd_int_dat_i[22] ,
\wbd_int_dat_i[21] ,
\wbd_int_dat_i[20] ,
\wbd_int_dat_i[19] ,
\wbd_int_dat_i[18] ,
\wbd_int_dat_i[17] ,
\wbd_int_dat_i[16] ,
\wbd_int_dat_i[15] ,
\wbd_int_dat_i[14] ,
\wbd_int_dat_i[13] ,
\wbd_int_dat_i[12] ,
\wbd_int_dat_i[11] ,
\wbd_int_dat_i[10] ,
\wbd_int_dat_i[9] ,
\wbd_int_dat_i[8] ,
\wbd_int_dat_i[7] ,
\wbd_int_dat_i[6] ,
\wbd_int_dat_i[5] ,
\wbd_int_dat_i[4] ,
\wbd_int_dat_i[3] ,
\wbd_int_dat_i[2] ,
\wbd_int_dat_i[1] ,
\wbd_int_dat_i[0] }),
.m0_wbd_dat_o({\wbd_int_dat_o[31] ,
\wbd_int_dat_o[30] ,
\wbd_int_dat_o[29] ,
\wbd_int_dat_o[28] ,
\wbd_int_dat_o[27] ,
\wbd_int_dat_o[26] ,
\wbd_int_dat_o[25] ,
\wbd_int_dat_o[24] ,
\wbd_int_dat_o[23] ,
\wbd_int_dat_o[22] ,
\wbd_int_dat_o[21] ,
\wbd_int_dat_o[20] ,
\wbd_int_dat_o[19] ,
\wbd_int_dat_o[18] ,
\wbd_int_dat_o[17] ,
\wbd_int_dat_o[16] ,
\wbd_int_dat_o[15] ,
\wbd_int_dat_o[14] ,
\wbd_int_dat_o[13] ,
\wbd_int_dat_o[12] ,
\wbd_int_dat_o[11] ,
\wbd_int_dat_o[10] ,
\wbd_int_dat_o[9] ,
\wbd_int_dat_o[8] ,
\wbd_int_dat_o[7] ,
\wbd_int_dat_o[6] ,
\wbd_int_dat_o[5] ,
\wbd_int_dat_o[4] ,
\wbd_int_dat_o[3] ,
\wbd_int_dat_o[2] ,
\wbd_int_dat_o[1] ,
\wbd_int_dat_o[0] }),
.m0_wbd_sel_i({\wbd_int_sel_i[3] ,
\wbd_int_sel_i[2] ,
\wbd_int_sel_i[1] ,
\wbd_int_sel_i[0] }),
.m1_wbd_adr_i({\wbd_riscv_imem_adr_i[31] ,
\wbd_riscv_imem_adr_i[30] ,
\wbd_riscv_imem_adr_i[29] ,
\wbd_riscv_imem_adr_i[28] ,
\wbd_riscv_imem_adr_i[27] ,
\wbd_riscv_imem_adr_i[26] ,
\wbd_riscv_imem_adr_i[25] ,
\wbd_riscv_imem_adr_i[24] ,
\wbd_riscv_imem_adr_i[23] ,
\wbd_riscv_imem_adr_i[22] ,
\wbd_riscv_imem_adr_i[21] ,
\wbd_riscv_imem_adr_i[20] ,
\wbd_riscv_imem_adr_i[19] ,
\wbd_riscv_imem_adr_i[18] ,
\wbd_riscv_imem_adr_i[17] ,
\wbd_riscv_imem_adr_i[16] ,
\wbd_riscv_imem_adr_i[15] ,
\wbd_riscv_imem_adr_i[14] ,
\wbd_riscv_imem_adr_i[13] ,
\wbd_riscv_imem_adr_i[12] ,
\wbd_riscv_imem_adr_i[11] ,
\wbd_riscv_imem_adr_i[10] ,
\wbd_riscv_imem_adr_i[9] ,
\wbd_riscv_imem_adr_i[8] ,
\wbd_riscv_imem_adr_i[7] ,
\wbd_riscv_imem_adr_i[6] ,
\wbd_riscv_imem_adr_i[5] ,
\wbd_riscv_imem_adr_i[4] ,
\wbd_riscv_imem_adr_i[3] ,
\wbd_riscv_imem_adr_i[2] ,
\wbd_riscv_imem_adr_i[1] ,
\wbd_riscv_imem_adr_i[0] }),
.m1_wbd_dat_i({\wbd_riscv_imem_dat_i[31] ,
\wbd_riscv_imem_dat_i[30] ,
\wbd_riscv_imem_dat_i[29] ,
\wbd_riscv_imem_dat_i[28] ,
\wbd_riscv_imem_dat_i[27] ,
\wbd_riscv_imem_dat_i[26] ,
\wbd_riscv_imem_dat_i[25] ,
\wbd_riscv_imem_dat_i[24] ,
\wbd_riscv_imem_dat_i[23] ,
\wbd_riscv_imem_dat_i[22] ,
\wbd_riscv_imem_dat_i[21] ,
\wbd_riscv_imem_dat_i[20] ,
\wbd_riscv_imem_dat_i[19] ,
\wbd_riscv_imem_dat_i[18] ,
\wbd_riscv_imem_dat_i[17] ,
\wbd_riscv_imem_dat_i[16] ,
\wbd_riscv_imem_dat_i[15] ,
\wbd_riscv_imem_dat_i[14] ,
\wbd_riscv_imem_dat_i[13] ,
\wbd_riscv_imem_dat_i[12] ,
\wbd_riscv_imem_dat_i[11] ,
\wbd_riscv_imem_dat_i[10] ,
\wbd_riscv_imem_dat_i[9] ,
\wbd_riscv_imem_dat_i[8] ,
\wbd_riscv_imem_dat_i[7] ,
\wbd_riscv_imem_dat_i[6] ,
\wbd_riscv_imem_dat_i[5] ,
\wbd_riscv_imem_dat_i[4] ,
\wbd_riscv_imem_dat_i[3] ,
\wbd_riscv_imem_dat_i[2] ,
\wbd_riscv_imem_dat_i[1] ,
\wbd_riscv_imem_dat_i[0] }),
.m1_wbd_dat_o({\wbd_riscv_imem_dat_o[31] ,
\wbd_riscv_imem_dat_o[30] ,
\wbd_riscv_imem_dat_o[29] ,
\wbd_riscv_imem_dat_o[28] ,
\wbd_riscv_imem_dat_o[27] ,
\wbd_riscv_imem_dat_o[26] ,
\wbd_riscv_imem_dat_o[25] ,
\wbd_riscv_imem_dat_o[24] ,
\wbd_riscv_imem_dat_o[23] ,
\wbd_riscv_imem_dat_o[22] ,
\wbd_riscv_imem_dat_o[21] ,
\wbd_riscv_imem_dat_o[20] ,
\wbd_riscv_imem_dat_o[19] ,
\wbd_riscv_imem_dat_o[18] ,
\wbd_riscv_imem_dat_o[17] ,
\wbd_riscv_imem_dat_o[16] ,
\wbd_riscv_imem_dat_o[15] ,
\wbd_riscv_imem_dat_o[14] ,
\wbd_riscv_imem_dat_o[13] ,
\wbd_riscv_imem_dat_o[12] ,
\wbd_riscv_imem_dat_o[11] ,
\wbd_riscv_imem_dat_o[10] ,
\wbd_riscv_imem_dat_o[9] ,
\wbd_riscv_imem_dat_o[8] ,
\wbd_riscv_imem_dat_o[7] ,
\wbd_riscv_imem_dat_o[6] ,
\wbd_riscv_imem_dat_o[5] ,
\wbd_riscv_imem_dat_o[4] ,
\wbd_riscv_imem_dat_o[3] ,
\wbd_riscv_imem_dat_o[2] ,
\wbd_riscv_imem_dat_o[1] ,
\wbd_riscv_imem_dat_o[0] }),
.m1_wbd_sel_i({\wbd_riscv_imem_sel_i[3] ,
\wbd_riscv_imem_sel_i[2] ,
\wbd_riscv_imem_sel_i[1] ,
\wbd_riscv_imem_sel_i[0] }),
.m2_wbd_adr_i({\wbd_riscv_dmem_adr_i[31] ,
\wbd_riscv_dmem_adr_i[30] ,
\wbd_riscv_dmem_adr_i[29] ,
\wbd_riscv_dmem_adr_i[28] ,
\wbd_riscv_dmem_adr_i[27] ,
\wbd_riscv_dmem_adr_i[26] ,
\wbd_riscv_dmem_adr_i[25] ,
\wbd_riscv_dmem_adr_i[24] ,
\wbd_riscv_dmem_adr_i[23] ,
\wbd_riscv_dmem_adr_i[22] ,
\wbd_riscv_dmem_adr_i[21] ,
\wbd_riscv_dmem_adr_i[20] ,
\wbd_riscv_dmem_adr_i[19] ,
\wbd_riscv_dmem_adr_i[18] ,
\wbd_riscv_dmem_adr_i[17] ,
\wbd_riscv_dmem_adr_i[16] ,
\wbd_riscv_dmem_adr_i[15] ,
\wbd_riscv_dmem_adr_i[14] ,
\wbd_riscv_dmem_adr_i[13] ,
\wbd_riscv_dmem_adr_i[12] ,
\wbd_riscv_dmem_adr_i[11] ,
\wbd_riscv_dmem_adr_i[10] ,
\wbd_riscv_dmem_adr_i[9] ,
\wbd_riscv_dmem_adr_i[8] ,
\wbd_riscv_dmem_adr_i[7] ,
\wbd_riscv_dmem_adr_i[6] ,
\wbd_riscv_dmem_adr_i[5] ,
\wbd_riscv_dmem_adr_i[4] ,
\wbd_riscv_dmem_adr_i[3] ,
\wbd_riscv_dmem_adr_i[2] ,
\wbd_riscv_dmem_adr_i[1] ,
\wbd_riscv_dmem_adr_i[0] }),
.m2_wbd_dat_i({\wbd_riscv_dmem_dat_i[31] ,
\wbd_riscv_dmem_dat_i[30] ,
\wbd_riscv_dmem_dat_i[29] ,
\wbd_riscv_dmem_dat_i[28] ,
\wbd_riscv_dmem_dat_i[27] ,
\wbd_riscv_dmem_dat_i[26] ,
\wbd_riscv_dmem_dat_i[25] ,
\wbd_riscv_dmem_dat_i[24] ,
\wbd_riscv_dmem_dat_i[23] ,
\wbd_riscv_dmem_dat_i[22] ,
\wbd_riscv_dmem_dat_i[21] ,
\wbd_riscv_dmem_dat_i[20] ,
\wbd_riscv_dmem_dat_i[19] ,
\wbd_riscv_dmem_dat_i[18] ,
\wbd_riscv_dmem_dat_i[17] ,
\wbd_riscv_dmem_dat_i[16] ,
\wbd_riscv_dmem_dat_i[15] ,
\wbd_riscv_dmem_dat_i[14] ,
\wbd_riscv_dmem_dat_i[13] ,
\wbd_riscv_dmem_dat_i[12] ,
\wbd_riscv_dmem_dat_i[11] ,
\wbd_riscv_dmem_dat_i[10] ,
\wbd_riscv_dmem_dat_i[9] ,
\wbd_riscv_dmem_dat_i[8] ,
\wbd_riscv_dmem_dat_i[7] ,
\wbd_riscv_dmem_dat_i[6] ,
\wbd_riscv_dmem_dat_i[5] ,
\wbd_riscv_dmem_dat_i[4] ,
\wbd_riscv_dmem_dat_i[3] ,
\wbd_riscv_dmem_dat_i[2] ,
\wbd_riscv_dmem_dat_i[1] ,
\wbd_riscv_dmem_dat_i[0] }),
.m2_wbd_dat_o({\wbd_riscv_dmem_dat_o[31] ,
\wbd_riscv_dmem_dat_o[30] ,
\wbd_riscv_dmem_dat_o[29] ,
\wbd_riscv_dmem_dat_o[28] ,
\wbd_riscv_dmem_dat_o[27] ,
\wbd_riscv_dmem_dat_o[26] ,
\wbd_riscv_dmem_dat_o[25] ,
\wbd_riscv_dmem_dat_o[24] ,
\wbd_riscv_dmem_dat_o[23] ,
\wbd_riscv_dmem_dat_o[22] ,
\wbd_riscv_dmem_dat_o[21] ,
\wbd_riscv_dmem_dat_o[20] ,
\wbd_riscv_dmem_dat_o[19] ,
\wbd_riscv_dmem_dat_o[18] ,
\wbd_riscv_dmem_dat_o[17] ,
\wbd_riscv_dmem_dat_o[16] ,
\wbd_riscv_dmem_dat_o[15] ,
\wbd_riscv_dmem_dat_o[14] ,
\wbd_riscv_dmem_dat_o[13] ,
\wbd_riscv_dmem_dat_o[12] ,
\wbd_riscv_dmem_dat_o[11] ,
\wbd_riscv_dmem_dat_o[10] ,
\wbd_riscv_dmem_dat_o[9] ,
\wbd_riscv_dmem_dat_o[8] ,
\wbd_riscv_dmem_dat_o[7] ,
\wbd_riscv_dmem_dat_o[6] ,
\wbd_riscv_dmem_dat_o[5] ,
\wbd_riscv_dmem_dat_o[4] ,
\wbd_riscv_dmem_dat_o[3] ,
\wbd_riscv_dmem_dat_o[2] ,
\wbd_riscv_dmem_dat_o[1] ,
\wbd_riscv_dmem_dat_o[0] }),
.m2_wbd_sel_i({\wbd_riscv_dmem_sel_i[3] ,
\wbd_riscv_dmem_sel_i[2] ,
\wbd_riscv_dmem_sel_i[1] ,
\wbd_riscv_dmem_sel_i[0] }),
.s0_wbd_adr_o({\wbd_spim_adr_o[31] ,
\wbd_spim_adr_o[30] ,
\wbd_spim_adr_o[29] ,
\wbd_spim_adr_o[28] ,
\wbd_spim_adr_o[27] ,
\wbd_spim_adr_o[26] ,
\wbd_spim_adr_o[25] ,
\wbd_spim_adr_o[24] ,
\wbd_spim_adr_o[23] ,
\wbd_spim_adr_o[22] ,
\wbd_spim_adr_o[21] ,
\wbd_spim_adr_o[20] ,
\wbd_spim_adr_o[19] ,
\wbd_spim_adr_o[18] ,
\wbd_spim_adr_o[17] ,
\wbd_spim_adr_o[16] ,
\wbd_spim_adr_o[15] ,
\wbd_spim_adr_o[14] ,
\wbd_spim_adr_o[13] ,
\wbd_spim_adr_o[12] ,
\wbd_spim_adr_o[11] ,
\wbd_spim_adr_o[10] ,
\wbd_spim_adr_o[9] ,
\wbd_spim_adr_o[8] ,
\wbd_spim_adr_o[7] ,
\wbd_spim_adr_o[6] ,
\wbd_spim_adr_o[5] ,
\wbd_spim_adr_o[4] ,
\wbd_spim_adr_o[3] ,
\wbd_spim_adr_o[2] ,
\wbd_spim_adr_o[1] ,
\wbd_spim_adr_o[0] }),
.s0_wbd_dat_i({\wbd_spim_dat_i[31] ,
\wbd_spim_dat_i[30] ,
\wbd_spim_dat_i[29] ,
\wbd_spim_dat_i[28] ,
\wbd_spim_dat_i[27] ,
\wbd_spim_dat_i[26] ,
\wbd_spim_dat_i[25] ,
\wbd_spim_dat_i[24] ,
\wbd_spim_dat_i[23] ,
\wbd_spim_dat_i[22] ,
\wbd_spim_dat_i[21] ,
\wbd_spim_dat_i[20] ,
\wbd_spim_dat_i[19] ,
\wbd_spim_dat_i[18] ,
\wbd_spim_dat_i[17] ,
\wbd_spim_dat_i[16] ,
\wbd_spim_dat_i[15] ,
\wbd_spim_dat_i[14] ,
\wbd_spim_dat_i[13] ,
\wbd_spim_dat_i[12] ,
\wbd_spim_dat_i[11] ,
\wbd_spim_dat_i[10] ,
\wbd_spim_dat_i[9] ,
\wbd_spim_dat_i[8] ,
\wbd_spim_dat_i[7] ,
\wbd_spim_dat_i[6] ,
\wbd_spim_dat_i[5] ,
\wbd_spim_dat_i[4] ,
\wbd_spim_dat_i[3] ,
\wbd_spim_dat_i[2] ,
\wbd_spim_dat_i[1] ,
\wbd_spim_dat_i[0] }),
.s0_wbd_dat_o({\wbd_spim_dat_o[31] ,
\wbd_spim_dat_o[30] ,
\wbd_spim_dat_o[29] ,
\wbd_spim_dat_o[28] ,
\wbd_spim_dat_o[27] ,
\wbd_spim_dat_o[26] ,
\wbd_spim_dat_o[25] ,
\wbd_spim_dat_o[24] ,
\wbd_spim_dat_o[23] ,
\wbd_spim_dat_o[22] ,
\wbd_spim_dat_o[21] ,
\wbd_spim_dat_o[20] ,
\wbd_spim_dat_o[19] ,
\wbd_spim_dat_o[18] ,
\wbd_spim_dat_o[17] ,
\wbd_spim_dat_o[16] ,
\wbd_spim_dat_o[15] ,
\wbd_spim_dat_o[14] ,
\wbd_spim_dat_o[13] ,
\wbd_spim_dat_o[12] ,
\wbd_spim_dat_o[11] ,
\wbd_spim_dat_o[10] ,
\wbd_spim_dat_o[9] ,
\wbd_spim_dat_o[8] ,
\wbd_spim_dat_o[7] ,
\wbd_spim_dat_o[6] ,
\wbd_spim_dat_o[5] ,
\wbd_spim_dat_o[4] ,
\wbd_spim_dat_o[3] ,
\wbd_spim_dat_o[2] ,
\wbd_spim_dat_o[1] ,
\wbd_spim_dat_o[0] }),
.s0_wbd_sel_o({\wbd_spim_sel_o[3] ,
\wbd_spim_sel_o[2] ,
\wbd_spim_sel_o[1] ,
\wbd_spim_sel_o[0] }),
.s1_wbd_adr_o({\wbd_sdram_adr_o[31] ,
\wbd_sdram_adr_o[30] ,
\wbd_sdram_adr_o[29] ,
\wbd_sdram_adr_o[28] ,
\wbd_sdram_adr_o[27] ,
\wbd_sdram_adr_o[26] ,
\wbd_sdram_adr_o[25] ,
\wbd_sdram_adr_o[24] ,
\wbd_sdram_adr_o[23] ,
\wbd_sdram_adr_o[22] ,
\wbd_sdram_adr_o[21] ,
\wbd_sdram_adr_o[20] ,
\wbd_sdram_adr_o[19] ,
\wbd_sdram_adr_o[18] ,
\wbd_sdram_adr_o[17] ,
\wbd_sdram_adr_o[16] ,
\wbd_sdram_adr_o[15] ,
\wbd_sdram_adr_o[14] ,
\wbd_sdram_adr_o[13] ,
\wbd_sdram_adr_o[12] ,
\wbd_sdram_adr_o[11] ,
\wbd_sdram_adr_o[10] ,
\wbd_sdram_adr_o[9] ,
\wbd_sdram_adr_o[8] ,
\wbd_sdram_adr_o[7] ,
\wbd_sdram_adr_o[6] ,
\wbd_sdram_adr_o[5] ,
\wbd_sdram_adr_o[4] ,
\wbd_sdram_adr_o[3] ,
\wbd_sdram_adr_o[2] ,
\wbd_sdram_adr_o[1] ,
\wbd_sdram_adr_o[0] }),
.s1_wbd_dat_i({\wbd_sdram_dat_i[31] ,
\wbd_sdram_dat_i[30] ,
\wbd_sdram_dat_i[29] ,
\wbd_sdram_dat_i[28] ,
\wbd_sdram_dat_i[27] ,
\wbd_sdram_dat_i[26] ,
\wbd_sdram_dat_i[25] ,
\wbd_sdram_dat_i[24] ,
\wbd_sdram_dat_i[23] ,
\wbd_sdram_dat_i[22] ,
\wbd_sdram_dat_i[21] ,
\wbd_sdram_dat_i[20] ,
\wbd_sdram_dat_i[19] ,
\wbd_sdram_dat_i[18] ,
\wbd_sdram_dat_i[17] ,
\wbd_sdram_dat_i[16] ,
\wbd_sdram_dat_i[15] ,
\wbd_sdram_dat_i[14] ,
\wbd_sdram_dat_i[13] ,
\wbd_sdram_dat_i[12] ,
\wbd_sdram_dat_i[11] ,
\wbd_sdram_dat_i[10] ,
\wbd_sdram_dat_i[9] ,
\wbd_sdram_dat_i[8] ,
\wbd_sdram_dat_i[7] ,
\wbd_sdram_dat_i[6] ,
\wbd_sdram_dat_i[5] ,
\wbd_sdram_dat_i[4] ,
\wbd_sdram_dat_i[3] ,
\wbd_sdram_dat_i[2] ,
\wbd_sdram_dat_i[1] ,
\wbd_sdram_dat_i[0] }),
.s1_wbd_dat_o({\wbd_sdram_dat_o[31] ,
\wbd_sdram_dat_o[30] ,
\wbd_sdram_dat_o[29] ,
\wbd_sdram_dat_o[28] ,
\wbd_sdram_dat_o[27] ,
\wbd_sdram_dat_o[26] ,
\wbd_sdram_dat_o[25] ,
\wbd_sdram_dat_o[24] ,
\wbd_sdram_dat_o[23] ,
\wbd_sdram_dat_o[22] ,
\wbd_sdram_dat_o[21] ,
\wbd_sdram_dat_o[20] ,
\wbd_sdram_dat_o[19] ,
\wbd_sdram_dat_o[18] ,
\wbd_sdram_dat_o[17] ,
\wbd_sdram_dat_o[16] ,
\wbd_sdram_dat_o[15] ,
\wbd_sdram_dat_o[14] ,
\wbd_sdram_dat_o[13] ,
\wbd_sdram_dat_o[12] ,
\wbd_sdram_dat_o[11] ,
\wbd_sdram_dat_o[10] ,
\wbd_sdram_dat_o[9] ,
\wbd_sdram_dat_o[8] ,
\wbd_sdram_dat_o[7] ,
\wbd_sdram_dat_o[6] ,
\wbd_sdram_dat_o[5] ,
\wbd_sdram_dat_o[4] ,
\wbd_sdram_dat_o[3] ,
\wbd_sdram_dat_o[2] ,
\wbd_sdram_dat_o[1] ,
\wbd_sdram_dat_o[0] }),
.s1_wbd_sel_o({\wbd_sdram_sel_o[3] ,
\wbd_sdram_sel_o[2] ,
\wbd_sdram_sel_o[1] ,
\wbd_sdram_sel_o[0] }),
.s2_wbd_adr_o({\wbd_glbl_adr_o[7] ,
\wbd_glbl_adr_o[6] ,
\wbd_glbl_adr_o[5] ,
\wbd_glbl_adr_o[4] ,
\wbd_glbl_adr_o[3] ,
\wbd_glbl_adr_o[2] ,
\wbd_glbl_adr_o[1] ,
\wbd_glbl_adr_o[0] }),
.s2_wbd_dat_i({\wbd_glbl_dat_i[31] ,
\wbd_glbl_dat_i[30] ,
\wbd_glbl_dat_i[29] ,
\wbd_glbl_dat_i[28] ,
\wbd_glbl_dat_i[27] ,
\wbd_glbl_dat_i[26] ,
\wbd_glbl_dat_i[25] ,
\wbd_glbl_dat_i[24] ,
\wbd_glbl_dat_i[23] ,
\wbd_glbl_dat_i[22] ,
\wbd_glbl_dat_i[21] ,
\wbd_glbl_dat_i[20] ,
\wbd_glbl_dat_i[19] ,
\wbd_glbl_dat_i[18] ,
\wbd_glbl_dat_i[17] ,
\wbd_glbl_dat_i[16] ,
\wbd_glbl_dat_i[15] ,
\wbd_glbl_dat_i[14] ,
\wbd_glbl_dat_i[13] ,
\wbd_glbl_dat_i[12] ,
\wbd_glbl_dat_i[11] ,
\wbd_glbl_dat_i[10] ,
\wbd_glbl_dat_i[9] ,
\wbd_glbl_dat_i[8] ,
\wbd_glbl_dat_i[7] ,
\wbd_glbl_dat_i[6] ,
\wbd_glbl_dat_i[5] ,
\wbd_glbl_dat_i[4] ,
\wbd_glbl_dat_i[3] ,
\wbd_glbl_dat_i[2] ,
\wbd_glbl_dat_i[1] ,
\wbd_glbl_dat_i[0] }),
.s2_wbd_dat_o({\wbd_glbl_dat_o[31] ,
\wbd_glbl_dat_o[30] ,
\wbd_glbl_dat_o[29] ,
\wbd_glbl_dat_o[28] ,
\wbd_glbl_dat_o[27] ,
\wbd_glbl_dat_o[26] ,
\wbd_glbl_dat_o[25] ,
\wbd_glbl_dat_o[24] ,
\wbd_glbl_dat_o[23] ,
\wbd_glbl_dat_o[22] ,
\wbd_glbl_dat_o[21] ,
\wbd_glbl_dat_o[20] ,
\wbd_glbl_dat_o[19] ,
\wbd_glbl_dat_o[18] ,
\wbd_glbl_dat_o[17] ,
\wbd_glbl_dat_o[16] ,
\wbd_glbl_dat_o[15] ,
\wbd_glbl_dat_o[14] ,
\wbd_glbl_dat_o[13] ,
\wbd_glbl_dat_o[12] ,
\wbd_glbl_dat_o[11] ,
\wbd_glbl_dat_o[10] ,
\wbd_glbl_dat_o[9] ,
\wbd_glbl_dat_o[8] ,
\wbd_glbl_dat_o[7] ,
\wbd_glbl_dat_o[6] ,
\wbd_glbl_dat_o[5] ,
\wbd_glbl_dat_o[4] ,
\wbd_glbl_dat_o[3] ,
\wbd_glbl_dat_o[2] ,
\wbd_glbl_dat_o[1] ,
\wbd_glbl_dat_o[0] }),
.s2_wbd_sel_o({\wbd_glbl_sel_o[3] ,
\wbd_glbl_sel_o[2] ,
\wbd_glbl_sel_o[1] ,
\wbd_glbl_sel_o[0] }),
.s3_wbd_adr_o({\wbd_uart_adr_o[7] ,
\wbd_uart_adr_o[6] ,
\wbd_uart_adr_o[5] ,
\wbd_uart_adr_o[4] ,
\wbd_uart_adr_o[3] ,
\wbd_uart_adr_o[2] ,
\wbd_uart_adr_o[1] ,
\wbd_uart_adr_o[0] }),
.s3_wbd_dat_i({\wbd_uart_dat_i[31] ,
\wbd_uart_dat_i[30] ,
\wbd_uart_dat_i[29] ,
\wbd_uart_dat_i[28] ,
\wbd_uart_dat_i[27] ,
\wbd_uart_dat_i[