final gds oasis
diff --git a/gds/Core.gds.gz b/gds/Core.gds.gz
new file mode 100644
index 0000000..1141ef2
--- /dev/null
+++ b/gds/Core.gds.gz
Binary files differ
diff --git a/gds/Motor_Top.gds.gz b/gds/Motor_Top.gds.gz
new file mode 100644
index 0000000..0b3c413
--- /dev/null
+++ b/gds/Motor_Top.gds.gz
Binary files differ
diff --git a/gds/WB_InterConnect.gds.gz b/gds/WB_InterConnect.gds.gz
new file mode 100644
index 0000000..1177042
--- /dev/null
+++ b/gds/WB_InterConnect.gds.gz
Binary files differ
diff --git a/gds/user_proj_example.gds.gz b/gds/user_proj_example.gds.gz
new file mode 100644
index 0000000..97bc1f0
--- /dev/null
+++ b/gds/user_proj_example.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
new file mode 100644
index 0000000..58578dc
--- /dev/null
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/mpw_precheck/logs/gds.info b/mpw_precheck/logs/gds.info
new file mode 100644
index 0000000..4cdd8b7
--- /dev/null
+++ b/mpw_precheck/logs/gds.info
@@ -0,0 +1 @@
+user_project_wrapper.gds: 5dda8bbf359cfa2f0d51c3f3f3324383907d0bc0
\ No newline at end of file
diff --git a/mpw_precheck/logs/git.info b/mpw_precheck/logs/git.info
new file mode 100644
index 0000000..8059e39
--- /dev/null
+++ b/mpw_precheck/logs/git.info
@@ -0,0 +1,3 @@
+Repository: https://github.com/ee-uet/UETRV-ECORE.git
+Branch: ecore-dev
+Commit: 63707093d5fc606e8151e288d32070134f043aa7
diff --git a/mpw_precheck/logs/klayout_beol_check.log b/mpw_precheck/logs/klayout_beol_check.log
new file mode 100644
index 0000000..1393298
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.log
@@ -0,0 +1,992 @@
+/opt/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+Writing report database: /mnt/uffs/user/u7044_mtahir/design/uetrv-ecore/jobs/mpw_precheck/345b5aad-c406-4b35-b842-8361a0011a60/outputs/reports/klayout_beol_check.xml ..
+Total elapsed: 643.870s  Memory: 2562.00M
diff --git a/mpw_precheck/logs/klayout_beol_check.total b/mpw_precheck/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_feol_check.log b/mpw_precheck/logs/klayout_feol_check.log
new file mode 100644
index 0000000..0e3b280
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.log
@@ -0,0 +1,789 @@
+/opt/checks/tech-files/sky130A_mr.drc:36: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+FEOL section
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+Writing report database: /mnt/uffs/user/u7044_mtahir/design/uetrv-ecore/jobs/mpw_precheck/345b5aad-c406-4b35-b842-8361a0011a60/outputs/reports/klayout_feol_check.xml ..
+Total elapsed: 90.300s  Memory: 1446.00M
diff --git a/mpw_precheck/logs/klayout_feol_check.total b/mpw_precheck/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.log b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..daca16d
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
@@ -0,0 +1,79 @@
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+Writing report database: /mnt/uffs/user/u7044_mtahir/design/uetrv-ecore/jobs/mpw_precheck/345b5aad-c406-4b35-b842-8361a0011a60/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 37.720s  Memory: 928.00M
diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.total b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_offgrid_check.log b/mpw_precheck/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..22dae3b
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.log
@@ -0,0 +1,755 @@
+/opt/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+"output" in: sky130A_mr.drc:738
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"with_angle" in: sky130A_mr.drc:739
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.030s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:739
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1562.00M
+"ongrid" in: sky130A_mr.drc:740
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.870s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:740
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"with_angle" in: sky130A_mr.drc:741
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:741
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"ongrid" in: sky130A_mr.drc:742
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.310s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:742
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"with_angle" in: sky130A_mr.drc:743
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.030s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:743
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"ongrid" in: sky130A_mr.drc:744
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.140s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:744
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"with_angle" in: sky130A_mr.drc:745
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:745
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"ongrid" in: sky130A_mr.drc:746
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.270s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:746
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"with_angle" in: sky130A_mr.drc:747
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:747
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1562.00M
+"ongrid" in: sky130A_mr.drc:748
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.230s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:748
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"with_angle" in: sky130A_mr.drc:749
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:749
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"ongrid" in: sky130A_mr.drc:750
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.150s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:750
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"with_angle" in: sky130A_mr.drc:751
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:751
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1562.00M
+"ongrid" in: sky130A_mr.drc:752
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:752
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"with_angle" in: sky130A_mr.drc:753
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:753
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"ongrid" in: sky130A_mr.drc:754
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.140s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:754
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1562.00M
+"with_angle" in: sky130A_mr.drc:755
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:755
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"ongrid" in: sky130A_mr.drc:756
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.140s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:756
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"with_angle" in: sky130A_mr.drc:757
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:757
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"ongrid" in: sky130A_mr.drc:758
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.140s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:758
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"with_angle" in: sky130A_mr.drc:759
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:759
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"ongrid" in: sky130A_mr.drc:760
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.140s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:760
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1562.00M
+"with_angle" in: sky130A_mr.drc:761
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:761
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"ongrid" in: sky130A_mr.drc:762
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.140s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:762
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"with_angle" in: sky130A_mr.drc:763
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:763
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"ongrid" in: sky130A_mr.drc:764
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.140s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:764
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+"with_angle" in: sky130A_mr.drc:765
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:765
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1562.00M
+"ongrid" in: sky130A_mr.drc:766
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.130s  Memory: 1562.00M
+"output" in: sky130A_mr.drc:766
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1562.00M
+Writing report database: /mnt/uffs/user/u7044_mtahir/design/uetrv-ecore/jobs/mpw_precheck/345b5aad-c406-4b35-b842-8361a0011a60/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 95.190s  Memory: 1546.00M
diff --git a/mpw_precheck/logs/klayout_offgrid_check.total b/mpw_precheck/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..874796c
--- /dev/null
+++ b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/root/uetrv-ecore/gds/user_project_wrapper.gds, topcell=user_project_wrapper, output to /mnt/uffs/user/u7044_mtahir/design/uetrv-ecore/jobs/mpw_precheck/345b5aad-c406-4b35-b842-8361a0011a60/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+  deep:true tiled:false threads:32
+--- #err|description, table for cell: user_project_wrapper
+NO-Check ----        pwell:64/44/EMP   122/16/dat    64/59/EMP    44/16/EMP     44/5/EMP
+         ----        nwell:64/20/dat    64/16/dat     64/5/EMP
+         ----         diff:65/20/dat    65/16/EMP     65/6/EMP
+         ----          tap:65/44/dat    65/48/EMP     65/5/EMP
+         ----         poly:66/20/dat    66/16/EMP     66/5/EMP
+         ----       licon1:66/44/dat    66/58/EMP
+         ----          li1:67/20/dat    67/16/dat     67/5/EMP
+         ----         mcon:67/44/dat    67/48/EMP
+         ----         met1:68/20/dat    68/16/dat     68/5/dat
+         ----          via:68/44/dat    68/58/EMP
+         ----         met2:69/20/dat    69/16/dat     69/5/dat
+         ----         via2:69/44/dat    69/58/EMP
+         ----         met3:70/20/dat    70/16/dat     70/5/dat
+         ----         via3:70/44/dat    70/48/EMP
+         ----         met4:71/20/dat    71/16/dat     71/5/dat
+         ----         via4:71/44/dat    71/48/EMP
+         ----         met5:72/20/dat    72/16/dat     72/5/EMP
+         ----          pad:76/20/EMP     76/5/EMP    76/16/EMP
+         ----          pnp:82/44/EMP    82/59/EMP
+         ----          npn:82/20/EMP     82/5/EMP
+         ----          rdl:74/20/EMP    74/16/EMP     74/5/EMP
+         ----     inductor:82/24/EMP    82/25/EMP
+       0 total error(s) among 0 error type(s), 33 checks, cell: user_project_wrapper
+Writing report...
+VmPeak:	 5780996 kB
+VmHWM:	  699620 kB
diff --git a/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_zeroarea_check.log b/mpw_precheck/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..1a8d592
--- /dev/null
+++ b/mpw_precheck/logs/klayout_zeroarea_check.log
@@ -0,0 +1,4 @@
+0 zero-area shapes
+writing to /mnt/uffs/user/u7044_mtahir/design/uetrv-ecore/jobs/mpw_precheck/345b5aad-c406-4b35-b842-8361a0011a60/outputs/user_project_wrapper_no_zero_areas.gds
+VmPeak:	  955444 kB
+VmHWM:	  663744 kB
diff --git a/mpw_precheck/logs/klayout_zeroarea_check.total b/mpw_precheck/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/magic_drc_check.log b/mpw_precheck/logs/magic_drc_check.log
new file mode 100644
index 0000000..356f540
--- /dev/null
+++ b/mpw_precheck/logs/magic_drc_check.log
@@ -0,0 +1,477 @@
+
+Magic 8.3 revision 274 - Compiled on Fri Mar  4 22:53:06 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    mvobsactive ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Detected an SRAM module
+Pre-loading a maglef of the SRAM block: sky130_sram_2kbyte_1rw1r_32x512_8
+Scaled magic input cell sky130_sram_2kbyte_1rw1r_32x512_8 geometry by factor of 2
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620068): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620772): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2621732): Unknown layer/datatype in boundary, layer=22 type=21
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3113978): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3117754): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3121946): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3126746): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3128794): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3308236): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3312012): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3316204): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3322668): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3324844): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3565294): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3569070): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3573262): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3579726): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3581902): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+Warning:  cell sky130_sram_2kbyte_1rw1r_32x512_8 already existed before reading GDS!
+Using pre-existing cell definition
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__o32ai_4".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__nor2b_2".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__nor2b_4".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__nor2b_1".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__o311ai_4".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__a2bb2oi_2".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "Motor_Top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__a311oi_4".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__o2bb2a_4".
+Reading "sky130_fd_sc_hd__o21ba_4".
+Reading "WB_InterConnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+    100000 uses
+    105000 uses
+    110000 uses
+    115000 uses
+    120000 uses
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__a311o_4".
+Reading "sky130_fd_sc_hd__o311a_4".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__o311ai_1".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "Core".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+Reading "user_project_wrapper".
+[INFO]: Loading user_project_wrapper
+
+DRC style is now "drc(full)"
+Loading DRC CIF style.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/mnt/uffs/user/u7044_mtahir/design/uetrv-ecore/jobs/mpw_precheck/345b5aad-c406-4b35-b842-8361a0011a60/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/mnt/uffs/user/u7044_mtahir/design/uetrv-ecore/jobs/mpw_precheck/345b5aad-c406-4b35-b842-8361a0011a60/outputs/user_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/mpw_precheck/logs/magic_drc_check.total b/mpw_precheck/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/pdks.info b/mpw_precheck/logs/pdks.info
new file mode 100644
index 0000000..19f87e1
--- /dev/null
+++ b/mpw_precheck/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs 27ecf1c16911f7dd4428ffab96f62c1fb876ea70
+Skywater PDK c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
\ No newline at end of file
diff --git a/mpw_precheck/logs/precheck.log b/mpw_precheck/logs/precheck.log
new file mode 100644
index 0000000..85fc243
--- /dev/null
+++ b/mpw_precheck/logs/precheck.log
@@ -0,0 +1,65 @@
+2022-04-29 16:07:28 - [INFO] - {{Project Git Info}} Repository: https://github.com/ee-uet/UETRV-ECORE.git | Branch: ecore-dev | Commit: 63707093d5fc606e8151e288d32070134f043aa7
+2022-04-29 16:07:28 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: uetrv-ecore
+2022-04-29 16:07:28 - [INFO] - {{Project Type Info}} digital
+2022-04-29 16:07:28 - [INFO] - {{Project GDS Info}} user_project_wrapper: 5dda8bbf359cfa2f0d51c3f3f3324383907d0bc0
+2022-04-29 16:07:28 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
+2022-04-29 16:07:28 - [INFO] - {{PDKs Info}} Open PDKs: 27ecf1c16911f7dd4428ffab96f62c1fb876ea70 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+2022-04-29 16:07:28 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'uetrv-ecore/jobs/mpw_precheck/345b5aad-c406-4b35-b842-8361a0011a60/logs'
+2022-04-29 16:07:28 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-04-29 16:07:28 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2022-04-29 16:07:29 - [INFO] - An approved LICENSE (Apache-2.0) was found in uetrv-ecore.
+2022-04-29 16:07:29 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-04-29 16:07:30 - [INFO] - An approved LICENSE (Apache-2.0) was found in uetrv-ecore.
+2022-04-29 16:07:30 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-04-29 16:07:30 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in uetrv-ecore/openlane/Makefile
+2022-04-29 16:07:31 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 52 non-compliant file(s) with the SPDX Standard.
+2022-04-29 16:07:31 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['uetrv-ecore/Makefile', 'uetrv-ecore/docs/Makefile', 'uetrv-ecore/docs/environment.yml', 'uetrv-ecore/docs/source/conf.py', 'uetrv-ecore/docs/source/index.rst', 'uetrv-ecore/docs/source/quickstart.rst', 'uetrv-ecore/gds/(UNNAMED).ext', 'uetrv-ecore/mag/tmp/extract_BMem.tcl', 'uetrv-ecore/openlane/Core/config.tcl', 'uetrv-ecore/openlane/Motor_Top/config.tcl', 'uetrv-ecore/openlane/Wishbone_InterConnect/config.tcl', 'uetrv-ecore/openlane/user_proj_example/config.json', 'uetrv-ecore/openlane/user_proj_example/config.tcl', 'uetrv-ecore/openlane/user_project_wrapper/config.json', 'uetrv-ecore/openlane/user_project_wrapper/config.tcl']
+2022-04-29 16:07:31 - [INFO] - For the full SPDX compliance report check: uetrv-ecore/jobs/mpw_precheck/345b5aad-c406-4b35-b842-8361a0011a60/logs/spdx_compliance_report.log
+2022-04-29 16:07:31 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2022-04-29 16:07:31 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-04-29 16:07:31 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2022-04-29 16:07:31 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-04-29 16:07:32 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-04-29 16:07:32 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2022-04-29 16:07:32 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-04-29 16:07:32 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
+2022-04-29 16:07:37 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel. 
+2022-04-29 16:07:37 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (90 instances). 
+2022-04-29 16:07:37 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
+2022-04-29 16:07:37 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
+2022-04-29 16:07:37 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
+2022-04-29 16:07:37 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
+2022-04-29 16:07:37 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
+2022-04-29 16:07:37 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (7 instances). 
+2022-04-29 16:07:37 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
+2022-04-29 16:07:37 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
+2022-04-29 16:07:37 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
+2022-04-29 16:07:37 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
+2022-04-29 16:07:37 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
+2022-04-29 16:07:38 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
+2022-04-29 16:07:38 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
+2022-04-29 16:08:56 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view uetrv-ecore/jobs/mpw_precheck/345b5aad-c406-4b35-b842-8361a0011a60/outputs/user_project_wrapper.xor.gds
+2022-04-29 16:08:56 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
+2022-04-29 16:08:56 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
+2022-04-29 16:20:11 - [INFO] - 0 DRC violations
+2022-04-29 16:20:11 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-04-29 16:20:11 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
+2022-04-29 16:21:34 - [INFO] - No DRC Violations found
+2022-04-29 16:21:34 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-04-29 16:21:34 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
+2022-04-29 16:29:35 - [INFO] - No DRC Violations found
+2022-04-29 16:29:35 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-04-29 16:29:35 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
+2022-04-29 16:31:12 - [INFO] - No DRC Violations found
+2022-04-29 16:31:12 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-04-29 16:31:12 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
+2022-04-29 16:31:51 - [INFO] - No DRC Violations found
+2022-04-29 16:31:51 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-04-29 16:31:51 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
+2022-04-29 16:32:12 - [INFO] - No DRC Violations found
+2022-04-29 16:32:12 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-04-29 16:32:12 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
+2022-04-29 16:32:18 - [INFO] - No DRC Violations found
+2022-04-29 16:32:18 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-04-29 16:32:18 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'uetrv-ecore/jobs/mpw_precheck/345b5aad-c406-4b35-b842-8361a0011a60/logs'
+2022-04-29 16:32:18 - [INFO] - {{SUCCESS}} All Checks Passed !!!
diff --git a/mpw_precheck/logs/spdx_compliance_report.log b/mpw_precheck/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..daca088
--- /dev/null
+++ b/mpw_precheck/logs/spdx_compliance_report.log
@@ -0,0 +1,52 @@
+/root/uetrv-ecore/Makefile
+/root/uetrv-ecore/docs/Makefile
+/root/uetrv-ecore/docs/environment.yml
+/root/uetrv-ecore/docs/source/conf.py
+/root/uetrv-ecore/docs/source/index.rst
+/root/uetrv-ecore/docs/source/quickstart.rst
+/root/uetrv-ecore/gds/(UNNAMED).ext
+/root/uetrv-ecore/mag/tmp/extract_BMem.tcl
+/root/uetrv-ecore/openlane/Core/config.tcl
+/root/uetrv-ecore/openlane/Motor_Top/config.tcl
+/root/uetrv-ecore/openlane/Wishbone_InterConnect/config.tcl
+/root/uetrv-ecore/openlane/user_proj_example/config.json
+/root/uetrv-ecore/openlane/user_proj_example/config.tcl
+/root/uetrv-ecore/openlane/user_project_wrapper/config.json
+/root/uetrv-ecore/openlane/user_project_wrapper/config.tcl
+/root/uetrv-ecore/sdc/Core.sdc
+/root/uetrv-ecore/sdc/Motor_Top.sdc
+/root/uetrv-ecore/sdc/WB_InterConnect.sdc
+/root/uetrv-ecore/sdc/user_proj_example.sdc
+/root/uetrv-ecore/sdc/user_project_wrapper.sdc
+/root/uetrv-ecore/sdf/Core.sdf
+/root/uetrv-ecore/sdf/Motor_Top.sdf
+/root/uetrv-ecore/sdf/WB_InterConnect.sdf
+/root/uetrv-ecore/sdf/user_proj_example.sdf
+/root/uetrv-ecore/sdf/user_project_wrapper.sdf
+/root/uetrv-ecore/spef/Core.spef
+/root/uetrv-ecore/spef/Motor_Top.spef
+/root/uetrv-ecore/spef/WB_InterConnect.spef
+/root/uetrv-ecore/spef/user_proj_example.spef
+/root/uetrv-ecore/spef/user_project_wrapper.spef
+/root/uetrv-ecore/verilog/dv/Makefile
+/root/uetrv-ecore/verilog/dv/io_ports/Makefile
+/root/uetrv-ecore/verilog/dv/io_ports/io_ports.c
+/root/uetrv-ecore/verilog/dv/io_ports/io_ports_tb.v
+/root/uetrv-ecore/verilog/dv/la_test1/Makefile
+/root/uetrv-ecore/verilog/dv/la_test1/la_test1.c
+/root/uetrv-ecore/verilog/dv/la_test1/la_test1_tb.v
+/root/uetrv-ecore/verilog/dv/la_test2/Makefile
+/root/uetrv-ecore/verilog/dv/la_test2/la_test2.c
+/root/uetrv-ecore/verilog/dv/la_test2/la_test2_tb.v
+/root/uetrv-ecore/verilog/dv/mprj_stimulus/Makefile
+/root/uetrv-ecore/verilog/dv/mprj_stimulus/mprj_stimulus.c
+/root/uetrv-ecore/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
+/root/uetrv-ecore/verilog/dv/wb_port/Makefile
+/root/uetrv-ecore/verilog/dv/wb_port/wb_port.c
+/root/uetrv-ecore/verilog/dv/wb_port/wb_port_tb.v
+/root/uetrv-ecore/verilog/rtl/Core.v
+/root/uetrv-ecore/verilog/rtl/Motor_Top.v
+/root/uetrv-ecore/verilog/rtl/WB_InterConnect.v
+/root/uetrv-ecore/verilog/rtl/uprj_netlists.v
+/root/uetrv-ecore/verilog/rtl/user_proj_example.v
+/root/uetrv-ecore/verilog/rtl/user_project_wrapper.v
diff --git a/mpw_precheck/logs/tools.info b/mpw_precheck/logs/tools.info
new file mode 100644
index 0000000..9b2230a
--- /dev/null
+++ b/mpw_precheck/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.8
+Magic: 8.3.274
\ No newline at end of file
diff --git a/mpw_precheck/logs/xor_check.log b/mpw_precheck/logs/xor_check.log
new file mode 100644
index 0000000..d0b56f6
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.log
@@ -0,0 +1,629 @@
+Reading file /root/uetrv-ecore/gds/user_project_wrapper.gds for cell user_project_wrapper
+dbu=0.001
+cell user_project_wrapper dbu-bbox(ll;ur)=(-43630,-38270;2963250,3557950)
+cell user_project_wrapper dbu-bbox(left,bottom,right,top)=(-43630,-38270,2963250,3557950)
+cell user_project_wrapper dbu-size(width,height)=(3006880,3596220)
+cell user_project_wrapper micron-bbox(left,bottom,right,top)=(-43.63,-38.27,2963.25,3557.9500000000003)
+cell user_project_wrapper micron-size(width,height)=(3006.88,3596.2200000000003)
+Done.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar  4 22:53:06 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    mvobsactive ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620068): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620772): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2621732): Unknown layer/datatype in boundary, layer=22 type=21
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3113978): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3117754): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3121946): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3126746): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3128794): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3308236): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3312012): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3316204): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3322668): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3324844): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3565294): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3569070): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3573262): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3579726): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3581902): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+    5000 uses
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__o32ai_4".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__nor2b_2".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__nor2b_4".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__nor2b_1".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__o311ai_4".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__a2bb2oi_2".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "Motor_Top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__a311oi_4".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__o2bb2a_4".
+Reading "sky130_fd_sc_hd__o21ba_4".
+Reading "WB_InterConnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+    90000 uses
+    95000 uses
+    100000 uses
+    105000 uses
+    110000 uses
+    115000 uses
+    120000 uses
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__a311o_4".
+Reading "sky130_fd_sc_hd__o311a_4".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__o311ai_1".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "Core".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+Reading "user_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.880 x 3520.000  (-42.880,  0.000), ( 0.000,  3520.000)  150937.594
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.500 x 3520.000  ( 2920.000,  0.000), ( 2962.500,  3520.000)  149600.000
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.530  (-42.880, -37.530), ( 2962.500,  0.000)  112791.906
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.210  (-42.880,  3520.000), ( 2962.500,  3557.210)  111830.188
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+
+Magic 8.3 revision 274 - Compiled on Fri Mar  4 22:53:06 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    mvobsactive ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "user_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.880 x 3520.000  (-42.880,  0.000), ( 0.000,  3520.000)  150937.594
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.500 x 3520.000  ( 2920.000,  0.000), ( 2962.500,  3520.000)  149600.000
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.530  (-42.880, -37.530), ( 2962.500,  0.000)  112791.906
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.210  (-42.880,  3520.000), ( 2962.500,  3557.210)  111830.188
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+Reading /mnt/uffs/user/u7044_mtahir/design/uetrv-ecore/jobs/mpw_precheck/345b5aad-c406-4b35-b842-8361a0011a60/outputs/user_project_wrapper_erased.gds ..
+Reading /mnt/uffs/user/u7044_mtahir/design/uetrv-ecore/jobs/mpw_precheck/345b5aad-c406-4b35-b842-8361a0011a60/outputs/user_project_wrapper_empty_erased.gds ..
+--- Running XOR for 69/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 530 (flat)  530 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 530 (flat)  530 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+--- Running XOR for 70/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 107 (flat)  107 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 107 (flat)  107 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+--- Running XOR for 71/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+--- Running XOR for 71/44 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 116 (flat)  116 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 116 (flat)  116 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+--- Running XOR for 72/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+--- Running XOR for 81/14 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+Writing layout file: /mnt/uffs/user/u7044_mtahir/design/uetrv-ecore/jobs/mpw_precheck/345b5aad-c406-4b35-b842-8361a0011a60/outputs/user_project_wrapper.xor.gds ..
+Total elapsed: 0.120s  Memory: 523.00M
diff --git a/mpw_precheck/logs/xor_check.total b/mpw_precheck/logs/xor_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/outputs/reports/klayout_beol_check.xml b/mpw_precheck/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..5ffd971
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>li.1</name>
+   <description>li.1 : min. li width : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3</name>
+   <description>li.3 : min. li spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.5</name>
+   <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.6</name>
+   <description>li.6 : min. li area : 0.0561um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1</name>
+   <description>ct.1: non-ring mcon should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_a</name>
+   <description>ct.1_a : minimum width of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_b</name>
+   <description>ct.1_b : maximum length of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.2</name>
+   <description>ct.2 : min. mcon spacing : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.4</name>
+   <description>ct.4 : mcon should covered by li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.1</name>
+   <description>m1.1 : min. m1 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.2</name>
+   <description>m1.2 : min. m1 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.3ab</name>
+   <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>791_m1.4</name>
+   <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4</name>
+   <description>m1.4 : mcon periphery must be enclosed by m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a</name>
+   <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a_a</name>
+   <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.6</name>
+   <description>m1.6 : min. m1 area : 0.083um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.7</name>
+   <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.5</name>
+   <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a</name>
+   <description>via.1a : via outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_a</name>
+   <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_b</name>
+   <description>via.1a_b : maximum length of via : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.2</name>
+   <description>via.2 : min. via spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a</name>
+   <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a_a</name>
+   <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.5a</name>
+   <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.1</name>
+   <description>m2.1 : min. m2 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.2</name>
+   <description>m2.2 : min. m2 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.3ab</name>
+   <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.6</name>
+   <description>m2.6 : min. m2 area : 0.0676um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.7</name>
+   <description>m2.7 : min. m2 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4</name>
+   <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4_a</name>
+   <description>m2.4_a : via in periphery must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.5</name>
+   <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a</name>
+   <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_a</name>
+   <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_b</name>
+   <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.2</name>
+   <description>via2.2 : min. via2 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4</name>
+   <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4_a</name>
+   <description>via2.4_a : via must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.5</name>
+   <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.1</name>
+   <description>m3.1 : min. m3 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.2</name>
+   <description>m3.2 : min. m3 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.3cd</name>
+   <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4</name>
+   <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4_a</name>
+   <description>m3.4_a : via2 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1</name>
+   <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_a</name>
+   <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_b</name>
+   <description>via3.1_b : maximum length of via3 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.2</name>
+   <description>via3.2 : min. via3 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4</name>
+   <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4_a</name>
+   <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.5</name>
+   <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.1</name>
+   <description>m4.1 : min. m4 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.2</name>
+   <description>m4.2 : min. m4 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.4a</name>
+   <description>m4.4a : min. m4 area : 0.240um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.5ab</name>
+   <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3</name>
+   <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3_a</name>
+   <description>m4.3_a : via3 must be enclosed by met4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1</name>
+   <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_a</name>
+   <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_b</name>
+   <description>via4.1_b : maximum length of via4 : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.2</name>
+   <description>via4.2 : min. via4 spacing : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4</name>
+   <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4_a</name>
+   <description>via4.4_a : m4 must enclose all via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.1</name>
+   <description>m5.1 : min. m5 width : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.2</name>
+   <description>m5.2 : min. m5 spacing : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3</name>
+   <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3_a</name>
+   <description>m5.3_a : via must be enclosed by m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.4</name>
+   <description>m5.4 : min. m5 area : 4.0um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad.2</name>
+   <description>pad.2 : min. pad spacing : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_feol_check.xml b/mpw_precheck/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..987027f
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,363 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell.2</name>
+   <description>dnwell.2 : min. dnwell width : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.1</name>
+   <description>nwell.1 : min. nwell width : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.2a</name>
+   <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.6</name>
+   <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.1</name>
+   <description>hvtp.1 : min. hvtp width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.2</name>
+   <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.1</name>
+   <description>hvtr.1 : min. hvtr width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2</name>
+   <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2_a</name>
+   <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.1a</name>
+   <description>lvtn.1a : min. lvtn width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.2</name>
+   <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.1</name>
+   <description>ncm.1 : min. ncm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.2a</name>
+   <description>ncm.2a : min. ncm spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1</name>
+   <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_a</name>
+   <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_b</name>
+   <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_c</name>
+   <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.3</name>
+   <description>difftap.3 : min. difftap spacing : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.1</name>
+   <description>tunm.1 : min. tunm width : 0.41um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.2</name>
+   <description>tunm.2 : min. tunm spacing : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.1a</name>
+   <description>poly.1a : min. poly width : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.2</name>
+   <description>poly.2 : min. poly spacing : 0.21um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.1a</name>
+   <description>rpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.2</name>
+   <description>rpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.1a</name>
+   <description>urpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.2</name>
+   <description>urpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.1</name>
+   <description>npc.1 : min. npc width : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.2</name>
+   <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.1</name>
+   <description>nsd.1 : min. nsdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.2</name>
+   <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.1</name>
+   <description>psd.1 : min. psdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.2</name>
+   <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1</name>
+   <description>licon.1 : licon should be rectangle</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1_a/b</name>
+   <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13</name>
+   <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13_a</name>
+   <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.17</name>
+   <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.1</name>
+   <description>capm.1 : min. capm width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2a</name>
+   <description>capm.2a : min. capm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b</name>
+   <description>capm.2b : min. capm spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b_a</name>
+   <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3</name>
+   <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3_a</name>
+   <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.4</name>
+   <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.5</name>
+   <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.1</name>
+   <description>cap2m.1 : min. cap2m width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2a</name>
+   <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b</name>
+   <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b_a</name>
+   <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3</name>
+   <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3_a</name>
+   <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.4</name>
+   <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.5</name>
+   <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.1</name>
+   <description>hvi.1 : min. hvi width : 0.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.2a</name>
+   <description>hvi.2a : min. hvi spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.1</name>
+   <description>hvntm.1 : min. hvntm width : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.2</name>
+   <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..698a39a
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_offgrid_check.xml b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..95ebbc9
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_angle</name>
+   <description>x.3a : non 45 degree angle dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_angle</name>
+   <description>x.3a : non 45 degree angle nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_angle</name>
+   <description>x.3a : non 45 degree angle pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_angle</name>
+   <description>x.3a : non 45 degree angle pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_angle</name>
+   <description>x.3a : non 45 degree angle hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_angle</name>
+   <description>x.3a : non 45 degree angle hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_angle</name>
+   <description>x.3a : non 45 degree angle lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_angle</name>
+   <description>x.3a : non 45 degree angle ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2 : non 90 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2c : non 45 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2 : non 90 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2c : non 45 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_angle</name>
+   <description>x.3a : non 45 degree angle tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_angle</name>
+   <description>x.2 : non 90 degree angle poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_angle</name>
+   <description>x.3a : non 45 degree angle rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_angle</name>
+   <description>x.3a : non 45 degree angle npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_angle</name>
+   <description>x.3a : non 45 degree angle nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_angle</name>
+   <description>x.3a : non 45 degree angle psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_angle</name>
+   <description>x.2 : non 90 degree angle licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_angle</name>
+   <description>x.3a : non 45 degree angle li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_angle</name>
+   <description>x.2 : non 90 degree angle mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_angle</name>
+   <description>x.3a : non 45 degree angle vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_angle</name>
+   <description>x.3a : non 45 degree angle m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_angle</name>
+   <description>x.2 : non 90 degree angle via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_angle</name>
+   <description>x.3a : non 45 degree angle m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_angle</name>
+   <description>x.2 : non 90 degree angle via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_angle</name>
+   <description>x.3a : non 45 degree angle m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_angle</name>
+   <description>x.2 : non 90 degree angle via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_angle</name>
+   <description>x.3a : non 45 degree angle nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_angle</name>
+   <description>x.3a : non 45 degree angle m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_angle</name>
+   <description>x.2 : non 90 degree angle via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_angle</name>
+   <description>x.3a : non 45 degree angle m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_angle</name>
+   <description>x.3a : non 45 degree angle pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_angle</name>
+   <description>x.2 : non 90 degree angle mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_angle</name>
+   <description>x.3a : non 45 degree angle hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_angle</name>
+   <description>x.3a : non 45 degree angle hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_angle</name>
+   <description>x.3a : non 45 degree angle vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_angle</name>
+   <description>x.3a : non 45 degree angle uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_angle</name>
+   <description>x.3a : non 45 degree angle pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>areaid_re_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on areaid.re</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..8593fd3
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/root/uetrv-ecore/gds/user_project_wrapper.gds, topcell=user_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml b/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..7f95f69
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.drc.report b/mpw_precheck/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..46ca7f3
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.rdb b/mpw_precheck/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..ac5b3c4
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_project_wrapper
+ 100
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.tcl b/mpw_precheck/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.tcl
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.tr b/mpw_precheck/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.tr
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.xml b/mpw_precheck/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..0eff265
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+    <categories/>
+    <cells>
+        <cell>
+            <name>user_project_wrapper</name>
+        </cell>
+    </cells>
+    <items/>
+</report-database>
diff --git a/mpw_precheck/outputs/user_project_wrapper.filtered.v b/mpw_precheck/outputs/user_project_wrapper.filtered.v
new file mode 100644
index 0000000..0755d16
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.filtered.v
@@ -0,0 +1,1804 @@
+module user_project_wrapper (user_clock2,
+    vccd1,
+    vccd2,
+    vdda1,
+    vdda2,
+    vssa1,
+    vssa2,
+    vssd1,
+    vssd2,
+    wb_clk_i,
+    wb_rst_i,
+    wbs_ack_o,
+    wbs_cyc_i,
+    wbs_stb_i,
+    wbs_we_i,
+    analog_io,
+    io_in,
+    io_oeb,
+    io_out,
+    la_data_in,
+    la_data_out,
+    la_oenb,
+    user_irq,
+    wbs_adr_i,
+    wbs_dat_i,
+    wbs_dat_o,
+    wbs_sel_i);
+ input user_clock2;
+ input vccd1;
+ input vccd2;
+ input vdda1;
+ input vdda2;
+ input vssa1;
+ input vssa2;
+ input vssd1;
+ input vssd2;
+ input wb_clk_i;
+ input wb_rst_i;
+ output wbs_ack_o;
+ input wbs_cyc_i;
+ input wbs_stb_i;
+ input wbs_we_i;
+ inout [28:0] analog_io;
+ input [37:0] io_in;
+ output [37:0] io_oeb;
+ output [37:0] io_out;
+ input [127:0] la_data_in;
+ output [127:0] la_data_out;
+ input [127:0] la_oenb;
+ output [2:0] user_irq;
+ input [31:0] wbs_adr_i;
+ input [31:0] wbs_dat_i;
+ output [31:0] wbs_dat_o;
+ input [3:0] wbs_sel_i;
+
+ wire io_spi_cs_en;
+ wire io_spi_clk_en;
+ wire io_spi_mosi_en;
+ wire io_m1_io_pwm_high_en;
+ wire io_m1_io_pwm_low_en;
+ wire io_m2_io_pwm_high_en;
+ wire io_m2_io_pwm_low_en;
+ wire io_m3_io_pwm_high_en;
+ wire io_m3_io_pwm_low_en;
+ wire io_uart_tx;
+ wire io_spi_cs;
+ wire io_spi_clk;
+ wire io_spi_mosi;
+ wire io_m1_io_pwm_high;
+ wire io_m1_io_pwm_low;
+ wire io_m2_io_pwm_high;
+ wire io_m2_io_pwm_low;
+ wire io_m3_io_pwm_high;
+ wire io_m3_io_pwm_low;
+ wire \core_io_dbus_addr[0] ;
+ wire \core_io_dbus_addr[10] ;
+ wire \core_io_dbus_addr[11] ;
+ wire \core_io_dbus_addr[12] ;
+ wire \core_io_dbus_addr[13] ;
+ wire \core_io_dbus_addr[14] ;
+ wire \core_io_dbus_addr[15] ;
+ wire \core_io_dbus_addr[16] ;
+ wire \core_io_dbus_addr[17] ;
+ wire \core_io_dbus_addr[18] ;
+ wire \core_io_dbus_addr[19] ;
+ wire \core_io_dbus_addr[1] ;
+ wire \core_io_dbus_addr[20] ;
+ wire \core_io_dbus_addr[21] ;
+ wire \core_io_dbus_addr[22] ;
+ wire \core_io_dbus_addr[23] ;
+ wire \core_io_dbus_addr[24] ;
+ wire \core_io_dbus_addr[25] ;
+ wire \core_io_dbus_addr[26] ;
+ wire \core_io_dbus_addr[27] ;
+ wire \core_io_dbus_addr[28] ;
+ wire \core_io_dbus_addr[29] ;
+ wire \core_io_dbus_addr[2] ;
+ wire \core_io_dbus_addr[30] ;
+ wire \core_io_dbus_addr[31] ;
+ wire \core_io_dbus_addr[3] ;
+ wire \core_io_dbus_addr[4] ;
+ wire \core_io_dbus_addr[5] ;
+ wire \core_io_dbus_addr[6] ;
+ wire \core_io_dbus_addr[7] ;
+ wire \core_io_dbus_addr[8] ;
+ wire \core_io_dbus_addr[9] ;
+ wire \core_io_dbus_ld_type[0] ;
+ wire \core_io_dbus_ld_type[1] ;
+ wire \core_io_dbus_ld_type[2] ;
+ wire core_io_dbus_rd_en;
+ wire \core_io_dbus_rdata[0] ;
+ wire \core_io_dbus_rdata[10] ;
+ wire \core_io_dbus_rdata[11] ;
+ wire \core_io_dbus_rdata[12] ;
+ wire \core_io_dbus_rdata[13] ;
+ wire \core_io_dbus_rdata[14] ;
+ wire \core_io_dbus_rdata[15] ;
+ wire \core_io_dbus_rdata[16] ;
+ wire \core_io_dbus_rdata[17] ;
+ wire \core_io_dbus_rdata[18] ;
+ wire \core_io_dbus_rdata[19] ;
+ wire \core_io_dbus_rdata[1] ;
+ wire \core_io_dbus_rdata[20] ;
+ wire \core_io_dbus_rdata[21] ;
+ wire \core_io_dbus_rdata[22] ;
+ wire \core_io_dbus_rdata[23] ;
+ wire \core_io_dbus_rdata[24] ;
+ wire \core_io_dbus_rdata[25] ;
+ wire \core_io_dbus_rdata[26] ;
+ wire \core_io_dbus_rdata[27] ;
+ wire \core_io_dbus_rdata[28] ;
+ wire \core_io_dbus_rdata[29] ;
+ wire \core_io_dbus_rdata[2] ;
+ wire \core_io_dbus_rdata[30] ;
+ wire \core_io_dbus_rdata[31] ;
+ wire \core_io_dbus_rdata[3] ;
+ wire \core_io_dbus_rdata[4] ;
+ wire \core_io_dbus_rdata[5] ;
+ wire \core_io_dbus_rdata[6] ;
+ wire \core_io_dbus_rdata[7] ;
+ wire \core_io_dbus_rdata[8] ;
+ wire \core_io_dbus_rdata[9] ;
+ wire \core_io_dbus_st_type[0] ;
+ wire \core_io_dbus_st_type[1] ;
+ wire core_io_dbus_valid;
+ wire \core_io_dbus_wdata[0] ;
+ wire \core_io_dbus_wdata[10] ;
+ wire \core_io_dbus_wdata[11] ;
+ wire \core_io_dbus_wdata[12] ;
+ wire \core_io_dbus_wdata[13] ;
+ wire \core_io_dbus_wdata[14] ;
+ wire \core_io_dbus_wdata[15] ;
+ wire \core_io_dbus_wdata[16] ;
+ wire \core_io_dbus_wdata[17] ;
+ wire \core_io_dbus_wdata[18] ;
+ wire \core_io_dbus_wdata[19] ;
+ wire \core_io_dbus_wdata[1] ;
+ wire \core_io_dbus_wdata[20] ;
+ wire \core_io_dbus_wdata[21] ;
+ wire \core_io_dbus_wdata[22] ;
+ wire \core_io_dbus_wdata[23] ;
+ wire \core_io_dbus_wdata[24] ;
+ wire \core_io_dbus_wdata[25] ;
+ wire \core_io_dbus_wdata[26] ;
+ wire \core_io_dbus_wdata[27] ;
+ wire \core_io_dbus_wdata[28] ;
+ wire \core_io_dbus_wdata[29] ;
+ wire \core_io_dbus_wdata[2] ;
+ wire \core_io_dbus_wdata[30] ;
+ wire \core_io_dbus_wdata[31] ;
+ wire \core_io_dbus_wdata[3] ;
+ wire \core_io_dbus_wdata[4] ;
+ wire \core_io_dbus_wdata[5] ;
+ wire \core_io_dbus_wdata[6] ;
+ wire \core_io_dbus_wdata[7] ;
+ wire \core_io_dbus_wdata[8] ;
+ wire \core_io_dbus_wdata[9] ;
+ wire core_io_dbus_wr_en;
+ wire \core_io_ibus_addr[0] ;
+ wire \core_io_ibus_addr[10] ;
+ wire \core_io_ibus_addr[11] ;
+ wire \core_io_ibus_addr[12] ;
+ wire \core_io_ibus_addr[13] ;
+ wire \core_io_ibus_addr[14] ;
+ wire \core_io_ibus_addr[15] ;
+ wire \core_io_ibus_addr[16] ;
+ wire \core_io_ibus_addr[17] ;
+ wire \core_io_ibus_addr[18] ;
+ wire \core_io_ibus_addr[19] ;
+ wire \core_io_ibus_addr[1] ;
+ wire \core_io_ibus_addr[20] ;
+ wire \core_io_ibus_addr[21] ;
+ wire \core_io_ibus_addr[22] ;
+ wire \core_io_ibus_addr[23] ;
+ wire \core_io_ibus_addr[24] ;
+ wire \core_io_ibus_addr[25] ;
+ wire \core_io_ibus_addr[26] ;
+ wire \core_io_ibus_addr[27] ;
+ wire \core_io_ibus_addr[28] ;
+ wire \core_io_ibus_addr[29] ;
+ wire \core_io_ibus_addr[2] ;
+ wire \core_io_ibus_addr[30] ;
+ wire \core_io_ibus_addr[31] ;
+ wire \core_io_ibus_addr[3] ;
+ wire \core_io_ibus_addr[4] ;
+ wire \core_io_ibus_addr[5] ;
+ wire \core_io_ibus_addr[6] ;
+ wire \core_io_ibus_addr[7] ;
+ wire \core_io_ibus_addr[8] ;
+ wire \core_io_ibus_addr[9] ;
+ wire \core_io_ibus_inst[0] ;
+ wire \core_io_ibus_inst[10] ;
+ wire \core_io_ibus_inst[11] ;
+ wire \core_io_ibus_inst[12] ;
+ wire \core_io_ibus_inst[13] ;
+ wire \core_io_ibus_inst[14] ;
+ wire \core_io_ibus_inst[15] ;
+ wire \core_io_ibus_inst[16] ;
+ wire \core_io_ibus_inst[17] ;
+ wire \core_io_ibus_inst[18] ;
+ wire \core_io_ibus_inst[19] ;
+ wire \core_io_ibus_inst[1] ;
+ wire \core_io_ibus_inst[20] ;
+ wire \core_io_ibus_inst[21] ;
+ wire \core_io_ibus_inst[22] ;
+ wire \core_io_ibus_inst[23] ;
+ wire \core_io_ibus_inst[24] ;
+ wire \core_io_ibus_inst[25] ;
+ wire \core_io_ibus_inst[26] ;
+ wire \core_io_ibus_inst[27] ;
+ wire \core_io_ibus_inst[28] ;
+ wire \core_io_ibus_inst[29] ;
+ wire \core_io_ibus_inst[2] ;
+ wire \core_io_ibus_inst[30] ;
+ wire \core_io_ibus_inst[31] ;
+ wire \core_io_ibus_inst[3] ;
+ wire \core_io_ibus_inst[4] ;
+ wire \core_io_ibus_inst[5] ;
+ wire \core_io_ibus_inst[6] ;
+ wire \core_io_ibus_inst[7] ;
+ wire \core_io_ibus_inst[8] ;
+ wire \core_io_ibus_inst[9] ;
+ wire core_io_ibus_valid;
+ wire core_io_irq_m1_irq;
+ wire core_io_irq_m2_irq;
+ wire core_io_irq_m3_irq;
+ wire core_io_irq_spi_irq;
+ wire core_io_irq_uart_irq;
+ wire \dmem_io_addr[0] ;
+ wire \dmem_io_addr[1] ;
+ wire \dmem_io_addr[2] ;
+ wire \dmem_io_addr[3] ;
+ wire \dmem_io_addr[4] ;
+ wire \dmem_io_addr[5] ;
+ wire \dmem_io_addr[6] ;
+ wire \dmem_io_addr[7] ;
+ wire \dmem_io_addr[8] ;
+ wire dmem_io_cs;
+ wire \dmem_io_rdata[0] ;
+ wire \dmem_io_rdata[10] ;
+ wire \dmem_io_rdata[11] ;
+ wire \dmem_io_rdata[12] ;
+ wire \dmem_io_rdata[13] ;
+ wire \dmem_io_rdata[14] ;
+ wire \dmem_io_rdata[15] ;
+ wire \dmem_io_rdata[16] ;
+ wire \dmem_io_rdata[17] ;
+ wire \dmem_io_rdata[18] ;
+ wire \dmem_io_rdata[19] ;
+ wire \dmem_io_rdata[1] ;
+ wire \dmem_io_rdata[20] ;
+ wire \dmem_io_rdata[21] ;
+ wire \dmem_io_rdata[22] ;
+ wire \dmem_io_rdata[23] ;
+ wire \dmem_io_rdata[24] ;
+ wire \dmem_io_rdata[25] ;
+ wire \dmem_io_rdata[26] ;
+ wire \dmem_io_rdata[27] ;
+ wire \dmem_io_rdata[28] ;
+ wire \dmem_io_rdata[29] ;
+ wire \dmem_io_rdata[2] ;
+ wire \dmem_io_rdata[30] ;
+ wire \dmem_io_rdata[31] ;
+ wire \dmem_io_rdata[3] ;
+ wire \dmem_io_rdata[4] ;
+ wire \dmem_io_rdata[5] ;
+ wire \dmem_io_rdata[6] ;
+ wire \dmem_io_rdata[7] ;
+ wire \dmem_io_rdata[8] ;
+ wire \dmem_io_rdata[9] ;
+ wire \dmem_io_st_type[0] ;
+ wire \dmem_io_st_type[1] ;
+ wire \dmem_io_st_type[2] ;
+ wire \dmem_io_st_type[3] ;
+ wire \dmem_io_wdata[0] ;
+ wire \dmem_io_wdata[10] ;
+ wire \dmem_io_wdata[11] ;
+ wire \dmem_io_wdata[12] ;
+ wire \dmem_io_wdata[13] ;
+ wire \dmem_io_wdata[14] ;
+ wire \dmem_io_wdata[15] ;
+ wire \dmem_io_wdata[16] ;
+ wire \dmem_io_wdata[17] ;
+ wire \dmem_io_wdata[18] ;
+ wire \dmem_io_wdata[19] ;
+ wire \dmem_io_wdata[1] ;
+ wire \dmem_io_wdata[20] ;
+ wire \dmem_io_wdata[21] ;
+ wire \dmem_io_wdata[22] ;
+ wire \dmem_io_wdata[23] ;
+ wire \dmem_io_wdata[24] ;
+ wire \dmem_io_wdata[25] ;
+ wire \dmem_io_wdata[26] ;
+ wire \dmem_io_wdata[27] ;
+ wire \dmem_io_wdata[28] ;
+ wire \dmem_io_wdata[29] ;
+ wire \dmem_io_wdata[2] ;
+ wire \dmem_io_wdata[30] ;
+ wire \dmem_io_wdata[31] ;
+ wire \dmem_io_wdata[3] ;
+ wire \dmem_io_wdata[4] ;
+ wire \dmem_io_wdata[5] ;
+ wire \dmem_io_wdata[6] ;
+ wire \dmem_io_wdata[7] ;
+ wire \dmem_io_wdata[8] ;
+ wire \dmem_io_wdata[9] ;
+ wire dmem_io_wr_en;
+ wire \imem_io_addr[0] ;
+ wire \imem_io_addr[1] ;
+ wire \imem_io_addr[2] ;
+ wire \imem_io_addr[3] ;
+ wire \imem_io_addr[4] ;
+ wire \imem_io_addr[5] ;
+ wire \imem_io_addr[6] ;
+ wire \imem_io_addr[7] ;
+ wire \imem_io_addr[8] ;
+ wire imem_io_cs;
+ wire \imem_io_rdata[0] ;
+ wire \imem_io_rdata[10] ;
+ wire \imem_io_rdata[11] ;
+ wire \imem_io_rdata[12] ;
+ wire \imem_io_rdata[13] ;
+ wire \imem_io_rdata[14] ;
+ wire \imem_io_rdata[15] ;
+ wire \imem_io_rdata[16] ;
+ wire \imem_io_rdata[17] ;
+ wire \imem_io_rdata[18] ;
+ wire \imem_io_rdata[19] ;
+ wire \imem_io_rdata[1] ;
+ wire \imem_io_rdata[20] ;
+ wire \imem_io_rdata[21] ;
+ wire \imem_io_rdata[22] ;
+ wire \imem_io_rdata[23] ;
+ wire \imem_io_rdata[24] ;
+ wire \imem_io_rdata[25] ;
+ wire \imem_io_rdata[26] ;
+ wire \imem_io_rdata[27] ;
+ wire \imem_io_rdata[28] ;
+ wire \imem_io_rdata[29] ;
+ wire \imem_io_rdata[2] ;
+ wire \imem_io_rdata[30] ;
+ wire \imem_io_rdata[31] ;
+ wire \imem_io_rdata[3] ;
+ wire \imem_io_rdata[4] ;
+ wire \imem_io_rdata[5] ;
+ wire \imem_io_rdata[6] ;
+ wire \imem_io_rdata[7] ;
+ wire \imem_io_rdata[8] ;
+ wire \imem_io_rdata[9] ;
+ wire \imem_io_st_type[0] ;
+ wire \imem_io_st_type[1] ;
+ wire \imem_io_st_type[2] ;
+ wire \imem_io_st_type[3] ;
+ wire \imem_io_wdata[0] ;
+ wire \imem_io_wdata[10] ;
+ wire \imem_io_wdata[11] ;
+ wire \imem_io_wdata[12] ;
+ wire \imem_io_wdata[13] ;
+ wire \imem_io_wdata[14] ;
+ wire \imem_io_wdata[15] ;
+ wire \imem_io_wdata[16] ;
+ wire \imem_io_wdata[17] ;
+ wire \imem_io_wdata[18] ;
+ wire \imem_io_wdata[19] ;
+ wire \imem_io_wdata[1] ;
+ wire \imem_io_wdata[20] ;
+ wire \imem_io_wdata[21] ;
+ wire \imem_io_wdata[22] ;
+ wire \imem_io_wdata[23] ;
+ wire \imem_io_wdata[24] ;
+ wire \imem_io_wdata[25] ;
+ wire \imem_io_wdata[26] ;
+ wire \imem_io_wdata[27] ;
+ wire \imem_io_wdata[28] ;
+ wire \imem_io_wdata[29] ;
+ wire \imem_io_wdata[2] ;
+ wire \imem_io_wdata[30] ;
+ wire \imem_io_wdata[31] ;
+ wire \imem_io_wdata[3] ;
+ wire \imem_io_wdata[4] ;
+ wire \imem_io_wdata[5] ;
+ wire \imem_io_wdata[6] ;
+ wire \imem_io_wdata[7] ;
+ wire \imem_io_wdata[8] ;
+ wire \imem_io_wdata[9] ;
+ wire imem_io_wr_en;
+ wire io_uart_tx_en;
+ wire m1_io_ba_match;
+ wire m1_io_wbs_ack_o;
+ wire \m1_io_wbs_data_o[0] ;
+ wire \m1_io_wbs_data_o[10] ;
+ wire \m1_io_wbs_data_o[11] ;
+ wire \m1_io_wbs_data_o[12] ;
+ wire \m1_io_wbs_data_o[13] ;
+ wire \m1_io_wbs_data_o[14] ;
+ wire \m1_io_wbs_data_o[15] ;
+ wire \m1_io_wbs_data_o[16] ;
+ wire \m1_io_wbs_data_o[17] ;
+ wire \m1_io_wbs_data_o[18] ;
+ wire \m1_io_wbs_data_o[19] ;
+ wire \m1_io_wbs_data_o[1] ;
+ wire \m1_io_wbs_data_o[20] ;
+ wire \m1_io_wbs_data_o[21] ;
+ wire \m1_io_wbs_data_o[22] ;
+ wire \m1_io_wbs_data_o[23] ;
+ wire \m1_io_wbs_data_o[24] ;
+ wire \m1_io_wbs_data_o[25] ;
+ wire \m1_io_wbs_data_o[26] ;
+ wire \m1_io_wbs_data_o[27] ;
+ wire \m1_io_wbs_data_o[28] ;
+ wire \m1_io_wbs_data_o[29] ;
+ wire \m1_io_wbs_data_o[2] ;
+ wire \m1_io_wbs_data_o[30] ;
+ wire \m1_io_wbs_data_o[31] ;
+ wire \m1_io_wbs_data_o[3] ;
+ wire \m1_io_wbs_data_o[4] ;
+ wire \m1_io_wbs_data_o[5] ;
+ wire \m1_io_wbs_data_o[6] ;
+ wire \m1_io_wbs_data_o[7] ;
+ wire \m1_io_wbs_data_o[8] ;
+ wire \m1_io_wbs_data_o[9] ;
+ wire \m1_io_wbs_m2s_addr[0] ;
+ wire \m1_io_wbs_m2s_addr[10] ;
+ wire \m1_io_wbs_m2s_addr[11] ;
+ wire \m1_io_wbs_m2s_addr[12] ;
+ wire \m1_io_wbs_m2s_addr[13] ;
+ wire \m1_io_wbs_m2s_addr[14] ;
+ wire \m1_io_wbs_m2s_addr[15] ;
+ wire \m1_io_wbs_m2s_addr[1] ;
+ wire \m1_io_wbs_m2s_addr[2] ;
+ wire \m1_io_wbs_m2s_addr[3] ;
+ wire \m1_io_wbs_m2s_addr[4] ;
+ wire \m1_io_wbs_m2s_addr[5] ;
+ wire \m1_io_wbs_m2s_addr[6] ;
+ wire \m1_io_wbs_m2s_addr[7] ;
+ wire \m1_io_wbs_m2s_addr[8] ;
+ wire \m1_io_wbs_m2s_addr[9] ;
+ wire \m1_io_wbs_m2s_data[0] ;
+ wire \m1_io_wbs_m2s_data[10] ;
+ wire \m1_io_wbs_m2s_data[11] ;
+ wire \m1_io_wbs_m2s_data[12] ;
+ wire \m1_io_wbs_m2s_data[13] ;
+ wire \m1_io_wbs_m2s_data[14] ;
+ wire \m1_io_wbs_m2s_data[15] ;
+ wire \m1_io_wbs_m2s_data[16] ;
+ wire \m1_io_wbs_m2s_data[17] ;
+ wire \m1_io_wbs_m2s_data[18] ;
+ wire \m1_io_wbs_m2s_data[19] ;
+ wire \m1_io_wbs_m2s_data[1] ;
+ wire \m1_io_wbs_m2s_data[20] ;
+ wire \m1_io_wbs_m2s_data[21] ;
+ wire \m1_io_wbs_m2s_data[22] ;
+ wire \m1_io_wbs_m2s_data[23] ;
+ wire \m1_io_wbs_m2s_data[24] ;
+ wire \m1_io_wbs_m2s_data[25] ;
+ wire \m1_io_wbs_m2s_data[26] ;
+ wire \m1_io_wbs_m2s_data[27] ;
+ wire \m1_io_wbs_m2s_data[28] ;
+ wire \m1_io_wbs_m2s_data[29] ;
+ wire \m1_io_wbs_m2s_data[2] ;
+ wire \m1_io_wbs_m2s_data[30] ;
+ wire \m1_io_wbs_m2s_data[31] ;
+ wire \m1_io_wbs_m2s_data[3] ;
+ wire \m1_io_wbs_m2s_data[4] ;
+ wire \m1_io_wbs_m2s_data[5] ;
+ wire \m1_io_wbs_m2s_data[6] ;
+ wire \m1_io_wbs_m2s_data[7] ;
+ wire \m1_io_wbs_m2s_data[8] ;
+ wire \m1_io_wbs_m2s_data[9] ;
+ wire \m1_io_wbs_m2s_sel[0] ;
+ wire \m1_io_wbs_m2s_sel[1] ;
+ wire \m1_io_wbs_m2s_sel[2] ;
+ wire \m1_io_wbs_m2s_sel[3] ;
+ wire m1_io_wbs_m2s_stb;
+ wire m1_io_wbs_m2s_we;
+ wire m2_io_ba_match;
+ wire m2_io_wbs_ack_o;
+ wire \m2_io_wbs_data_o[0] ;
+ wire \m2_io_wbs_data_o[10] ;
+ wire \m2_io_wbs_data_o[11] ;
+ wire \m2_io_wbs_data_o[12] ;
+ wire \m2_io_wbs_data_o[13] ;
+ wire \m2_io_wbs_data_o[14] ;
+ wire \m2_io_wbs_data_o[15] ;
+ wire \m2_io_wbs_data_o[16] ;
+ wire \m2_io_wbs_data_o[17] ;
+ wire \m2_io_wbs_data_o[18] ;
+ wire \m2_io_wbs_data_o[19] ;
+ wire \m2_io_wbs_data_o[1] ;
+ wire \m2_io_wbs_data_o[20] ;
+ wire \m2_io_wbs_data_o[21] ;
+ wire \m2_io_wbs_data_o[22] ;
+ wire \m2_io_wbs_data_o[23] ;
+ wire \m2_io_wbs_data_o[24] ;
+ wire \m2_io_wbs_data_o[25] ;
+ wire \m2_io_wbs_data_o[26] ;
+ wire \m2_io_wbs_data_o[27] ;
+ wire \m2_io_wbs_data_o[28] ;
+ wire \m2_io_wbs_data_o[29] ;
+ wire \m2_io_wbs_data_o[2] ;
+ wire \m2_io_wbs_data_o[30] ;
+ wire \m2_io_wbs_data_o[31] ;
+ wire \m2_io_wbs_data_o[3] ;
+ wire \m2_io_wbs_data_o[4] ;
+ wire \m2_io_wbs_data_o[5] ;
+ wire \m2_io_wbs_data_o[6] ;
+ wire \m2_io_wbs_data_o[7] ;
+ wire \m2_io_wbs_data_o[8] ;
+ wire \m2_io_wbs_data_o[9] ;
+ wire m3_io_ba_match;
+ wire m3_io_wbs_ack_o;
+ wire \m3_io_wbs_data_o[0] ;
+ wire \m3_io_wbs_data_o[10] ;
+ wire \m3_io_wbs_data_o[11] ;
+ wire \m3_io_wbs_data_o[12] ;
+ wire \m3_io_wbs_data_o[13] ;
+ wire \m3_io_wbs_data_o[14] ;
+ wire \m3_io_wbs_data_o[15] ;
+ wire \m3_io_wbs_data_o[16] ;
+ wire \m3_io_wbs_data_o[17] ;
+ wire \m3_io_wbs_data_o[18] ;
+ wire \m3_io_wbs_data_o[19] ;
+ wire \m3_io_wbs_data_o[1] ;
+ wire \m3_io_wbs_data_o[20] ;
+ wire \m3_io_wbs_data_o[21] ;
+ wire \m3_io_wbs_data_o[22] ;
+ wire \m3_io_wbs_data_o[23] ;
+ wire \m3_io_wbs_data_o[24] ;
+ wire \m3_io_wbs_data_o[25] ;
+ wire \m3_io_wbs_data_o[26] ;
+ wire \m3_io_wbs_data_o[27] ;
+ wire \m3_io_wbs_data_o[28] ;
+ wire \m3_io_wbs_data_o[29] ;
+ wire \m3_io_wbs_data_o[2] ;
+ wire \m3_io_wbs_data_o[30] ;
+ wire \m3_io_wbs_data_o[31] ;
+ wire \m3_io_wbs_data_o[3] ;
+ wire \m3_io_wbs_data_o[4] ;
+ wire \m3_io_wbs_data_o[5] ;
+ wire \m3_io_wbs_data_o[6] ;
+ wire \m3_io_wbs_data_o[7] ;
+ wire \m3_io_wbs_data_o[8] ;
+ wire \m3_io_wbs_data_o[9] ;
+
+ Core core (.clock(wb_clk_i),
+    .io_dbus_rd_en(core_io_dbus_rd_en),
+    .io_dbus_valid(core_io_dbus_valid),
+    .io_dbus_wr_en(core_io_dbus_wr_en),
+    .io_ibus_valid(core_io_ibus_valid),
+    .io_irq_m1_irq(core_io_irq_m1_irq),
+    .io_irq_m2_irq(core_io_irq_m2_irq),
+    .io_irq_m3_irq(core_io_irq_m3_irq),
+    .io_irq_spi_irq(core_io_irq_spi_irq),
+    .io_irq_uart_irq(core_io_irq_uart_irq),
+    .reset(wb_rst_i),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .io_dbus_addr({\core_io_dbus_addr[31] ,
+    \core_io_dbus_addr[30] ,
+    \core_io_dbus_addr[29] ,
+    \core_io_dbus_addr[28] ,
+    \core_io_dbus_addr[27] ,
+    \core_io_dbus_addr[26] ,
+    \core_io_dbus_addr[25] ,
+    \core_io_dbus_addr[24] ,
+    \core_io_dbus_addr[23] ,
+    \core_io_dbus_addr[22] ,
+    \core_io_dbus_addr[21] ,
+    \core_io_dbus_addr[20] ,
+    \core_io_dbus_addr[19] ,
+    \core_io_dbus_addr[18] ,
+    \core_io_dbus_addr[17] ,
+    \core_io_dbus_addr[16] ,
+    \core_io_dbus_addr[15] ,
+    \core_io_dbus_addr[14] ,
+    \core_io_dbus_addr[13] ,
+    \core_io_dbus_addr[12] ,
+    \core_io_dbus_addr[11] ,
+    \core_io_dbus_addr[10] ,
+    \core_io_dbus_addr[9] ,
+    \core_io_dbus_addr[8] ,
+    \core_io_dbus_addr[7] ,
+    \core_io_dbus_addr[6] ,
+    \core_io_dbus_addr[5] ,
+    \core_io_dbus_addr[4] ,
+    \core_io_dbus_addr[3] ,
+    \core_io_dbus_addr[2] ,
+    \core_io_dbus_addr[1] ,
+    \core_io_dbus_addr[0] }),
+    .io_dbus_ld_type({\core_io_dbus_ld_type[2] ,
+    \core_io_dbus_ld_type[1] ,
+    \core_io_dbus_ld_type[0] }),
+    .io_dbus_rdata({\core_io_dbus_rdata[31] ,
+    \core_io_dbus_rdata[30] ,
+    \core_io_dbus_rdata[29] ,
+    \core_io_dbus_rdata[28] ,
+    \core_io_dbus_rdata[27] ,
+    \core_io_dbus_rdata[26] ,
+    \core_io_dbus_rdata[25] ,
+    \core_io_dbus_rdata[24] ,
+    \core_io_dbus_rdata[23] ,
+    \core_io_dbus_rdata[22] ,
+    \core_io_dbus_rdata[21] ,
+    \core_io_dbus_rdata[20] ,
+    \core_io_dbus_rdata[19] ,
+    \core_io_dbus_rdata[18] ,
+    \core_io_dbus_rdata[17] ,
+    \core_io_dbus_rdata[16] ,
+    \core_io_dbus_rdata[15] ,
+    \core_io_dbus_rdata[14] ,
+    \core_io_dbus_rdata[13] ,
+    \core_io_dbus_rdata[12] ,
+    \core_io_dbus_rdata[11] ,
+    \core_io_dbus_rdata[10] ,
+    \core_io_dbus_rdata[9] ,
+    \core_io_dbus_rdata[8] ,
+    \core_io_dbus_rdata[7] ,
+    \core_io_dbus_rdata[6] ,
+    \core_io_dbus_rdata[5] ,
+    \core_io_dbus_rdata[4] ,
+    \core_io_dbus_rdata[3] ,
+    \core_io_dbus_rdata[2] ,
+    \core_io_dbus_rdata[1] ,
+    \core_io_dbus_rdata[0] }),
+    .io_dbus_st_type({\core_io_dbus_st_type[1] ,
+    \core_io_dbus_st_type[0] }),
+    .io_dbus_wdata({\core_io_dbus_wdata[31] ,
+    \core_io_dbus_wdata[30] ,
+    \core_io_dbus_wdata[29] ,
+    \core_io_dbus_wdata[28] ,
+    \core_io_dbus_wdata[27] ,
+    \core_io_dbus_wdata[26] ,
+    \core_io_dbus_wdata[25] ,
+    \core_io_dbus_wdata[24] ,
+    \core_io_dbus_wdata[23] ,
+    \core_io_dbus_wdata[22] ,
+    \core_io_dbus_wdata[21] ,
+    \core_io_dbus_wdata[20] ,
+    \core_io_dbus_wdata[19] ,
+    \core_io_dbus_wdata[18] ,
+    \core_io_dbus_wdata[17] ,
+    \core_io_dbus_wdata[16] ,
+    \core_io_dbus_wdata[15] ,
+    \core_io_dbus_wdata[14] ,
+    \core_io_dbus_wdata[13] ,
+    \core_io_dbus_wdata[12] ,
+    \core_io_dbus_wdata[11] ,
+    \core_io_dbus_wdata[10] ,
+    \core_io_dbus_wdata[9] ,
+    \core_io_dbus_wdata[8] ,
+    \core_io_dbus_wdata[7] ,
+    \core_io_dbus_wdata[6] ,
+    \core_io_dbus_wdata[5] ,
+    \core_io_dbus_wdata[4] ,
+    \core_io_dbus_wdata[3] ,
+    \core_io_dbus_wdata[2] ,
+    \core_io_dbus_wdata[1] ,
+    \core_io_dbus_wdata[0] }),
+    .io_ibus_addr({\core_io_ibus_addr[31] ,
+    \core_io_ibus_addr[30] ,
+    \core_io_ibus_addr[29] ,
+    \core_io_ibus_addr[28] ,
+    \core_io_ibus_addr[27] ,
+    \core_io_ibus_addr[26] ,
+    \core_io_ibus_addr[25] ,
+    \core_io_ibus_addr[24] ,
+    \core_io_ibus_addr[23] ,
+    \core_io_ibus_addr[22] ,
+    \core_io_ibus_addr[21] ,
+    \core_io_ibus_addr[20] ,
+    \core_io_ibus_addr[19] ,
+    \core_io_ibus_addr[18] ,
+    \core_io_ibus_addr[17] ,
+    \core_io_ibus_addr[16] ,
+    \core_io_ibus_addr[15] ,
+    \core_io_ibus_addr[14] ,
+    \core_io_ibus_addr[13] ,
+    \core_io_ibus_addr[12] ,
+    \core_io_ibus_addr[11] ,
+    \core_io_ibus_addr[10] ,
+    \core_io_ibus_addr[9] ,
+    \core_io_ibus_addr[8] ,
+    \core_io_ibus_addr[7] ,
+    \core_io_ibus_addr[6] ,
+    \core_io_ibus_addr[5] ,
+    \core_io_ibus_addr[4] ,
+    \core_io_ibus_addr[3] ,
+    \core_io_ibus_addr[2] ,
+    \core_io_ibus_addr[1] ,
+    \core_io_ibus_addr[0] }),
+    .io_ibus_inst({\core_io_ibus_inst[31] ,
+    \core_io_ibus_inst[30] ,
+    \core_io_ibus_inst[29] ,
+    \core_io_ibus_inst[28] ,
+    \core_io_ibus_inst[27] ,
+    \core_io_ibus_inst[26] ,
+    \core_io_ibus_inst[25] ,
+    \core_io_ibus_inst[24] ,
+    \core_io_ibus_inst[23] ,
+    \core_io_ibus_inst[22] ,
+    \core_io_ibus_inst[21] ,
+    \core_io_ibus_inst[20] ,
+    \core_io_ibus_inst[19] ,
+    \core_io_ibus_inst[18] ,
+    \core_io_ibus_inst[17] ,
+    \core_io_ibus_inst[16] ,
+    \core_io_ibus_inst[15] ,
+    \core_io_ibus_inst[14] ,
+    \core_io_ibus_inst[13] ,
+    \core_io_ibus_inst[12] ,
+    \core_io_ibus_inst[11] ,
+    \core_io_ibus_inst[10] ,
+    \core_io_ibus_inst[9] ,
+    \core_io_ibus_inst[8] ,
+    \core_io_ibus_inst[7] ,
+    \core_io_ibus_inst[6] ,
+    \core_io_ibus_inst[5] ,
+    \core_io_ibus_inst[4] ,
+    \core_io_ibus_inst[3] ,
+    \core_io_ibus_inst[2] ,
+    \core_io_ibus_inst[1] ,
+    \core_io_ibus_inst[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 dmem (.csb0(dmem_io_cs),
+    .web0(dmem_io_wr_en),
+    .clk0(wb_clk_i),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\dmem_io_addr[8] ,
+    \dmem_io_addr[7] ,
+    \dmem_io_addr[6] ,
+    \dmem_io_addr[5] ,
+    \dmem_io_addr[4] ,
+    \dmem_io_addr[3] ,
+    \dmem_io_addr[2] ,
+    \dmem_io_addr[1] ,
+    \dmem_io_addr[0] }),
+    .addr1({_NC1,
+    _NC2,
+    _NC3,
+    _NC4,
+    _NC5,
+    _NC6,
+    _NC7,
+    _NC8,
+    _NC9}),
+    .din0({\dmem_io_wdata[31] ,
+    \dmem_io_wdata[30] ,
+    \dmem_io_wdata[29] ,
+    \dmem_io_wdata[28] ,
+    \dmem_io_wdata[27] ,
+    \dmem_io_wdata[26] ,
+    \dmem_io_wdata[25] ,
+    \dmem_io_wdata[24] ,
+    \dmem_io_wdata[23] ,
+    \dmem_io_wdata[22] ,
+    \dmem_io_wdata[21] ,
+    \dmem_io_wdata[20] ,
+    \dmem_io_wdata[19] ,
+    \dmem_io_wdata[18] ,
+    \dmem_io_wdata[17] ,
+    \dmem_io_wdata[16] ,
+    \dmem_io_wdata[15] ,
+    \dmem_io_wdata[14] ,
+    \dmem_io_wdata[13] ,
+    \dmem_io_wdata[12] ,
+    \dmem_io_wdata[11] ,
+    \dmem_io_wdata[10] ,
+    \dmem_io_wdata[9] ,
+    \dmem_io_wdata[8] ,
+    \dmem_io_wdata[7] ,
+    \dmem_io_wdata[6] ,
+    \dmem_io_wdata[5] ,
+    \dmem_io_wdata[4] ,
+    \dmem_io_wdata[3] ,
+    \dmem_io_wdata[2] ,
+    \dmem_io_wdata[1] ,
+    \dmem_io_wdata[0] }),
+    .dout0({\dmem_io_rdata[31] ,
+    \dmem_io_rdata[30] ,
+    \dmem_io_rdata[29] ,
+    \dmem_io_rdata[28] ,
+    \dmem_io_rdata[27] ,
+    \dmem_io_rdata[26] ,
+    \dmem_io_rdata[25] ,
+    \dmem_io_rdata[24] ,
+    \dmem_io_rdata[23] ,
+    \dmem_io_rdata[22] ,
+    \dmem_io_rdata[21] ,
+    \dmem_io_rdata[20] ,
+    \dmem_io_rdata[19] ,
+    \dmem_io_rdata[18] ,
+    \dmem_io_rdata[17] ,
+    \dmem_io_rdata[16] ,
+    \dmem_io_rdata[15] ,
+    \dmem_io_rdata[14] ,
+    \dmem_io_rdata[13] ,
+    \dmem_io_rdata[12] ,
+    \dmem_io_rdata[11] ,
+    \dmem_io_rdata[10] ,
+    \dmem_io_rdata[9] ,
+    \dmem_io_rdata[8] ,
+    \dmem_io_rdata[7] ,
+    \dmem_io_rdata[6] ,
+    \dmem_io_rdata[5] ,
+    \dmem_io_rdata[4] ,
+    \dmem_io_rdata[3] ,
+    \dmem_io_rdata[2] ,
+    \dmem_io_rdata[1] ,
+    \dmem_io_rdata[0] }),
+    .dout1({_NC10,
+    _NC11,
+    _NC12,
+    _NC13,
+    _NC14,
+    _NC15,
+    _NC16,
+    _NC17,
+    _NC18,
+    _NC19,
+    _NC20,
+    _NC21,
+    _NC22,
+    _NC23,
+    _NC24,
+    _NC25,
+    _NC26,
+    _NC27,
+    _NC28,
+    _NC29,
+    _NC30,
+    _NC31,
+    _NC32,
+    _NC33,
+    _NC34,
+    _NC35,
+    _NC36,
+    _NC37,
+    _NC38,
+    _NC39,
+    _NC40,
+    _NC41}),
+    .wmask0({\dmem_io_st_type[3] ,
+    \dmem_io_st_type[2] ,
+    \dmem_io_st_type[1] ,
+    \dmem_io_st_type[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 imem (.csb0(imem_io_cs),
+    .web0(imem_io_wr_en),
+    .clk0(wb_clk_i),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\imem_io_addr[8] ,
+    \imem_io_addr[7] ,
+    \imem_io_addr[6] ,
+    \imem_io_addr[5] ,
+    \imem_io_addr[4] ,
+    \imem_io_addr[3] ,
+    \imem_io_addr[2] ,
+    \imem_io_addr[1] ,
+    \imem_io_addr[0] }),
+    .addr1({_NC42,
+    _NC43,
+    _NC44,
+    _NC45,
+    _NC46,
+    _NC47,
+    _NC48,
+    _NC49,
+    _NC50}),
+    .din0({\imem_io_wdata[31] ,
+    \imem_io_wdata[30] ,
+    \imem_io_wdata[29] ,
+    \imem_io_wdata[28] ,
+    \imem_io_wdata[27] ,
+    \imem_io_wdata[26] ,
+    \imem_io_wdata[25] ,
+    \imem_io_wdata[24] ,
+    \imem_io_wdata[23] ,
+    \imem_io_wdata[22] ,
+    \imem_io_wdata[21] ,
+    \imem_io_wdata[20] ,
+    \imem_io_wdata[19] ,
+    \imem_io_wdata[18] ,
+    \imem_io_wdata[17] ,
+    \imem_io_wdata[16] ,
+    \imem_io_wdata[15] ,
+    \imem_io_wdata[14] ,
+    \imem_io_wdata[13] ,
+    \imem_io_wdata[12] ,
+    \imem_io_wdata[11] ,
+    \imem_io_wdata[10] ,
+    \imem_io_wdata[9] ,
+    \imem_io_wdata[8] ,
+    \imem_io_wdata[7] ,
+    \imem_io_wdata[6] ,
+    \imem_io_wdata[5] ,
+    \imem_io_wdata[4] ,
+    \imem_io_wdata[3] ,
+    \imem_io_wdata[2] ,
+    \imem_io_wdata[1] ,
+    \imem_io_wdata[0] }),
+    .dout0({\imem_io_rdata[31] ,
+    \imem_io_rdata[30] ,
+    \imem_io_rdata[29] ,
+    \imem_io_rdata[28] ,
+    \imem_io_rdata[27] ,
+    \imem_io_rdata[26] ,
+    \imem_io_rdata[25] ,
+    \imem_io_rdata[24] ,
+    \imem_io_rdata[23] ,
+    \imem_io_rdata[22] ,
+    \imem_io_rdata[21] ,
+    \imem_io_rdata[20] ,
+    \imem_io_rdata[19] ,
+    \imem_io_rdata[18] ,
+    \imem_io_rdata[17] ,
+    \imem_io_rdata[16] ,
+    \imem_io_rdata[15] ,
+    \imem_io_rdata[14] ,
+    \imem_io_rdata[13] ,
+    \imem_io_rdata[12] ,
+    \imem_io_rdata[11] ,
+    \imem_io_rdata[10] ,
+    \imem_io_rdata[9] ,
+    \imem_io_rdata[8] ,
+    \imem_io_rdata[7] ,
+    \imem_io_rdata[6] ,
+    \imem_io_rdata[5] ,
+    \imem_io_rdata[4] ,
+    \imem_io_rdata[3] ,
+    \imem_io_rdata[2] ,
+    \imem_io_rdata[1] ,
+    \imem_io_rdata[0] }),
+    .dout1({_NC51,
+    _NC52,
+    _NC53,
+    _NC54,
+    _NC55,
+    _NC56,
+    _NC57,
+    _NC58,
+    _NC59,
+    _NC60,
+    _NC61,
+    _NC62,
+    _NC63,
+    _NC64,
+    _NC65,
+    _NC66,
+    _NC67,
+    _NC68,
+    _NC69,
+    _NC70,
+    _NC71,
+    _NC72,
+    _NC73,
+    _NC74,
+    _NC75,
+    _NC76,
+    _NC77,
+    _NC78,
+    _NC79,
+    _NC80,
+    _NC81,
+    _NC82}),
+    .wmask0({\dmem_io_st_type[3] ,
+    \dmem_io_st_type[2] ,
+    \dmem_io_st_type[1] ,
+    \dmem_io_st_type[0] }));
+ Motor_Top m1 (.clock(wb_clk_i),
+    .io_ba_match(m1_io_ba_match),
+    .io_motor_gpio_pwm_high(io_m1_io_pwm_high),
+    .io_motor_gpio_pwm_high_en(io_m1_io_pwm_high_en),
+    .io_motor_gpio_pwm_low(io_m1_io_pwm_low),
+    .io_motor_gpio_pwm_low_en(io_m1_io_pwm_low_en),
+    .io_motor_gpio_qei_ch_a(io_in[2]),
+    .io_motor_gpio_qei_ch_b(io_in[3]),
+    .io_motor_irq(core_io_irq_m1_irq),
+    .io_wbs_ack_o(m1_io_wbs_ack_o),
+    .io_wbs_m2s_stb(m1_io_wbs_m2s_stb),
+    .io_wbs_m2s_we(m1_io_wbs_m2s_we),
+    .reset(wb_rst_i),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .io_wbs_data_o({\m1_io_wbs_data_o[31] ,
+    \m1_io_wbs_data_o[30] ,
+    \m1_io_wbs_data_o[29] ,
+    \m1_io_wbs_data_o[28] ,
+    \m1_io_wbs_data_o[27] ,
+    \m1_io_wbs_data_o[26] ,
+    \m1_io_wbs_data_o[25] ,
+    \m1_io_wbs_data_o[24] ,
+    \m1_io_wbs_data_o[23] ,
+    \m1_io_wbs_data_o[22] ,
+    \m1_io_wbs_data_o[21] ,
+    \m1_io_wbs_data_o[20] ,
+    \m1_io_wbs_data_o[19] ,
+    \m1_io_wbs_data_o[18] ,
+    \m1_io_wbs_data_o[17] ,
+    \m1_io_wbs_data_o[16] ,
+    \m1_io_wbs_data_o[15] ,
+    \m1_io_wbs_data_o[14] ,
+    \m1_io_wbs_data_o[13] ,
+    \m1_io_wbs_data_o[12] ,
+    \m1_io_wbs_data_o[11] ,
+    \m1_io_wbs_data_o[10] ,
+    \m1_io_wbs_data_o[9] ,
+    \m1_io_wbs_data_o[8] ,
+    \m1_io_wbs_data_o[7] ,
+    \m1_io_wbs_data_o[6] ,
+    \m1_io_wbs_data_o[5] ,
+    \m1_io_wbs_data_o[4] ,
+    \m1_io_wbs_data_o[3] ,
+    \m1_io_wbs_data_o[2] ,
+    \m1_io_wbs_data_o[1] ,
+    \m1_io_wbs_data_o[0] }),
+    .io_wbs_m2s_addr({\m1_io_wbs_m2s_addr[15] ,
+    \m1_io_wbs_m2s_addr[14] ,
+    \m1_io_wbs_m2s_addr[13] ,
+    \m1_io_wbs_m2s_addr[12] ,
+    \m1_io_wbs_m2s_addr[11] ,
+    \m1_io_wbs_m2s_addr[10] ,
+    \m1_io_wbs_m2s_addr[9] ,
+    \m1_io_wbs_m2s_addr[8] ,
+    \m1_io_wbs_m2s_addr[7] ,
+    \m1_io_wbs_m2s_addr[6] ,
+    \m1_io_wbs_m2s_addr[5] ,
+    \m1_io_wbs_m2s_addr[4] ,
+    \m1_io_wbs_m2s_addr[3] ,
+    \m1_io_wbs_m2s_addr[2] ,
+    \m1_io_wbs_m2s_addr[1] ,
+    \m1_io_wbs_m2s_addr[0] }),
+    .io_wbs_m2s_data({\m1_io_wbs_m2s_data[31] ,
+    \m1_io_wbs_m2s_data[30] ,
+    \m1_io_wbs_m2s_data[29] ,
+    \m1_io_wbs_m2s_data[28] ,
+    \m1_io_wbs_m2s_data[27] ,
+    \m1_io_wbs_m2s_data[26] ,
+    \m1_io_wbs_m2s_data[25] ,
+    \m1_io_wbs_m2s_data[24] ,
+    \m1_io_wbs_m2s_data[23] ,
+    \m1_io_wbs_m2s_data[22] ,
+    \m1_io_wbs_m2s_data[21] ,
+    \m1_io_wbs_m2s_data[20] ,
+    \m1_io_wbs_m2s_data[19] ,
+    \m1_io_wbs_m2s_data[18] ,
+    \m1_io_wbs_m2s_data[17] ,
+    \m1_io_wbs_m2s_data[16] ,
+    \m1_io_wbs_m2s_data[15] ,
+    \m1_io_wbs_m2s_data[14] ,
+    \m1_io_wbs_m2s_data[13] ,
+    \m1_io_wbs_m2s_data[12] ,
+    \m1_io_wbs_m2s_data[11] ,
+    \m1_io_wbs_m2s_data[10] ,
+    \m1_io_wbs_m2s_data[9] ,
+    \m1_io_wbs_m2s_data[8] ,
+    \m1_io_wbs_m2s_data[7] ,
+    \m1_io_wbs_m2s_data[6] ,
+    \m1_io_wbs_m2s_data[5] ,
+    \m1_io_wbs_m2s_data[4] ,
+    \m1_io_wbs_m2s_data[3] ,
+    \m1_io_wbs_m2s_data[2] ,
+    \m1_io_wbs_m2s_data[1] ,
+    \m1_io_wbs_m2s_data[0] }),
+    .io_wbs_m2s_sel({\m1_io_wbs_m2s_sel[3] ,
+    \m1_io_wbs_m2s_sel[2] ,
+    \m1_io_wbs_m2s_sel[1] ,
+    \m1_io_wbs_m2s_sel[0] }));
+ Motor_Top m2 (.clock(wb_clk_i),
+    .io_ba_match(m2_io_ba_match),
+    .io_motor_gpio_pwm_high(io_m2_io_pwm_high),
+    .io_motor_gpio_pwm_high_en(io_m2_io_pwm_high_en),
+    .io_motor_gpio_pwm_low(io_m2_io_pwm_low),
+    .io_motor_gpio_pwm_low_en(io_m2_io_pwm_low_en),
+    .io_motor_gpio_qei_ch_a(io_in[4]),
+    .io_motor_gpio_qei_ch_b(io_in[5]),
+    .io_motor_irq(core_io_irq_m2_irq),
+    .io_wbs_ack_o(m2_io_wbs_ack_o),
+    .io_wbs_m2s_stb(m1_io_wbs_m2s_stb),
+    .io_wbs_m2s_we(m1_io_wbs_m2s_we),
+    .reset(wb_rst_i),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .io_wbs_data_o({\m2_io_wbs_data_o[31] ,
+    \m2_io_wbs_data_o[30] ,
+    \m2_io_wbs_data_o[29] ,
+    \m2_io_wbs_data_o[28] ,
+    \m2_io_wbs_data_o[27] ,
+    \m2_io_wbs_data_o[26] ,
+    \m2_io_wbs_data_o[25] ,
+    \m2_io_wbs_data_o[24] ,
+    \m2_io_wbs_data_o[23] ,
+    \m2_io_wbs_data_o[22] ,
+    \m2_io_wbs_data_o[21] ,
+    \m2_io_wbs_data_o[20] ,
+    \m2_io_wbs_data_o[19] ,
+    \m2_io_wbs_data_o[18] ,
+    \m2_io_wbs_data_o[17] ,
+    \m2_io_wbs_data_o[16] ,
+    \m2_io_wbs_data_o[15] ,
+    \m2_io_wbs_data_o[14] ,
+    \m2_io_wbs_data_o[13] ,
+    \m2_io_wbs_data_o[12] ,
+    \m2_io_wbs_data_o[11] ,
+    \m2_io_wbs_data_o[10] ,
+    \m2_io_wbs_data_o[9] ,
+    \m2_io_wbs_data_o[8] ,
+    \m2_io_wbs_data_o[7] ,
+    \m2_io_wbs_data_o[6] ,
+    \m2_io_wbs_data_o[5] ,
+    \m2_io_wbs_data_o[4] ,
+    \m2_io_wbs_data_o[3] ,
+    \m2_io_wbs_data_o[2] ,
+    \m2_io_wbs_data_o[1] ,
+    \m2_io_wbs_data_o[0] }),
+    .io_wbs_m2s_addr({\m1_io_wbs_m2s_addr[15] ,
+    \m1_io_wbs_m2s_addr[14] ,
+    \m1_io_wbs_m2s_addr[13] ,
+    \m1_io_wbs_m2s_addr[12] ,
+    \m1_io_wbs_m2s_addr[11] ,
+    \m1_io_wbs_m2s_addr[10] ,
+    \m1_io_wbs_m2s_addr[9] ,
+    \m1_io_wbs_m2s_addr[8] ,
+    \m1_io_wbs_m2s_addr[7] ,
+    \m1_io_wbs_m2s_addr[6] ,
+    \m1_io_wbs_m2s_addr[5] ,
+    \m1_io_wbs_m2s_addr[4] ,
+    \m1_io_wbs_m2s_addr[3] ,
+    \m1_io_wbs_m2s_addr[2] ,
+    \m1_io_wbs_m2s_addr[1] ,
+    \m1_io_wbs_m2s_addr[0] }),
+    .io_wbs_m2s_data({\m1_io_wbs_m2s_data[31] ,
+    \m1_io_wbs_m2s_data[30] ,
+    \m1_io_wbs_m2s_data[29] ,
+    \m1_io_wbs_m2s_data[28] ,
+    \m1_io_wbs_m2s_data[27] ,
+    \m1_io_wbs_m2s_data[26] ,
+    \m1_io_wbs_m2s_data[25] ,
+    \m1_io_wbs_m2s_data[24] ,
+    \m1_io_wbs_m2s_data[23] ,
+    \m1_io_wbs_m2s_data[22] ,
+    \m1_io_wbs_m2s_data[21] ,
+    \m1_io_wbs_m2s_data[20] ,
+    \m1_io_wbs_m2s_data[19] ,
+    \m1_io_wbs_m2s_data[18] ,
+    \m1_io_wbs_m2s_data[17] ,
+    \m1_io_wbs_m2s_data[16] ,
+    \m1_io_wbs_m2s_data[15] ,
+    \m1_io_wbs_m2s_data[14] ,
+    \m1_io_wbs_m2s_data[13] ,
+    \m1_io_wbs_m2s_data[12] ,
+    \m1_io_wbs_m2s_data[11] ,
+    \m1_io_wbs_m2s_data[10] ,
+    \m1_io_wbs_m2s_data[9] ,
+    \m1_io_wbs_m2s_data[8] ,
+    \m1_io_wbs_m2s_data[7] ,
+    \m1_io_wbs_m2s_data[6] ,
+    \m1_io_wbs_m2s_data[5] ,
+    \m1_io_wbs_m2s_data[4] ,
+    \m1_io_wbs_m2s_data[3] ,
+    \m1_io_wbs_m2s_data[2] ,
+    \m1_io_wbs_m2s_data[1] ,
+    \m1_io_wbs_m2s_data[0] }),
+    .io_wbs_m2s_sel({\m1_io_wbs_m2s_sel[3] ,
+    \m1_io_wbs_m2s_sel[2] ,
+    \m1_io_wbs_m2s_sel[1] ,
+    \m1_io_wbs_m2s_sel[0] }));
+ Motor_Top m3 (.clock(wb_clk_i),
+    .io_ba_match(m3_io_ba_match),
+    .io_motor_gpio_pwm_high(io_m3_io_pwm_high),
+    .io_motor_gpio_pwm_high_en(io_m3_io_pwm_high_en),
+    .io_motor_gpio_pwm_low(io_m3_io_pwm_low),
+    .io_motor_gpio_pwm_low_en(io_m3_io_pwm_low_en),
+    .io_motor_gpio_qei_ch_a(io_in[6]),
+    .io_motor_gpio_qei_ch_b(io_in[7]),
+    .io_motor_irq(core_io_irq_m3_irq),
+    .io_wbs_ack_o(m3_io_wbs_ack_o),
+    .io_wbs_m2s_stb(m1_io_wbs_m2s_stb),
+    .io_wbs_m2s_we(m1_io_wbs_m2s_we),
+    .reset(wb_rst_i),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .io_wbs_data_o({\m3_io_wbs_data_o[31] ,
+    \m3_io_wbs_data_o[30] ,
+    \m3_io_wbs_data_o[29] ,
+    \m3_io_wbs_data_o[28] ,
+    \m3_io_wbs_data_o[27] ,
+    \m3_io_wbs_data_o[26] ,
+    \m3_io_wbs_data_o[25] ,
+    \m3_io_wbs_data_o[24] ,
+    \m3_io_wbs_data_o[23] ,
+    \m3_io_wbs_data_o[22] ,
+    \m3_io_wbs_data_o[21] ,
+    \m3_io_wbs_data_o[20] ,
+    \m3_io_wbs_data_o[19] ,
+    \m3_io_wbs_data_o[18] ,
+    \m3_io_wbs_data_o[17] ,
+    \m3_io_wbs_data_o[16] ,
+    \m3_io_wbs_data_o[15] ,
+    \m3_io_wbs_data_o[14] ,
+    \m3_io_wbs_data_o[13] ,
+    \m3_io_wbs_data_o[12] ,
+    \m3_io_wbs_data_o[11] ,
+    \m3_io_wbs_data_o[10] ,
+    \m3_io_wbs_data_o[9] ,
+    \m3_io_wbs_data_o[8] ,
+    \m3_io_wbs_data_o[7] ,
+    \m3_io_wbs_data_o[6] ,
+    \m3_io_wbs_data_o[5] ,
+    \m3_io_wbs_data_o[4] ,
+    \m3_io_wbs_data_o[3] ,
+    \m3_io_wbs_data_o[2] ,
+    \m3_io_wbs_data_o[1] ,
+    \m3_io_wbs_data_o[0] }),
+    .io_wbs_m2s_addr({\m1_io_wbs_m2s_addr[15] ,
+    \m1_io_wbs_m2s_addr[14] ,
+    \m1_io_wbs_m2s_addr[13] ,
+    \m1_io_wbs_m2s_addr[12] ,
+    \m1_io_wbs_m2s_addr[11] ,
+    \m1_io_wbs_m2s_addr[10] ,
+    \m1_io_wbs_m2s_addr[9] ,
+    \m1_io_wbs_m2s_addr[8] ,
+    \m1_io_wbs_m2s_addr[7] ,
+    \m1_io_wbs_m2s_addr[6] ,
+    \m1_io_wbs_m2s_addr[5] ,
+    \m1_io_wbs_m2s_addr[4] ,
+    \m1_io_wbs_m2s_addr[3] ,
+    \m1_io_wbs_m2s_addr[2] ,
+    \m1_io_wbs_m2s_addr[1] ,
+    \m1_io_wbs_m2s_addr[0] }),
+    .io_wbs_m2s_data({\m1_io_wbs_m2s_data[31] ,
+    \m1_io_wbs_m2s_data[30] ,
+    \m1_io_wbs_m2s_data[29] ,
+    \m1_io_wbs_m2s_data[28] ,
+    \m1_io_wbs_m2s_data[27] ,
+    \m1_io_wbs_m2s_data[26] ,
+    \m1_io_wbs_m2s_data[25] ,
+    \m1_io_wbs_m2s_data[24] ,
+    \m1_io_wbs_m2s_data[23] ,
+    \m1_io_wbs_m2s_data[22] ,
+    \m1_io_wbs_m2s_data[21] ,
+    \m1_io_wbs_m2s_data[20] ,
+    \m1_io_wbs_m2s_data[19] ,
+    \m1_io_wbs_m2s_data[18] ,
+    \m1_io_wbs_m2s_data[17] ,
+    \m1_io_wbs_m2s_data[16] ,
+    \m1_io_wbs_m2s_data[15] ,
+    \m1_io_wbs_m2s_data[14] ,
+    \m1_io_wbs_m2s_data[13] ,
+    \m1_io_wbs_m2s_data[12] ,
+    \m1_io_wbs_m2s_data[11] ,
+    \m1_io_wbs_m2s_data[10] ,
+    \m1_io_wbs_m2s_data[9] ,
+    \m1_io_wbs_m2s_data[8] ,
+    \m1_io_wbs_m2s_data[7] ,
+    \m1_io_wbs_m2s_data[6] ,
+    \m1_io_wbs_m2s_data[5] ,
+    \m1_io_wbs_m2s_data[4] ,
+    \m1_io_wbs_m2s_data[3] ,
+    \m1_io_wbs_m2s_data[2] ,
+    \m1_io_wbs_m2s_data[1] ,
+    \m1_io_wbs_m2s_data[0] }),
+    .io_wbs_m2s_sel({\m1_io_wbs_m2s_sel[3] ,
+    \m1_io_wbs_m2s_sel[2] ,
+    \m1_io_wbs_m2s_sel[1] ,
+    \m1_io_wbs_m2s_sel[0] }));
+ WB_InterConnect wb_inter_connect (.clock(wb_clk_i),
+    .io_dbus_rd_en(core_io_dbus_rd_en),
+    .io_dbus_valid(core_io_dbus_valid),
+    .io_dbus_wr_en(core_io_dbus_wr_en),
+    .io_dmem_io_cs(dmem_io_cs),
+    .io_dmem_io_wr_en(dmem_io_wr_en),
+    .io_ibus_valid(core_io_ibus_valid),
+    .io_imem_io_cs(imem_io_cs),
+    .io_imem_io_wr_en(imem_io_wr_en),
+    .io_m1_ack_i(m1_io_wbs_ack_o),
+    .io_m1_addr_sel(m1_io_ba_match),
+    .io_m2_ack_i(m2_io_wbs_ack_o),
+    .io_m2_addr_sel(m2_io_ba_match),
+    .io_m3_ack_i(m3_io_wbs_ack_o),
+    .io_m3_addr_sel(m3_io_ba_match),
+    .io_spi_clk(io_spi_clk),
+    .io_spi_clk_en(io_spi_clk_en),
+    .io_spi_cs(io_spi_cs),
+    .io_spi_cs_en(io_spi_cs_en),
+    .io_spi_irq(core_io_irq_spi_irq),
+    .io_spi_miso(io_in[1]),
+    .io_spi_mosi(io_spi_mosi),
+    .io_spi_mosi_en(io_spi_mosi_en),
+    .io_uart_irq(core_io_irq_uart_irq),
+    .io_uart_rx(io_in[0]),
+    .io_uart_tx(io_uart_tx),
+    .io_uart_tx_en(io_uart_tx_en),
+    .io_wbm_m2s_stb(m1_io_wbs_m2s_stb),
+    .io_wbm_m2s_we(m1_io_wbs_m2s_we),
+    .reset(wb_rst_i),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .io_dbus_addr({\core_io_dbus_addr[31] ,
+    \core_io_dbus_addr[30] ,
+    \core_io_dbus_addr[29] ,
+    \core_io_dbus_addr[28] ,
+    \core_io_dbus_addr[27] ,
+    \core_io_dbus_addr[26] ,
+    \core_io_dbus_addr[25] ,
+    \core_io_dbus_addr[24] ,
+    \core_io_dbus_addr[23] ,
+    \core_io_dbus_addr[22] ,
+    \core_io_dbus_addr[21] ,
+    \core_io_dbus_addr[20] ,
+    \core_io_dbus_addr[19] ,
+    \core_io_dbus_addr[18] ,
+    \core_io_dbus_addr[17] ,
+    \core_io_dbus_addr[16] ,
+    \core_io_dbus_addr[15] ,
+    \core_io_dbus_addr[14] ,
+    \core_io_dbus_addr[13] ,
+    \core_io_dbus_addr[12] ,
+    \core_io_dbus_addr[11] ,
+    \core_io_dbus_addr[10] ,
+    \core_io_dbus_addr[9] ,
+    \core_io_dbus_addr[8] ,
+    \core_io_dbus_addr[7] ,
+    \core_io_dbus_addr[6] ,
+    \core_io_dbus_addr[5] ,
+    \core_io_dbus_addr[4] ,
+    \core_io_dbus_addr[3] ,
+    \core_io_dbus_addr[2] ,
+    \core_io_dbus_addr[1] ,
+    \core_io_dbus_addr[0] }),
+    .io_dbus_ld_type({\core_io_dbus_ld_type[2] ,
+    \core_io_dbus_ld_type[1] ,
+    \core_io_dbus_ld_type[0] }),
+    .io_dbus_rdata({\core_io_dbus_rdata[31] ,
+    \core_io_dbus_rdata[30] ,
+    \core_io_dbus_rdata[29] ,
+    \core_io_dbus_rdata[28] ,
+    \core_io_dbus_rdata[27] ,
+    \core_io_dbus_rdata[26] ,
+    \core_io_dbus_rdata[25] ,
+    \core_io_dbus_rdata[24] ,
+    \core_io_dbus_rdata[23] ,
+    \core_io_dbus_rdata[22] ,
+    \core_io_dbus_rdata[21] ,
+    \core_io_dbus_rdata[20] ,
+    \core_io_dbus_rdata[19] ,
+    \core_io_dbus_rdata[18] ,
+    \core_io_dbus_rdata[17] ,
+    \core_io_dbus_rdata[16] ,
+    \core_io_dbus_rdata[15] ,
+    \core_io_dbus_rdata[14] ,
+    \core_io_dbus_rdata[13] ,
+    \core_io_dbus_rdata[12] ,
+    \core_io_dbus_rdata[11] ,
+    \core_io_dbus_rdata[10] ,
+    \core_io_dbus_rdata[9] ,
+    \core_io_dbus_rdata[8] ,
+    \core_io_dbus_rdata[7] ,
+    \core_io_dbus_rdata[6] ,
+    \core_io_dbus_rdata[5] ,
+    \core_io_dbus_rdata[4] ,
+    \core_io_dbus_rdata[3] ,
+    \core_io_dbus_rdata[2] ,
+    \core_io_dbus_rdata[1] ,
+    \core_io_dbus_rdata[0] }),
+    .io_dbus_st_type({\core_io_dbus_st_type[1] ,
+    \core_io_dbus_st_type[0] }),
+    .io_dbus_wdata({\core_io_dbus_wdata[31] ,
+    \core_io_dbus_wdata[30] ,
+    \core_io_dbus_wdata[29] ,
+    \core_io_dbus_wdata[28] ,
+    \core_io_dbus_wdata[27] ,
+    \core_io_dbus_wdata[26] ,
+    \core_io_dbus_wdata[25] ,
+    \core_io_dbus_wdata[24] ,
+    \core_io_dbus_wdata[23] ,
+    \core_io_dbus_wdata[22] ,
+    \core_io_dbus_wdata[21] ,
+    \core_io_dbus_wdata[20] ,
+    \core_io_dbus_wdata[19] ,
+    \core_io_dbus_wdata[18] ,
+    \core_io_dbus_wdata[17] ,
+    \core_io_dbus_wdata[16] ,
+    \core_io_dbus_wdata[15] ,
+    \core_io_dbus_wdata[14] ,
+    \core_io_dbus_wdata[13] ,
+    \core_io_dbus_wdata[12] ,
+    \core_io_dbus_wdata[11] ,
+    \core_io_dbus_wdata[10] ,
+    \core_io_dbus_wdata[9] ,
+    \core_io_dbus_wdata[8] ,
+    \core_io_dbus_wdata[7] ,
+    \core_io_dbus_wdata[6] ,
+    \core_io_dbus_wdata[5] ,
+    \core_io_dbus_wdata[4] ,
+    \core_io_dbus_wdata[3] ,
+    \core_io_dbus_wdata[2] ,
+    \core_io_dbus_wdata[1] ,
+    \core_io_dbus_wdata[0] }),
+    .io_dmem_io_addr({\dmem_io_addr[8] ,
+    \dmem_io_addr[7] ,
+    \dmem_io_addr[6] ,
+    \dmem_io_addr[5] ,
+    \dmem_io_addr[4] ,
+    \dmem_io_addr[3] ,
+    \dmem_io_addr[2] ,
+    \dmem_io_addr[1] ,
+    \dmem_io_addr[0] }),
+    .io_dmem_io_rdata({\dmem_io_rdata[31] ,
+    \dmem_io_rdata[30] ,
+    \dmem_io_rdata[29] ,
+    \dmem_io_rdata[28] ,
+    \dmem_io_rdata[27] ,
+    \dmem_io_rdata[26] ,
+    \dmem_io_rdata[25] ,
+    \dmem_io_rdata[24] ,
+    \dmem_io_rdata[23] ,
+    \dmem_io_rdata[22] ,
+    \dmem_io_rdata[21] ,
+    \dmem_io_rdata[20] ,
+    \dmem_io_rdata[19] ,
+    \dmem_io_rdata[18] ,
+    \dmem_io_rdata[17] ,
+    \dmem_io_rdata[16] ,
+    \dmem_io_rdata[15] ,
+    \dmem_io_rdata[14] ,
+    \dmem_io_rdata[13] ,
+    \dmem_io_rdata[12] ,
+    \dmem_io_rdata[11] ,
+    \dmem_io_rdata[10] ,
+    \dmem_io_rdata[9] ,
+    \dmem_io_rdata[8] ,
+    \dmem_io_rdata[7] ,
+    \dmem_io_rdata[6] ,
+    \dmem_io_rdata[5] ,
+    \dmem_io_rdata[4] ,
+    \dmem_io_rdata[3] ,
+    \dmem_io_rdata[2] ,
+    \dmem_io_rdata[1] ,
+    \dmem_io_rdata[0] }),
+    .io_dmem_io_st_type({\dmem_io_st_type[3] ,
+    \dmem_io_st_type[2] ,
+    \dmem_io_st_type[1] ,
+    \dmem_io_st_type[0] }),
+    .io_dmem_io_wdata({\dmem_io_wdata[31] ,
+    \dmem_io_wdata[30] ,
+    \dmem_io_wdata[29] ,
+    \dmem_io_wdata[28] ,
+    \dmem_io_wdata[27] ,
+    \dmem_io_wdata[26] ,
+    \dmem_io_wdata[25] ,
+    \dmem_io_wdata[24] ,
+    \dmem_io_wdata[23] ,
+    \dmem_io_wdata[22] ,
+    \dmem_io_wdata[21] ,
+    \dmem_io_wdata[20] ,
+    \dmem_io_wdata[19] ,
+    \dmem_io_wdata[18] ,
+    \dmem_io_wdata[17] ,
+    \dmem_io_wdata[16] ,
+    \dmem_io_wdata[15] ,
+    \dmem_io_wdata[14] ,
+    \dmem_io_wdata[13] ,
+    \dmem_io_wdata[12] ,
+    \dmem_io_wdata[11] ,
+    \dmem_io_wdata[10] ,
+    \dmem_io_wdata[9] ,
+    \dmem_io_wdata[8] ,
+    \dmem_io_wdata[7] ,
+    \dmem_io_wdata[6] ,
+    \dmem_io_wdata[5] ,
+    \dmem_io_wdata[4] ,
+    \dmem_io_wdata[3] ,
+    \dmem_io_wdata[2] ,
+    \dmem_io_wdata[1] ,
+    \dmem_io_wdata[0] }),
+    .io_ibus_addr({\core_io_ibus_addr[31] ,
+    \core_io_ibus_addr[30] ,
+    \core_io_ibus_addr[29] ,
+    \core_io_ibus_addr[28] ,
+    \core_io_ibus_addr[27] ,
+    \core_io_ibus_addr[26] ,
+    \core_io_ibus_addr[25] ,
+    \core_io_ibus_addr[24] ,
+    \core_io_ibus_addr[23] ,
+    \core_io_ibus_addr[22] ,
+    \core_io_ibus_addr[21] ,
+    \core_io_ibus_addr[20] ,
+    \core_io_ibus_addr[19] ,
+    \core_io_ibus_addr[18] ,
+    \core_io_ibus_addr[17] ,
+    \core_io_ibus_addr[16] ,
+    \core_io_ibus_addr[15] ,
+    \core_io_ibus_addr[14] ,
+    \core_io_ibus_addr[13] ,
+    \core_io_ibus_addr[12] ,
+    \core_io_ibus_addr[11] ,
+    \core_io_ibus_addr[10] ,
+    \core_io_ibus_addr[9] ,
+    \core_io_ibus_addr[8] ,
+    \core_io_ibus_addr[7] ,
+    \core_io_ibus_addr[6] ,
+    \core_io_ibus_addr[5] ,
+    \core_io_ibus_addr[4] ,
+    \core_io_ibus_addr[3] ,
+    \core_io_ibus_addr[2] ,
+    \core_io_ibus_addr[1] ,
+    \core_io_ibus_addr[0] }),
+    .io_ibus_inst({\core_io_ibus_inst[31] ,
+    \core_io_ibus_inst[30] ,
+    \core_io_ibus_inst[29] ,
+    \core_io_ibus_inst[28] ,
+    \core_io_ibus_inst[27] ,
+    \core_io_ibus_inst[26] ,
+    \core_io_ibus_inst[25] ,
+    \core_io_ibus_inst[24] ,
+    \core_io_ibus_inst[23] ,
+    \core_io_ibus_inst[22] ,
+    \core_io_ibus_inst[21] ,
+    \core_io_ibus_inst[20] ,
+    \core_io_ibus_inst[19] ,
+    \core_io_ibus_inst[18] ,
+    \core_io_ibus_inst[17] ,
+    \core_io_ibus_inst[16] ,
+    \core_io_ibus_inst[15] ,
+    \core_io_ibus_inst[14] ,
+    \core_io_ibus_inst[13] ,
+    \core_io_ibus_inst[12] ,
+    \core_io_ibus_inst[11] ,
+    \core_io_ibus_inst[10] ,
+    \core_io_ibus_inst[9] ,
+    \core_io_ibus_inst[8] ,
+    \core_io_ibus_inst[7] ,
+    \core_io_ibus_inst[6] ,
+    \core_io_ibus_inst[5] ,
+    \core_io_ibus_inst[4] ,
+    \core_io_ibus_inst[3] ,
+    \core_io_ibus_inst[2] ,
+    \core_io_ibus_inst[1] ,
+    \core_io_ibus_inst[0] }),
+    .io_imem_io_addr({\imem_io_addr[8] ,
+    \imem_io_addr[7] ,
+    \imem_io_addr[6] ,
+    \imem_io_addr[5] ,
+    \imem_io_addr[4] ,
+    \imem_io_addr[3] ,
+    \imem_io_addr[2] ,
+    \imem_io_addr[1] ,
+    \imem_io_addr[0] }),
+    .io_imem_io_rdata({\imem_io_rdata[31] ,
+    \imem_io_rdata[30] ,
+    \imem_io_rdata[29] ,
+    \imem_io_rdata[28] ,
+    \imem_io_rdata[27] ,
+    \imem_io_rdata[26] ,
+    \imem_io_rdata[25] ,
+    \imem_io_rdata[24] ,
+    \imem_io_rdata[23] ,
+    \imem_io_rdata[22] ,
+    \imem_io_rdata[21] ,
+    \imem_io_rdata[20] ,
+    \imem_io_rdata[19] ,
+    \imem_io_rdata[18] ,
+    \imem_io_rdata[17] ,
+    \imem_io_rdata[16] ,
+    \imem_io_rdata[15] ,
+    \imem_io_rdata[14] ,
+    \imem_io_rdata[13] ,
+    \imem_io_rdata[12] ,
+    \imem_io_rdata[11] ,
+    \imem_io_rdata[10] ,
+    \imem_io_rdata[9] ,
+    \imem_io_rdata[8] ,
+    \imem_io_rdata[7] ,
+    \imem_io_rdata[6] ,
+    \imem_io_rdata[5] ,
+    \imem_io_rdata[4] ,
+    \imem_io_rdata[3] ,
+    \imem_io_rdata[2] ,
+    \imem_io_rdata[1] ,
+    \imem_io_rdata[0] }),
+    .io_imem_io_st_type({\imem_io_st_type[3] ,
+    \imem_io_st_type[2] ,
+    \imem_io_st_type[1] ,
+    \imem_io_st_type[0] }),
+    .io_imem_io_wdata({\imem_io_wdata[31] ,
+    \imem_io_wdata[30] ,
+    \imem_io_wdata[29] ,
+    \imem_io_wdata[28] ,
+    \imem_io_wdata[27] ,
+    \imem_io_wdata[26] ,
+    \imem_io_wdata[25] ,
+    \imem_io_wdata[24] ,
+    \imem_io_wdata[23] ,
+    \imem_io_wdata[22] ,
+    \imem_io_wdata[21] ,
+    \imem_io_wdata[20] ,
+    \imem_io_wdata[19] ,
+    \imem_io_wdata[18] ,
+    \imem_io_wdata[17] ,
+    \imem_io_wdata[16] ,
+    \imem_io_wdata[15] ,
+    \imem_io_wdata[14] ,
+    \imem_io_wdata[13] ,
+    \imem_io_wdata[12] ,
+    \imem_io_wdata[11] ,
+    \imem_io_wdata[10] ,
+    \imem_io_wdata[9] ,
+    \imem_io_wdata[8] ,
+    \imem_io_wdata[7] ,
+    \imem_io_wdata[6] ,
+    \imem_io_wdata[5] ,
+    \imem_io_wdata[4] ,
+    \imem_io_wdata[3] ,
+    \imem_io_wdata[2] ,
+    \imem_io_wdata[1] ,
+    \imem_io_wdata[0] }),
+    .io_m1_data_i({\m1_io_wbs_data_o[31] ,
+    \m1_io_wbs_data_o[30] ,
+    \m1_io_wbs_data_o[29] ,
+    \m1_io_wbs_data_o[28] ,
+    \m1_io_wbs_data_o[27] ,
+    \m1_io_wbs_data_o[26] ,
+    \m1_io_wbs_data_o[25] ,
+    \m1_io_wbs_data_o[24] ,
+    \m1_io_wbs_data_o[23] ,
+    \m1_io_wbs_data_o[22] ,
+    \m1_io_wbs_data_o[21] ,
+    \m1_io_wbs_data_o[20] ,
+    \m1_io_wbs_data_o[19] ,
+    \m1_io_wbs_data_o[18] ,
+    \m1_io_wbs_data_o[17] ,
+    \m1_io_wbs_data_o[16] ,
+    \m1_io_wbs_data_o[15] ,
+    \m1_io_wbs_data_o[14] ,
+    \m1_io_wbs_data_o[13] ,
+    \m1_io_wbs_data_o[12] ,
+    \m1_io_wbs_data_o[11] ,
+    \m1_io_wbs_data_o[10] ,
+    \m1_io_wbs_data_o[9] ,
+    \m1_io_wbs_data_o[8] ,
+    \m1_io_wbs_data_o[7] ,
+    \m1_io_wbs_data_o[6] ,
+    \m1_io_wbs_data_o[5] ,
+    \m1_io_wbs_data_o[4] ,
+    \m1_io_wbs_data_o[3] ,
+    \m1_io_wbs_data_o[2] ,
+    \m1_io_wbs_data_o[1] ,
+    \m1_io_wbs_data_o[0] }),
+    .io_m2_data_i({\m2_io_wbs_data_o[31] ,
+    \m2_io_wbs_data_o[30] ,
+    \m2_io_wbs_data_o[29] ,
+    \m2_io_wbs_data_o[28] ,
+    \m2_io_wbs_data_o[27] ,
+    \m2_io_wbs_data_o[26] ,
+    \m2_io_wbs_data_o[25] ,
+    \m2_io_wbs_data_o[24] ,
+    \m2_io_wbs_data_o[23] ,
+    \m2_io_wbs_data_o[22] ,
+    \m2_io_wbs_data_o[21] ,
+    \m2_io_wbs_data_o[20] ,
+    \m2_io_wbs_data_o[19] ,
+    \m2_io_wbs_data_o[18] ,
+    \m2_io_wbs_data_o[17] ,
+    \m2_io_wbs_data_o[16] ,
+    \m2_io_wbs_data_o[15] ,
+    \m2_io_wbs_data_o[14] ,
+    \m2_io_wbs_data_o[13] ,
+    \m2_io_wbs_data_o[12] ,
+    \m2_io_wbs_data_o[11] ,
+    \m2_io_wbs_data_o[10] ,
+    \m2_io_wbs_data_o[9] ,
+    \m2_io_wbs_data_o[8] ,
+    \m2_io_wbs_data_o[7] ,
+    \m2_io_wbs_data_o[6] ,
+    \m2_io_wbs_data_o[5] ,
+    \m2_io_wbs_data_o[4] ,
+    \m2_io_wbs_data_o[3] ,
+    \m2_io_wbs_data_o[2] ,
+    \m2_io_wbs_data_o[1] ,
+    \m2_io_wbs_data_o[0] }),
+    .io_m3_data_i({\m3_io_wbs_data_o[31] ,
+    \m3_io_wbs_data_o[30] ,
+    \m3_io_wbs_data_o[29] ,
+    \m3_io_wbs_data_o[28] ,
+    \m3_io_wbs_data_o[27] ,
+    \m3_io_wbs_data_o[26] ,
+    \m3_io_wbs_data_o[25] ,
+    \m3_io_wbs_data_o[24] ,
+    \m3_io_wbs_data_o[23] ,
+    \m3_io_wbs_data_o[22] ,
+    \m3_io_wbs_data_o[21] ,
+    \m3_io_wbs_data_o[20] ,
+    \m3_io_wbs_data_o[19] ,
+    \m3_io_wbs_data_o[18] ,
+    \m3_io_wbs_data_o[17] ,
+    \m3_io_wbs_data_o[16] ,
+    \m3_io_wbs_data_o[15] ,
+    \m3_io_wbs_data_o[14] ,
+    \m3_io_wbs_data_o[13] ,
+    \m3_io_wbs_data_o[12] ,
+    \m3_io_wbs_data_o[11] ,
+    \m3_io_wbs_data_o[10] ,
+    \m3_io_wbs_data_o[9] ,
+    \m3_io_wbs_data_o[8] ,
+    \m3_io_wbs_data_o[7] ,
+    \m3_io_wbs_data_o[6] ,
+    \m3_io_wbs_data_o[5] ,
+    \m3_io_wbs_data_o[4] ,
+    \m3_io_wbs_data_o[3] ,
+    \m3_io_wbs_data_o[2] ,
+    \m3_io_wbs_data_o[1] ,
+    \m3_io_wbs_data_o[0] }),
+    .io_wbm_m2s_addr({\m1_io_wbs_m2s_addr[15] ,
+    \m1_io_wbs_m2s_addr[14] ,
+    \m1_io_wbs_m2s_addr[13] ,
+    \m1_io_wbs_m2s_addr[12] ,
+    \m1_io_wbs_m2s_addr[11] ,
+    \m1_io_wbs_m2s_addr[10] ,
+    \m1_io_wbs_m2s_addr[9] ,
+    \m1_io_wbs_m2s_addr[8] ,
+    \m1_io_wbs_m2s_addr[7] ,
+    \m1_io_wbs_m2s_addr[6] ,
+    \m1_io_wbs_m2s_addr[5] ,
+    \m1_io_wbs_m2s_addr[4] ,
+    \m1_io_wbs_m2s_addr[3] ,
+    \m1_io_wbs_m2s_addr[2] ,
+    \m1_io_wbs_m2s_addr[1] ,
+    \m1_io_wbs_m2s_addr[0] }),
+    .io_wbm_m2s_data({\m1_io_wbs_m2s_data[31] ,
+    \m1_io_wbs_m2s_data[30] ,
+    \m1_io_wbs_m2s_data[29] ,
+    \m1_io_wbs_m2s_data[28] ,
+    \m1_io_wbs_m2s_data[27] ,
+    \m1_io_wbs_m2s_data[26] ,
+    \m1_io_wbs_m2s_data[25] ,
+    \m1_io_wbs_m2s_data[24] ,
+    \m1_io_wbs_m2s_data[23] ,
+    \m1_io_wbs_m2s_data[22] ,
+    \m1_io_wbs_m2s_data[21] ,
+    \m1_io_wbs_m2s_data[20] ,
+    \m1_io_wbs_m2s_data[19] ,
+    \m1_io_wbs_m2s_data[18] ,
+    \m1_io_wbs_m2s_data[17] ,
+    \m1_io_wbs_m2s_data[16] ,
+    \m1_io_wbs_m2s_data[15] ,
+    \m1_io_wbs_m2s_data[14] ,
+    \m1_io_wbs_m2s_data[13] ,
+    \m1_io_wbs_m2s_data[12] ,
+    \m1_io_wbs_m2s_data[11] ,
+    \m1_io_wbs_m2s_data[10] ,
+    \m1_io_wbs_m2s_data[9] ,
+    \m1_io_wbs_m2s_data[8] ,
+    \m1_io_wbs_m2s_data[7] ,
+    \m1_io_wbs_m2s_data[6] ,
+    \m1_io_wbs_m2s_data[5] ,
+    \m1_io_wbs_m2s_data[4] ,
+    \m1_io_wbs_m2s_data[3] ,
+    \m1_io_wbs_m2s_data[2] ,
+    \m1_io_wbs_m2s_data[1] ,
+    \m1_io_wbs_m2s_data[0] }),
+    .io_wbm_m2s_sel({\m1_io_wbs_m2s_sel[3] ,
+    \m1_io_wbs_m2s_sel[2] ,
+    \m1_io_wbs_m2s_sel[1] ,
+    \m1_io_wbs_m2s_sel[0] }));
+ assign io_oeb[1] = io_spi_cs_en;
+ assign io_oeb[2] = io_spi_clk_en;
+ assign io_oeb[3] = io_spi_mosi_en;
+ assign io_oeb[4] = io_m1_io_pwm_high_en;
+ assign io_oeb[5] = io_m1_io_pwm_low_en;
+ assign io_oeb[6] = io_m2_io_pwm_high_en;
+ assign io_oeb[7] = io_m2_io_pwm_low_en;
+ assign io_oeb[8] = io_m3_io_pwm_high_en;
+ assign io_oeb[9] = io_m3_io_pwm_low_en;
+ assign io_out[0] = io_uart_tx;
+ assign io_out[1] = io_spi_cs;
+ assign io_out[2] = io_spi_clk;
+ assign io_out[3] = io_spi_mosi;
+ assign io_out[4] = io_m1_io_pwm_high;
+ assign io_out[5] = io_m1_io_pwm_low;
+ assign io_out[6] = io_m2_io_pwm_high;
+ assign io_out[7] = io_m2_io_pwm_low;
+ assign io_out[8] = io_m3_io_pwm_high;
+ assign io_out[9] = io_m3_io_pwm_low;
+endmodule
diff --git a/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag b/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..7125c2f
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag
@@ -0,0 +1,44883 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1651249211
+<< checkpaint >>
+rect -12658 -11586 596582 715522
+<< metal1 >>
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