|author||Jeff DiCorpo <firstname.lastname@example.org>||Sat Apr 30 22:52:48 2022 -0700|
|committer||Jeff DiCorpo <email@example.com>||Sat Apr 30 22:52:48 2022 -0700|
final gds oasis
UETRV-ECORE is a RISC-V based SoC integrating 3-stage pipelined core with multiple peripherals for embedded applications. Currently, the core implements RV32I ISA based on User-level ISA Version 2.0 and Privileged Architecture Version 1.11 supporting machine mode only. The core does not have any structural hazards, while data hazards are resolved using forwarding and stalling. Following is the status of current implementation:
The verilog rtl used in this repo is generated from Scala source which is available in a separate repository here. Further details bout the peripheral memory map, bootloader, example programs, testbenches etc. are also provided in that repo.