tree: ca4f2872a80135f05923c0ab75950eccfc76f47c [path history] [tgz]
  1. def/
  2. docs/
  3. gds/
  4. lef/
  5. mpw_precheck/
  6. openlane/
  7. signoff/
  8. spi/
  9. tapeout/
  10. verilog/
  11. .gitignore
  12. LICENSE
  13. Makefile
  14. README.md
README.md

Raster Engine

An implementation of rasterization engine using Skywater 130 nm PDK.

Even through open-source RISC-V processor architectures provide huge performance and flexibility for computation tasks, an accompanying GPU is required for user interaction and visualization. For this purpose, this project aims to integrate a rasterizer to the existing RISC-V core for the visualization purpose on the path of obtaining a fully open-source computational platform in the future.

The rasterizer can be programmed using the Wishbone interface. Since we don't have enough silicon area to put SRAMs for storing a frame, we made the signals that goes to VRAM output. So, to display the result of the rasterization engine, an FPGA with VRAM and VGA controller is needed.

Contributors

  • Can Kurt
  • Mehmet Fatih G├╝lakar