fix
diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz
index bbe83f6..62942f0 100644
--- a/gds/user_analog_project_wrapper.gds.gz
+++ b/gds/user_analog_project_wrapper.gds.gz
Binary files differ
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index 9d20872..106ecdd 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1647922527
+timestamp 1647922823
 << psubdiff >>
 rect 193788 665794 196518 666014
 rect 193788 663430 194026 665794
@@ -9751,7 +9751,8 @@
 rect 245920 490000 261942 490022
 rect 313468 490000 319246 493068
 rect 420318 490000 422470 490086
-rect 91216 486000 422470 490000
+rect 91216 486000 303062 490000
+rect 305276 486000 422470 490000
 rect 97266 465642 98176 486000
 rect 103556 485518 104170 486000
 rect 122018 485518 124932 486000
@@ -9782,11 +9783,13 @@
 rect 419220 449962 424204 450000
 rect 313734 447634 318786 449552
 rect 313676 442050 318850 447634
-rect 314104 431132 318786 442050
+rect 314104 433450 318786 442050
+rect 313690 431132 318786 433450
+rect 313690 428310 318708 431132
 rect 422600 428570 424204 449962
-rect 314104 426590 318786 428310
+rect 313690 425626 318786 428310
 rect 422600 426758 438628 428570
-rect 313814 424336 318786 426590
+rect 313814 424336 318786 425626
 rect 313814 423508 318828 424336
 rect 437936 424332 438390 426758
 rect 313756 410076 318930 423508
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
index c19e2f9..e9dd82a 100644
--- a/netgen/user_analog_project_wrapper.spice
+++ b/netgen/user_analog_project_wrapper.spice
@@ -88,7 +88,7 @@
 + la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
 + la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
 + la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
-+ vccd1 vccd2 vssa1 vdda2 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
 + wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
 + wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
 + wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
@@ -106,2207 +106,2207 @@
 + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
 + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
 + wbs_stb_i wbs_we_i
-C0 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in2 0.84fF
-C1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/div 0.01fF
-C2 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in3 1.27fF
-C3 io_analog[4] ro_complete_buffered_0/ro_complete_0/a4 0.20fF
-C4 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/REF 0.65fF
-C5 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in3 2.89fF
-C6 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in3 2.89fF
-C7 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/divider_0/clk 26.29fF
-C8 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in2 0.37fF
-C9 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in4 4.78fF
-C10 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.55fF
-C11 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
-C12 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a3 3.17fF
-C13 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C14 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Q 0.55fF
-C15 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.03fF
-C16 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF
-C17 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C18 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C19 pd_buffered_0/tapered_buf_0/in5 gpio_noesd[11] 26.29fF
-C20 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF
-C21 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/clk 0.01fF
-C22 ro_complete_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/ro_complete_0/a2 26.29fF
-C23 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF
-C24 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.38fF
-C25 io_analog[7] gpio_analog[6] 0.64fF
-C26 pd_buffered_0/tapered_buf_1/in1 pd_buffered_0/tapered_buf_1/in5 0.22fF
-C27 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.05fF
-C28 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF
-C29 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_1/B 0.18fF
-C30 ro_divider_buffered_0/tapered_buf_2/in4 ro_divider_buffered_0/tapered_buf_2/in5 29.21fF
-C31 filter_buffered_0/tapered_buf_1/in1 gpio_analog[17] 0.19fF
-C32 cp_buffered_0/tapered_buf_0/in4 cp_buffered_0/tapered_buf_0/in5 29.21fF
-C33 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/A 0.15fF
-C34 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/tapered_buf_2/in4 29.21fF
-C35 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_3/in3 1.27fF
-C36 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF
-C37 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.22fF
-C38 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C39 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in1 0.22fF
-C40 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF
-C41 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C42 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C43 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/divider_0/clk 1.30fF
-C44 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.35fF
-C45 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/clk 0.60fF
-C46 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/A 0.01fF
-C47 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.05fF
-C48 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C49 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF
-C50 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in3 1.27fF
-C51 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
-C52 pd_buffered_0/tapered_buf_0/in2 pd_buffered_0/tapered_buf_0/in3 1.27fF
-C53 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z3 0.65fF
-C54 io_analog[6] ro_divider_buffered_0/ro_complete_0/a1 0.20fF
-C55 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in1 0.22fF
-C56 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C57 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.80fF
-C58 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C59 ro_divider_buffered_0/tapered_buf_2/in2 ro_divider_buffered_0/tapered_buf_2/in5 0.84fF
-C60 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in3 1.27fF
-C61 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/tapered_buf_2/in1 0.22fF
-C62 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z1 0.01fF
-C63 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF
-C64 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF
-C65 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF
-C66 pll_full_buffered2_0/tapered_buf_1/in4 pll_full_buffered2_0/tapered_buf_1/in5 29.21fF
-C67 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C68 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.08fF
-C69 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C70 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/A 0.01fF
-C71 div_pd_buffered_0/divider_0/tspc_0/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.05fF
-C72 pd_buffered_0/pd_0/DIV io_analog[10] 0.52fF
-C73 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.05fF
-C74 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/Out 1.14fF
-C75 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
-C76 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Q 0.05fF
-C77 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C78 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a4 0.09fF
-C79 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a5 0.09fF
-C80 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF
-C81 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF
-C82 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in5 2.89fF
-C83 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF
-C84 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/and_0/OUT 0.03fF
-C85 io_analog[6] ro_divider_buffered_0/tapered_buf_6/in1 0.19fF
-C86 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
-C87 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C88 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF
-C89 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C90 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C91 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in3 1.27fF
-C92 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF
-C93 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/nor_1/B 0.06fF
-C94 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.36fF
-C95 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C96 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF
-C97 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF
-C98 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF
-C99 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C100 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in5 2.89fF
-C101 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF
-C102 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF
-C103 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C104 ro_complete_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/in5 29.21fF
-C105 ro_complete_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_1/in5 0.22fF
-C106 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/out 0.84fF
-C107 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.06fF
-C108 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C109 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C110 gpio_noesd[14] gpio_analog[9] 2.63fF
-C111 io_analog[6] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
-C112 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/DOWN 0.02fF
-C113 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/R 0.30fF
-C114 divider_buffered_0/tapered_buf_1/in2 divider_buffered_0/tapered_buf_1/in3 1.27fF
-C115 io_analog[3] gpio_analog[6] 0.53fF
-C116 io_analog[9] io_analog[8] 1.33fF
-C117 io_analog[4] ro_complete_buffered_0/ro_complete_0/a1 0.32fF
-C118 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in5 0.84fF
-C119 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in4 4.78fF
-C120 io_analog[10] div_pd_buffered_0/divider_0/mc2 0.64fF
-C121 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z2 1.07fF
-C122 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z4 0.15fF
-C123 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C124 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in3 1.27fF
-C125 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF
-C126 io_analog[4] io_analog[8] 1.24fF
-C127 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/tspc_0/Q 0.01fF
-C128 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF
-C129 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C130 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.36fF
-C131 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Q 0.05fF
-C132 ashish_0/a ashish_0/b 7.45fF
-C133 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C134 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
-C135 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/tapered_buf_3/in 0.11fF
-C136 gpio_noesd[10] io_analog[9] 3.45fF
-C137 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in2 0.84fF
-C138 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C139 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered1_0/pll_full_0/vco 1.58fF
-C140 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/R 0.51fF
-C141 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C142 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/UP 0.06fF
-C143 div_pd_buffered_0/tapered_buf_1/in1 div_pd_buffered_0/tapered_buf_1/in2 0.37fF
-C144 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/Z1 0.00fF
-C145 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.06fF
-C146 io_analog[3] ro_divider_buffered_0/ro_complete_0/a5 0.17fF
-C147 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C148 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/div 0.03fF
-C149 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/vco 0.06fF
-C150 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C151 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF
-C152 pd_buffered_0/pd_0/tspc_r_1/z5 pd_buffered_0/pd_0/tspc_r_0/z5 0.02fF
-C153 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF
-C154 pd_buffered_0/tapered_buf_2/in4 pd_buffered_0/tapered_buf_2/in3 4.78fF
-C155 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/UP 0.03fF
-C156 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/div 0.51fF
-C157 gpio_noesd[10] gpio_analog[10] 1.36fF
-C158 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
-C159 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/divider_0/mc2 26.29fF
-C160 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C161 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF
-C162 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in5 2.89fF
-C163 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C164 pd_buffered_0/tapered_buf_3/in4 pd_buffered_0/tapered_buf_3/in3 4.78fF
-C165 gpio_noesd[14] gpio_noesd[7] 2.93fF
-C166 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/clk 0.14fF
-C167 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/vco 0.64fF
-C168 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/cp_0/upbar 26.29fF
-C169 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.04fF
-C170 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF
-C171 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.01fF
-C172 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/upbar 0.29fF
-C173 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
-C174 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF
-C175 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a5 2.39fF
-C176 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C177 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in5 0.84fF
-C178 gpio_noesd[14] pll_full_buffered1_0/pll_full_0/vco 0.69fF
-C179 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/nor_1/A 0.03fF
-C180 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C181 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.12fF
-C182 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C183 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C184 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/div 0.65fF
-C185 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in3 1.27fF
-C186 cp_buffered_0/cp_0/upbar cp_buffered_0/cp_0/down 0.02fF
-C187 io_analog[4] io_analog[9] 1.28fF
-C188 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C189 pll_full_buffered1_0/tapered_buf_1/in4 pll_full_buffered1_0/tapered_buf_1/in5 29.21fF
-C190 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF
-C191 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/A 0.01fF
-C192 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF
-C193 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF
-C194 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in3 1.27fF
-C195 pll_full_buffered2_0/tapered_buf_3/in4 pll_full_buffered2_0/tapered_buf_3/in5 29.21fF
-C196 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/nor_1/B 0.38fF
-C197 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z1 0.00fF
-C198 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C199 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/divider_0/clk 0.05fF
-C200 pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.04fF
-C201 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in2 0.37fF
-C202 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z1 0.03fF
-C203 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z3 0.05fF
-C204 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C205 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C206 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.29fF
-C207 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C208 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF
-C209 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.16fF
-C210 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in1 0.37fF
-C211 io_analog[9] gpio_analog[10] 3.28fF
-C212 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in3 2.89fF
-C213 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/nor_1/A 0.01fF
-C214 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF
-C215 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C216 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_1/Z2 0.15fF
-C217 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF
-C218 cp_buffered_0/tapered_buf_0/in5 cp_buffered_0/cp_0/down 26.29fF
-C219 io_analog[9] ro_divider_buffered_0/tapered_buf_1/in1 0.19fF
-C220 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C221 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.03fF
-C222 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z1 0.03fF
-C223 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF
-C224 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF
-C225 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.04fF
-C226 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.26fF
-C227 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z2 0.01fF
-C228 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/clk 0.05fF
-C229 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF
-C230 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C231 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_divider_buffered_0/divider_0/clk 1.43fF
-C232 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
-C233 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in4 29.21fF
-C234 divider_buffered_0/tapered_buf_1/in4 divider_buffered_0/tapered_buf_1/in5 29.21fF
-C235 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C236 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in4 4.78fF
-C237 gpio_analog[8] io_analog[9] 1.10fF
-C238 div_pd_buffered_0/pd_0/tspc_r_1/Z4 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
-C239 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_1/Z4 0.02fF
-C240 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z3 0.06fF
-C241 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF
-C242 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C243 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in5 0.84fF
-C244 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in4 4.78fF
-C245 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF
-C246 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF
-C247 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/B 0.18fF
-C248 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.65fF
-C249 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF
-C250 divider_buffered_0/divider_0/prescaler_0/nand_0/z1 divider_buffered_0/divider_0/and_0/OUT 0.01fF
-C251 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.09fF
-C252 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 3.73fF
-C253 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.36fF
-C254 io_analog[3] ro_complete_buffered_0/ro_complete_0/a4 0.17fF
-C255 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z1 0.06fF
-C256 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C257 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in2 0.37fF
-C258 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in5 2.89fF
-C259 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C260 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/UP 0.33fF
-C261 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.45fF
-C262 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF
-C263 ro_complete_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_2/in1 0.37fF
-C264 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/Z1 0.04fF
-C265 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF
-C266 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C267 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C268 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in5 0.84fF
-C269 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in4 4.78fF
-C270 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.45fF
-C271 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF
-C272 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/A 0.80fF
-C273 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
-C274 io_clamp_low[1] io_clamp_high[1] 0.53fF
-C275 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C276 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF
-C277 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C278 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.80fF
-C279 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C280 io_analog[6] gpio_analog[6] 0.64fF
-C281 io_analog[7] ro_complete_buffered_0/ro_complete_0/a1 0.23fF
-C282 io_analog[7] io_analog[8] 1.38fF
-C283 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in4 29.21fF
-C284 ro_divider_buffered_0/tapered_buf_7/in4 ro_divider_buffered_0/tapered_buf_7/in5 29.21fF
-C285 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in5 0.84fF
-C286 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/DOWN 0.11fF
-C287 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z1 0.17fF
-C288 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in5 0.84fF
-C289 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF
-C290 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z3 0.16fF
-C291 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z2 1.07fF
-C292 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C293 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF
-C294 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C295 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C296 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C297 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C298 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z2 0.36fF
-C299 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
-C300 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
-C301 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C302 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF
-C303 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF
-C304 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C305 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF
-C306 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C307 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
-C308 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/R 0.01fF
-C309 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF
-C310 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
-C311 io_analog[5] ro_divider_buffered_0/ro_complete_0/a1 0.30fF
-C312 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/clk 0.01fF
-C313 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C314 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C315 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in5 29.21fF
-C316 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z4 0.00fF
-C317 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C318 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in5 0.22fF
-C319 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF
-C320 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF
-C321 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C322 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/vco 0.26fF
-C323 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Q 0.55fF
-C324 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_divider_buffered_0/divider_0/clk 1.30fF
-C325 gpio_analog[3] gpio_noesd[4] 1.38fF
-C326 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in4 4.78fF
-C327 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C328 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/div 0.02fF
-C329 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF
-C330 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C331 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/UP 0.61fF
-C332 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF
-C333 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C334 pll_full_buffered1_0/tapered_buf_1/in1 io_analog[10] 0.19fF
-C335 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C336 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C337 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z4 0.00fF
-C338 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in2 0.37fF
-C339 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF
-C340 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C341 io_analog[5] io_clamp_low[1] 0.53fF
-C342 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
-C343 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
-C344 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.11fF
-C345 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C346 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z1 0.01fF
-C347 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_0/Q 0.22fF
-C348 pd_buffered_0/tapered_buf_2/in4 pd_buffered_0/tapered_buf_2/in5 29.21fF
-C349 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C350 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
-C351 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in5 0.84fF
-C352 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF
-C353 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in4 29.21fF
-C354 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_0/Qbar 0.03fF
-C355 io_analog[5] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
-C356 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/REF 0.17fF
-C357 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z2 1.07fF
-C358 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/vco 0.06fF
-C359 io_analog[9] io_analog[7] 1.28fF
-C360 io_analog[3] ro_complete_buffered_0/ro_complete_0/a1 0.17fF
-C361 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/div 4.07fF
-C362 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C363 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_1/in5 26.29fF
-C364 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in5 0.84fF
-C365 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in4 4.78fF
-C366 io_analog[3] io_analog[8] 1.02fF
-C367 io_analog[4] io_analog[7] 1.11fF
-C368 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C369 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C370 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/out1 0.06fF
-C371 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF
-C372 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a1 3.18fF
-C373 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z1 0.01fF
-C374 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_0/Q 0.22fF
-C375 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in5 0.84fF
-C376 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C377 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/A 0.80fF
-C378 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C379 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/a_1710_0# 0.83fF
-C380 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C381 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z2 1.07fF
-C382 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z3 0.38fF
-C383 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z4 0.12fF
-C384 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C385 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in3 1.27fF
-C386 gpio_analog[3] io_analog[0] 3.87fF
-C387 gpio_noesd[10] gpio_noesd[7] 0.73fF
-C388 gpio_analog[9] io_analog[9] 0.93fF
-C389 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C390 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/down 0.32fF
-C391 gpio_analog[9] pd_buffered_0/tapered_buf_1/in1 0.19fF
-C392 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/vco 0.64fF
-C393 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C394 pll_full_buffered1_0/pll_full_0/div pll_full_buffered1_0/pll_full_0/vco 2.26fF
-C395 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/clk 0.12fF
-C396 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF
-C397 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF
-C398 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C399 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/B 0.30fF
-C400 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/divider_0/Out 0.20fF
-C401 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF
-C402 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
-C403 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z2 1.07fF
-C404 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z3 0.38fF
-C405 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z4 0.12fF
-C406 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Z4 0.12fF
-C407 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C408 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/DOWN 0.36fF
-C409 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
-C410 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z2 0.40fF
-C411 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/Out 0.04fF
-C412 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/clk 0.29fF
-C413 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/Z1 0.36fF
-C414 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF
-C415 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C416 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C417 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in1 0.37fF
-C418 gpio_noesd[11] gpio_noesd[8] 0.55fF
-C419 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C420 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF
-C421 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.21fF
-C422 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF
-C423 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF
-C424 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF
-C425 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF
-C426 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF
-C427 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/clk 0.26fF
-C428 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF
-C429 filter_buffered_0/tapered_buf_0/in4 filter_buffered_0/tapered_buf_0/in5 29.21fF
-C430 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Z4 0.12fF
-C431 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C432 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/clk 0.64fF
-C433 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in1 0.37fF
-C434 pll_full_buffered2_0/tapered_buf_2/in4 pll_full_buffered2_0/tapered_buf_2/in5 29.21fF
-C435 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF
-C436 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/div 0.05fF
-C437 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C438 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.29fF
-C439 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/Z1 0.36fF
-C440 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF
-C441 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
-C442 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/A 0.26fF
-C443 pll_full_buffered2_0/tapered_buf_0/in5 pll_full_buffered2_0/pll_full_0/ref 26.29fF
-C444 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF
-C445 gpio_noesd[11] io_analog[10] 1.30fF
-C446 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 0.38fF
-C447 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.14fF
-C448 gpio_noesd[7] io_analog[9] 1.42fF
-C449 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in3 1.27fF
-C450 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C451 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z2 0.01fF
-C452 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C453 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C454 io_analog[3] io_analog[9] 1.00fF
-C455 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C456 io_analog[3] io_analog[4] 0.88fF
-C457 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C458 ro_divider_buffered_0/tapered_buf_3/in4 ro_divider_buffered_0/tapered_buf_3/in5 29.21fF
-C459 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.04fF
-C460 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF
-C461 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/nor_1/B 0.22fF
-C462 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/clk 0.04fF
-C463 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C464 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C465 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF
-C466 cp_buffered_0/cp_0/a_10_n50# cp_buffered_0/cp_0/a_1710_0# 0.04fF
-C467 gpio_noesd[7] gpio_analog[10] 0.77fF
-C468 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/R 0.21fF
-C469 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF
-C470 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF
-C471 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C472 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C473 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF
-C474 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C475 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF
-C476 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C477 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF
-C478 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/clk 0.04fF
-C479 divider_buffered_0/tapered_buf_2/in1 divider_buffered_0/tapered_buf_2/in5 0.22fF
-C480 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in2 0.84fF
-C481 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/clk 0.64fF
-C482 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C483 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C484 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF
-C485 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF
-C486 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.27fF
-C487 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.05fF
-C488 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.05fF
-C489 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C490 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C491 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C492 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C493 gpio_analog[8] gpio_noesd[7] 1.68fF
-C494 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF
-C495 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/divider_0/clk 26.29fF
-C496 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in1 0.22fF
-C497 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
-C498 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Z4 0.65fF
-C499 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C500 gpio_noesd[7] pll_full_buffered2_0/tapered_buf_5/in 0.54fF
-C501 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in5 0.84fF
-C502 pll_full_buffered2_0/tapered_buf_5/in5 pll_full_buffered2_0/tapered_buf_5/in1 0.22fF
-C503 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C504 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C505 gpio_noesd[8] gpio_noesd[12] 0.46fF
-C506 pd_buffered_0/tapered_buf_1/in2 pd_buffered_0/tapered_buf_1/in5 0.84fF
-C507 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF
-C508 ro_complete_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_4/in5 29.21fF
-C509 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/and_0/B 0.29fF
-C510 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
-C511 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/A 0.01fF
-C512 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in5 2.89fF
-C513 pll_full_buffered1_0/tapered_buf_0/in pll_full_buffered1_0/tapered_buf_0/in1 0.19fF
-C514 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/clk 0.64fF
-C515 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C516 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z2 0.11fF
-C517 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/div 0.45fF
-C518 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/UP 0.45fF
-C519 io_analog[10] gpio_noesd[12] 1.57fF
-C520 io_analog[9] div_pd_buffered_0/divider_0/clk 0.65fF
-C521 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
-C522 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/out1 0.31fF
-C523 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/nor_1/B 0.21fF
-C524 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z4 0.21fF
-C525 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF
-C526 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF
-C527 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z3 0.45fF
-C528 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.04fF
-C529 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/A 0.26fF
-C530 cp_buffered_0/tapered_buf_2/in2 cp_buffered_0/tapered_buf_2/in3 1.27fF
-C531 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.05fF
-C532 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C533 ro_complete_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_1/in5 29.21fF
-C534 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
-C535 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C536 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/a3 0.09fF
-C537 io_analog[5] gpio_analog[6] 0.64fF
-C538 io_analog[6] ro_complete_buffered_0/ro_complete_0/a1 0.22fF
-C539 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C540 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/div 0.03fF
-C541 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 0.31fF
-C542 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/vco 0.26fF
-C543 io_analog[6] io_analog[8] 1.24fF
-C544 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C545 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z2 0.23fF
-C546 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C547 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/div 0.17fF
-C548 pd_buffered_0/tapered_buf_1/in2 pd_buffered_0/tapered_buf_1/in3 1.27fF
-C549 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/nor_1/A 0.15fF
-C550 cp_buffered_0/tapered_buf_1/in4 cp_buffered_0/tapered_buf_1/in5 29.21fF
-C551 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C552 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z3 0.45fF
-C553 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/A 0.26fF
-C554 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
-C555 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF
-C556 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z4 0.02fF
-C557 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C558 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
-C559 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/UP 0.61fF
-C560 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in5 0.84fF
-C561 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in4 4.78fF
-C562 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C563 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.16fF
-C564 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.22fF
-C565 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C566 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C567 io_analog[5] ro_complete_buffered_0/tapered_buf_5/in1 0.19fF
-C568 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.45fF
-C569 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C570 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
-C571 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C572 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.12fF
-C573 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C574 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
-C575 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z3 0.65fF
-C576 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in5 0.22fF
-C577 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF
-C578 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C579 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C580 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF
-C581 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z3 0.16fF
-C582 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.22fF
-C583 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF
-C584 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Z4 0.21fF
-C585 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C586 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/divider_0/clk 0.05fF
-C587 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z3 0.06fF
-C588 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/Out 0.44fF
-C589 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 0.22fF
-C590 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/nor_1/A 0.03fF
-C591 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in3 1.27fF
-C592 ro_divider_buffered_0/divider_0/and_0/A ro_divider_buffered_0/divider_0/and_0/B 0.18fF
-C593 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C594 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/div 0.65fF
-C595 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF
-C596 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.05fF
-C597 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF
-C598 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Z4 0.65fF
-C599 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C600 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C601 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C602 io_analog[5] ro_divider_buffered_0/tapered_buf_5/in1 0.19fF
-C603 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/UP 0.21fF
-C604 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF
-C605 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/tapered_buf_2/in3 2.89fF
-C606 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C607 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C608 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/out1 0.06fF
-C609 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Z4 0.21fF
-C610 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z3 0.45fF
-C611 filter_buffered_0/tapered_buf_0/in5 gpio_analog[17] 26.29fF
-C612 ro_divider_buffered_0/tapered_buf_0/in5 gpio_noesd[5] 26.29fF
-C613 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 gpio_noesd[14] 26.29fF
-C614 div_pd_buffered_0/divider_0/and_0/A div_pd_buffered_0/divider_0/and_0/B 0.18fF
-C615 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C616 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C617 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.12fF
-C618 gpio_noesd[10] pd_buffered_0/tapered_buf_2/in5 26.29fF
-C619 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF
-C620 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C621 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/div 0.25fF
-C622 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF
-C623 io_analog[3] ro_complete_buffered_0/ro_complete_0/a5 0.15fF
-C624 io_analog[6] io_analog[9] 1.28fF
-C625 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A 0.15fF
-C626 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.09fF
-C627 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in5 0.84fF
-C628 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in4 4.78fF
-C629 io_analog[3] io_analog[7] 0.92fF
-C630 io_analog[4] io_analog[6] 1.25fF
-C631 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_0/B 0.15fF
-C632 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C633 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C634 ro_divider_buffered_0/tapered_buf_8/in5 ro_divider_buffered_0/ro_complete_0/a0 26.29fF
-C635 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C636 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C637 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF
-C638 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.21fF
-C639 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/tspc_1/Z2 1.07fF
-C640 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.07fF
-C641 io_clamp_low[0] io_clamp_high[0] 0.53fF
-C642 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/clk 0.26fF
-C643 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in5 2.89fF
-C644 io_analog[10] pll_full_buffered2_0/pll_full_0/div 0.47fF
-C645 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C646 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C647 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C648 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/UP 1.14fF
-C649 ashish_0/b io_analog[0] 8.93fF
-C650 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF
-C651 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.05fF
-C652 gpio_analog[9] gpio_noesd[7] 1.96fF
-C653 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF
-C654 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF
-C655 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF
-C656 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/nor_1/B 0.38fF
-C657 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Q 0.05fF
-C658 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in3 1.27fF
-C659 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF
-C660 div_pd_buffered_0/pd_0/DOWN gpio_noesd[12] 0.33fF
-C661 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in3 2.89fF
-C662 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z2 0.11fF
-C663 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.06fF
-C664 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
-C665 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C666 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C667 pd_buffered_0/tapered_buf_1/in2 pd_buffered_0/tapered_buf_1/in1 0.37fF
-C668 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/clk 0.26fF
-C669 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z3 0.45fF
-C670 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/divider_0/clk 0.05fF
-C671 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in2 0.37fF
-C672 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C673 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C674 gpio_analog[6] ro_complete_buffered_0/tapered_buf_0/in1 0.19fF
-C675 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C676 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
-C677 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/nor_1/A 0.35fF
-C678 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C679 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/R 0.36fF
-C680 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF
-C681 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF
-C682 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF
-C683 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C684 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in5 2.89fF
-C685 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/divider_0/mc2 0.34fF
-C686 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in2 1.27fF
-C687 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/R 0.21fF
-C688 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/z5 0.03fF
-C689 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.13fF
-C690 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF
-C691 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C692 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C693 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a2 1.38fF
-C694 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/tspc_1/Z2 0.01fF
-C695 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C696 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.35fF
-C697 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/vco 0.60fF
-C698 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in3 4.78fF
-C699 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C700 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF
-C701 divider_buffered_0/divider_0/tspc_2/Z4 divider_buffered_0/divider_0/nor_1/B 0.02fF
-C702 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in2 0.37fF
-C703 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in3 1.27fF
-C704 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in1 0.37fF
-C705 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in1 0.22fF
-C706 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF
-C707 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C708 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF
-C709 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C710 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C711 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF
-C712 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z4 0.12fF
-C713 pd_buffered_0/tapered_buf_0/in3 pd_buffered_0/tapered_buf_0/in4 4.78fF
-C714 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF
-C715 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C716 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C717 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF
-C718 gpio_noesd[14] gpio_noesd[8] 2.61fF
-C719 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in3 2.89fF
-C720 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.06fF
-C721 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z2 0.11fF
-C722 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C723 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF
-C724 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF
-C725 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.27fF
-C726 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.05fF
-C727 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z4 0.15fF
-C728 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C729 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in2 0.37fF
-C730 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF
-C731 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF
-C732 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF
-C733 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
-C734 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C735 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in4 4.78fF
-C736 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in2 0.84fF
-C737 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C738 gpio_noesd[13] gpio_noesd[12] 0.45fF
-C739 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/A 0.04fF
-C740 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in2 0.84fF
-C741 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_0/B 0.22fF
-C742 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_0/Q 0.15fF
-C743 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C744 cp_buffered_0/tapered_buf_1/in5 gpio_noesd[9] 26.29fF
-C745 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/R 0.51fF
-C746 gpio_noesd[14] io_analog[10] 2.21fF
-C747 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.45fF
-C748 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a3 2.04fF
-C749 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z4 0.15fF
-C750 io_analog[9] pll_full_buffered2_0/tapered_buf_3/in 0.61fF
-C751 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in3 1.27fF
-C752 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in5 0.22fF
-C753 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C754 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
-C755 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF
-C756 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.36fF
-C757 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/Out 0.05fF
-C758 ro_complete_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_6/in5 29.21fF
-C759 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/nor_1/A 0.15fF
-C760 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/R 0.03fF
-C761 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF
-C762 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C763 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.15fF
-C764 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF
-C765 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/UP 0.03fF
-C766 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C767 pll_full_buffered2_0/tapered_buf_2/in1 pll_full_buffered2_0/pll_full_0/div 0.19fF
-C768 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in5 2.89fF
-C769 ro_divider_buffered_0/tapered_buf_6/in5 ro_divider_buffered_0/ro_complete_0/a2 26.29fF
-C770 gpio_noesd[14] gpio_noesd[9] 2.58fF
-C771 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C772 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C773 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF
-C774 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in4 4.78fF
-C775 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.16fF
-C776 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
-C777 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in1 0.37fF
-C778 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in5 2.89fF
-C779 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/a0 3.46fF
-C780 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C781 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C782 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z4 0.36fF
-C783 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z4 0.00fF
-C784 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C785 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in2 0.37fF
-C786 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C787 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 3.73fF
-C788 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF
-C789 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in1 0.37fF
-C790 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF
-C791 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C792 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in5 0.84fF
-C793 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in2 0.37fF
-C794 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C795 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C796 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C797 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C798 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in4 29.21fF
-C799 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/B 0.08fF
-C800 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF
-C801 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in5 0.22fF
-C802 io_analog[9] divider_buffered_0/tapered_buf_0/in1 0.19fF
-C803 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C804 gpio_analog[5] ro_divider_buffered_0/divider_0/Out 0.75fF
-C805 ro_divider_buffered_0/tapered_buf_1/in1 ro_divider_buffered_0/tapered_buf_1/in2 0.37fF
-C806 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.02fF
-C807 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C808 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF
-C809 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.12fF
-C810 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C811 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/pd_0/DOWN 0.19fF
-C812 io_analog[5] ro_complete_buffered_0/ro_complete_0/a1 0.22fF
-C813 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in4 29.21fF
-C814 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.06fF
-C815 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF
-C816 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF
-C817 io_analog[5] io_analog[8] 1.24fF
-C818 io_analog[6] io_analog[7] 1.12fF
-C819 ro_divider_buffered_0/tapered_buf_6/in4 ro_divider_buffered_0/tapered_buf_6/in5 29.21fF
-C820 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C821 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C822 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C823 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.02fF
-C824 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C825 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/clk 0.45fF
-C826 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/clk 0.14fF
-C827 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C828 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.14fF
-C829 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/out 26.29fF
-C830 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C831 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in5 0.22fF
-C832 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/tspc_r_0/Z4 0.04fF
-C833 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C834 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C835 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.65fF
-C836 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C837 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C838 gpio_analog[7] io_analog[10] 2.78fF
-C839 div_pd_buffered_0/tapered_buf_2/in2 div_pd_buffered_0/tapered_buf_2/in3 1.27fF
-C840 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
-C841 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF
-C842 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C843 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF
-C844 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF
-C845 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in4 4.78fF
-C846 gpio_analog[8] cp_buffered_0/cp_0/down 0.25fF
-C847 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF
-C848 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C849 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in5 0.22fF
-C850 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in4 29.21fF
-C851 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C852 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 io_analog[2] 26.29fF
-C853 pd_buffered_0/tapered_buf_2/in1 pd_buffered_0/tapered_buf_2/in5 0.22fF
-C854 ashish_0/a io_analog[1] 8.93fF
-C855 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A 0.15fF
-C856 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.09fF
-C857 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/tapered_buf_0/in2 0.37fF
-C858 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF
-C859 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF
-C860 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C861 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C862 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.43fF
-C863 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_0/Q 0.45fF
-C864 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.07fF
-C865 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in1 0.22fF
-C866 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.14fF
-C867 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in1 0.37fF
-C868 io_analog[10] pll_full_buffered2_0/tapered_buf_0/in1 0.19fF
-C869 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/and_0/OUT 0.14fF
-C870 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_0/B 0.15fF
-C871 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.30fF
-C872 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in1 0.22fF
-C873 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF
-C874 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.04fF
-C875 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF
-C876 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/vco 0.05fF
-C877 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in2 0.37fF
-C878 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_0/Q 0.01fF
-C879 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF
-C880 pd_buffered_0/pd_0/tspc_r_0/Z2 pd_buffered_0/pd_0/tspc_r_0/Z4 0.14fF
-C881 gpio_analog[3] ashish_0/b 0.27fF
-C882 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in5 0.84fF
-C883 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/DIV 0.51fF
-C884 pll_full_buffered1_0/tapered_buf_0/in2 pll_full_buffered1_0/tapered_buf_0/in3 1.27fF
-C885 pll_full_buffered1_0/tapered_buf_1/in5 pll_full_buffered1_0/pll_full_0/ref 26.29fF
-C886 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF
-C887 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
-C888 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF
-C889 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C890 io_analog[5] io_analog[9] 1.28fF
-C891 io_analog[3] io_analog[6] 1.03fF
-C892 io_analog[4] io_analog[5] 20.14fF
-C893 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in4 29.21fF
-C894 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
-C895 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C896 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a4 0.12fF
-C897 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C898 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF
-C899 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
-C900 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/clk 0.45fF
-C901 divider_buffered_0/tapered_buf_2/in4 divider_buffered_0/tapered_buf_2/in3 4.78fF
-C902 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in5 0.84fF
-C903 io_analog[9] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.53fF
-C904 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 0.06fF
-C905 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/R 0.36fF
-C906 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF
-C907 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF
-C908 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
-C909 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in3 1.27fF
-C910 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF
-C911 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.13fF
-C912 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C913 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C914 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C915 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C916 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/mc2 0.04fF
-C917 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C918 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/vco 0.60fF
-C919 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/REF 0.04fF
-C920 div_pd_buffered_0/tapered_buf_4/in4 div_pd_buffered_0/tapered_buf_4/in5 29.21fF
-C921 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z2 0.14fF
-C922 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C923 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C924 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C925 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/R 0.01fF
-C926 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
-C927 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C928 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C929 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/clk 0.45fF
-C930 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_3/in3 4.78fF
-C931 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/B 0.20fF
-C932 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.00fF
-C933 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
-C934 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C935 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/divider_0/clk 0.05fF
-C936 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in5 0.84fF
-C937 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C938 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 divider_buffered_0/divider_0/clk 0.12fF
-C939 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.06fF
-C940 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C941 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z4 0.65fF
-C942 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF
-C943 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C944 gpio_analog[3] gpio_noesd[5] 0.96fF
-C945 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C946 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.09fF
-C947 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 0.09fF
-C948 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/UP 0.33fF
-C949 gpio_noesd[10] gpio_noesd[8] 0.51fF
-C950 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/DOWN 0.11fF
-C951 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.17fF
-C952 gpio_noesd[14] gpio_noesd[13] 2.55fF
-C953 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF
-C954 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C955 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C956 filter_buffered_0/tapered_buf_1/in4 filter_buffered_0/tapered_buf_1/in5 29.21fF
-C957 io_analog[4] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
-C958 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C959 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C960 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/nor_1/A 0.15fF
-C961 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/a0 0.09fF
-C962 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF
-C963 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF
-C964 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C965 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C966 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/tspc_2/Z4 0.65fF
-C967 pll_full_buffered2_0/tapered_buf_3/in5 pll_full_buffered2_0/tapered_buf_3/out 26.29fF
-C968 ro_divider_buffered_0/divider_0/and_0/B ro_divider_buffered_0/divider_0/and_0/Z1 0.07fF
-C969 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 29.21fF
-C970 pd_buffered_0/tapered_buf_2/in3 pd_buffered_0/tapered_buf_2/in5 2.89fF
-C971 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C972 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/div 0.17fF
-C973 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
-C974 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/mc2 0.33fF
-C975 gpio_noesd[10] io_analog[10] 1.21fF
-C976 pll_full_buffered2_0/tapered_buf_5/in4 pll_full_buffered2_0/tapered_buf_5/in5 29.21fF
-C977 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in3 1.27fF
-C978 divider_buffered_0/tapered_buf_1/in2 divider_buffered_0/tapered_buf_1/in1 0.37fF
-C979 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF
-C980 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C981 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C982 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF
-C983 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C984 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/vco 0.15fF
-C985 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in3 4.78fF
-C986 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C987 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C988 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/R 0.03fF
-C989 div_pd_buffered_0/divider_0/and_0/B div_pd_buffered_0/divider_0/and_0/Z1 0.07fF
-C990 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.00fF
-C991 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/A 0.16fF
-C992 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.06fF
-C993 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
-C994 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C995 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
-C996 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in3 4.78fF
-C997 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a3 3.17fF
-C998 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C999 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF
-C1000 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF
-C1001 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
-C1002 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C1003 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C1004 io_analog[9] gpio_noesd[8] 0.91fF
-C1005 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF
-C1006 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF
-C1007 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z3 0.38fF
-C1008 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
-C1009 io_analog[4] io_clamp_high[0] 0.53fF
-C1010 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF
-C1011 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C1012 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C1013 pd_buffered_0/pd_0/tspc_r_0/Z2 pd_buffered_0/pd_0/R 0.21fF
-C1014 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF
-C1015 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF
-C1016 pd_buffered_0/pd_0/DOWN gpio_noesd[10] 0.54fF
-C1017 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.35fF
-C1018 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/clk 0.60fF
-C1019 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C1020 pll_full_buffered2_0/pll_full_0/cp_0/vbias pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# 0.19fF
-C1021 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C1022 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.19fF
-C1023 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C1024 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.30fF
-C1025 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
-C1026 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF
-C1027 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/div 0.05fF
-C1028 io_analog[9] io_analog[10] 1065.06fF
-C1029 gpio_noesd[8] gpio_analog[10] 0.48fF
-C1030 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.33fF
-C1031 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
-C1032 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C1033 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in5 2.89fF
-C1034 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in5 2.89fF
-C1035 div_pd_buffered_0/tapered_buf_0/in4 div_pd_buffered_0/tapered_buf_0/in5 29.21fF
-C1036 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF
-C1037 pll_full_buffered2_0/tapered_buf_2/in4 pll_full_buffered2_0/tapered_buf_2/in3 4.78fF
-C1038 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C1039 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.22fF
-C1040 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C1041 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C1042 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.35fF
-C1043 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/clk 0.60fF
-C1044 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C1045 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z2 1.07fF
-C1046 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/divider_0/clk 0.05fF
-C1047 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.06fF
-C1048 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/nor_1/B 0.30fF
-C1049 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C1050 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1051 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C1052 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C1053 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.11fF
-C1054 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.08fF
-C1055 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C1056 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.47fF
-C1057 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C1058 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.14fF
-C1059 io_analog[10] gpio_analog[10] 1.17fF
-C1060 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1061 gpio_noesd[9] io_analog[9] 1.19fF
-C1062 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in2 0.37fF
-C1063 divider_buffered_0/tapered_buf_1/in2 divider_buffered_0/tapered_buf_1/in5 0.84fF
-C1064 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF
-C1065 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C1066 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
-C1067 ro_divider_buffered_0/tapered_buf_2/in1 ro_divider_buffered_0/tapered_buf_2/in5 0.22fF
-C1068 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z4 0.02fF
-C1069 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z2 0.23fF
-C1070 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1071 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF
-C1072 io_analog[9] ro_divider_buffered_0/divider_0/Out 1.19fF
-C1073 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF
-C1074 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/div 0.04fF
-C1075 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/vco 0.29fF
-C1076 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in5 2.89fF
-C1077 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C1078 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.45fF
-C1079 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C1080 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C1081 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 1.21fF
-C1082 pll_full_buffered1_0/tapered_buf_0/in2 pll_full_buffered1_0/tapered_buf_0/in5 0.84fF
-C1083 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in4 4.78fF
-C1084 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in2 0.84fF
-C1085 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 0.38fF
-C1086 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C1087 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF
-C1088 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.20fF
-C1089 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C1090 io_analog[5] io_analog[7] 1.11fF
-C1091 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
-C1092 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.06fF
-C1093 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C1094 gpio_analog[8] io_analog[10] 1.48fF
-C1095 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C1096 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/B 0.01fF
-C1097 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/clk 0.12fF
-C1098 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C1099 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.04fF
-C1100 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C1101 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/vco 1.27fF
-C1102 pll_full_buffered2_0/tapered_buf_4/in4 pll_full_buffered2_0/tapered_buf_4/in5 29.21fF
-C1103 io_analog[6] io_clamp_high[2] 0.53fF
-C1104 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a0 0.47fF
-C1105 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF
-C1106 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/R 0.30fF
-C1107 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF
-C1108 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.16fF
-C1109 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
-C1110 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_0/Z4 0.02fF
-C1111 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in5 0.84fF
-C1112 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in4 4.78fF
-C1113 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF
-C1114 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/out 0.61fF
-C1115 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.35fF
-C1116 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in5 2.89fF
-C1117 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/divider_0/mc2 26.29fF
-C1118 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/R 0.29fF
-C1119 div_pd_buffered_0/tapered_buf_4/in5 gpio_noesd[13] 26.29fF
-C1120 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.04fF
-C1121 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/vco 0.05fF
-C1122 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in5 0.22fF
-C1123 gpio_noesd[9] gpio_analog[8] 2.46fF
-C1124 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/B 0.06fF
-C1125 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/nor_1/A 0.21fF
-C1126 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C1127 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_0/B 0.06fF
-C1128 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered2_0/pll_full_0/div 0.04fF
-C1129 cp_buffered_0/cp_0/out cp_buffered_0/cp_0/down 0.79fF
-C1130 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF
-C1131 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
-C1132 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C1133 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.47fF
-C1134 gpio_analog[5] ro_divider_buffered_0/divider_0/mc2 0.49fF
-C1135 div_pd_buffered_0/divider_0/tspc_0/Z2 div_pd_buffered_0/divider_0/tspc_0/Z3 0.16fF
-C1136 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
-C1137 divider_buffered_0/tapered_buf_1/in5 gpio_noesd[4] 26.29fF
-C1138 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C1139 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.00fF
-C1140 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF
-C1141 div_pd_buffered_0/tapered_buf_3/in4 div_pd_buffered_0/tapered_buf_3/in5 29.21fF
-C1142 io_analog[9] divider_buffered_0/divider_0/clk 0.40fF
-C1143 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/tapered_buf_3/in 0.03fF
-C1144 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF
-C1145 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/B 0.18fF
-C1146 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C1147 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1148 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 0.31fF
-C1149 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.15fF
-C1150 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C1151 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.14fF
-C1152 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C1153 gpio_analog[3] gpio_analog[6] 1.30fF
-C1154 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C1155 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C1156 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.31fF
-C1157 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
-C1158 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.04fF
-C1159 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C1160 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in5 0.84fF
-C1161 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in4 4.78fF
-C1162 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z2 0.19fF
-C1163 io_analog[3] io_analog[5] 0.93fF
-C1164 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/Out 0.05fF
-C1165 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/UP 2.89fF
-C1166 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C1167 div_pd_buffered_0/tapered_buf_0/in5 div_pd_buffered_0/tapered_buf_0/in1 0.22fF
-C1168 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z3 0.65fF
-C1169 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C1170 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/B 0.20fF
-C1171 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.35fF
-C1172 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C1173 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in3 1.27fF
-C1174 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a3 0.13fF
-C1175 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z2 0.15fF
-C1176 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C1177 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in2 0.37fF
-C1178 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.29fF
-C1179 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/and_0/OUT 0.06fF
-C1180 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C1181 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C1182 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.09fF
-C1183 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 0.09fF
-C1184 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C1185 pd_buffered_0/pd_0/DOWN pd_buffered_0/tapered_buf_0/in1 0.19fF
-C1186 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.22fF
-C1187 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF
-C1188 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C1189 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C1190 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in5 0.22fF
-C1191 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/REF 0.12fF
-C1192 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.06fF
-C1193 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/R 0.61fF
-C1194 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in5 2.89fF
-C1195 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.15fF
-C1196 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C1197 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.05fF
-C1198 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in5 2.89fF
-C1199 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/nor_1/B 0.30fF
-C1200 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/Z1 0.04fF
-C1201 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z2 0.01fF
-C1202 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/clk 0.05fF
-C1203 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF
-C1204 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.09fF
-C1205 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
-C1206 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/R 0.61fF
-C1207 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/UP 0.03fF
-C1208 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF
-C1209 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.51fF
-C1210 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C1211 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/vco 0.15fF
-C1212 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/mc2 0.05fF
-C1213 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in3 2.89fF
-C1214 gpio_analog[9] gpio_noesd[8] 1.10fF
-C1215 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.02fF
-C1216 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.08fF
-C1217 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1218 io_analog[8] ro_divider_buffered_0/tapered_buf_8/in1 0.19fF
-C1219 io_analog[3] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
-C1220 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.04fF
-C1221 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z2 0.36fF
-C1222 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C1223 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_0/B 0.06fF
-C1224 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/Z1 0.04fF
-C1225 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z2 0.01fF
-C1226 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/clk 0.05fF
-C1227 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/clk 0.45fF
-C1228 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF
-C1229 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.05fF
-C1230 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF
-C1231 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C1232 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in5 29.21fF
-C1233 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF
-C1234 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C1235 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
-C1236 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF
-C1237 gpio_analog[9] io_analog[10] 1.15fF
-C1238 gpio_analog[3] gpio_analog[5] 1.06fF
-C1239 io_analog[9] gpio_noesd[13] 2.15fF
-C1240 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.12fF
-C1241 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF
-C1242 divider_buffered_0/tapered_buf_1/in3 divider_buffered_0/tapered_buf_1/in5 2.89fF
-C1243 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
-C1244 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
-C1245 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C1246 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C1247 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in5 0.22fF
-C1248 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in2 1.27fF
-C1249 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C1250 pll_full_buffered1_0/pll_full_0/cp_0/vbias pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# 0.19fF
-C1251 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C1252 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/B 0.18fF
-C1253 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z2 0.14fF
-C1254 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF
-C1255 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/div 0.27fF
-C1256 pd_buffered_0/pd_0/DIV pd_buffered_0/tapered_buf_1/in5 26.29fF
-C1257 ro_divider_buffered_0/tapered_buf_0/in3 ro_divider_buffered_0/tapered_buf_0/in2 1.27fF
-C1258 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.00fF
-C1259 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
-C1260 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/A 0.01fF
-C1261 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
-C1262 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF
-C1263 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C1264 pll_full_buffered1_0/tapered_buf_0/in4 pll_full_buffered1_0/tapered_buf_0/in5 29.21fF
-C1265 gpio_analog[9] gpio_noesd[9] 1.46fF
-C1266 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF
-C1267 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.45fF
-C1268 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C1269 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C1270 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C1271 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in4 4.78fF
-C1272 io_analog[8] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
-C1273 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.51fF
-C1274 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF
-C1275 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C1276 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C1277 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C1278 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a4 0.09fF
-C1279 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a5 0.09fF
-C1280 div_pd_buffered_0/tapered_buf_1/in4 div_pd_buffered_0/tapered_buf_1/in3 4.78fF
-C1281 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.00fF
-C1282 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_0/Q 0.14fF
-C1283 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
-C1284 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/clk 0.01fF
-C1285 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in5 0.22fF
-C1286 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z1 0.03fF
-C1287 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C1288 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C1289 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.11fF
-C1290 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1291 ro_complete_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_5/in5 29.21fF
-C1292 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF
-C1293 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C1294 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1295 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/tapered_buf_0/in5 0.22fF
-C1296 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF
-C1297 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/UP 0.45fF
-C1298 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C1299 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF
-C1300 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C1301 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
-C1302 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.35fF
-C1303 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/vco 0.29fF
-C1304 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/tapered_buf_2/in2 0.84fF
-C1305 gpio_noesd[7] io_analog[10] 5.73fF
-C1306 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C1307 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1308 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in5 2.89fF
-C1309 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in2 1.27fF
-C1310 filter_buffered_0/filter_0/v gpio_analog[17] 0.54fF
-C1311 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in5 0.22fF
-C1312 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/DOWN 0.03fF
-C1313 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z3 0.06fF
-C1314 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 29.21fF
-C1315 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF
-C1316 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/Out 0.05fF
-C1317 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF
-C1318 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.65fF
-C1319 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C1320 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/divider_0/clk 0.10fF
-C1321 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C1322 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
-C1323 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C1324 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF
-C1325 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C1326 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/vco 1.27fF
-C1327 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF
-C1328 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/R 0.27fF
-C1329 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/UP 0.21fF
-C1330 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF
-C1331 gpio_noesd[9] gpio_noesd[7] 3.28fF
-C1332 pll_full_buffered1_0/pll_full_0/vco io_analog[10] 0.56fF
-C1333 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/Z2 0.36fF
-C1334 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.16fF
-C1335 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1336 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 1.21fF
-C1337 ro_divider_buffered_0/tapered_buf_2/in1 ro_divider_buffered_0/tapered_buf_2/in2 0.37fF
-C1338 div_pd_buffered_0/pd_0/UP div_pd_buffered_0/tapered_buf_0/in1 0.19fF
-C1339 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/nor_1/B 1.21fF
-C1340 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C1341 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF
-C1342 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z3 0.38fF
-C1343 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF
-C1344 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/nor_1/B 0.47fF
-C1345 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/UP 0.11fF
-C1346 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.08fF
-C1347 io_analog[5] io_analog[6] 21.00fF
-C1348 ro_divider_buffered_0/tapered_buf_5/in4 ro_divider_buffered_0/tapered_buf_5/in5 29.21fF
-C1349 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C1350 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.14fF
-C1351 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/vco 0.51fF
-C1352 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in4 4.78fF
-C1353 ro_divider_buffered_0/tapered_buf_7/in5 ro_divider_buffered_0/ro_complete_0/a1 26.29fF
-C1354 io_analog[4] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
-C1355 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/in1 0.22fF
-C1356 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
-C1357 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C1358 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.03fF
-C1359 pll_full_buffered2_0/tapered_buf_2/in2 pll_full_buffered2_0/tapered_buf_2/in1 0.37fF
-C1360 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/nor_0/B 0.22fF
-C1361 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C1362 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
-C1363 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF
-C1364 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in3 2.89fF
-C1365 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/tapered_buf_3/in1 0.22fF
-C1366 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a1 3.18fF
-C1367 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C1368 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/pll_full_0/vco 0.19fF
-C1369 ro_complete_buffered_0/tapered_buf_3/in1 io_analog[7] 0.19fF
-C1370 io_analog[9] pll_full_buffered2_0/tapered_buf_1/in1 0.19fF
-C1371 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C1372 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C1373 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C1374 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/div 0.12fF
-C1375 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in5 0.22fF
-C1376 io_analog[10] div_pd_buffered_0/divider_0/clk 0.61fF
-C1377 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1378 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.08fF
-C1379 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF
-C1380 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C1381 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
-C1382 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a5 2.39fF
-C1383 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1384 io_analog[4] ro_divider_buffered_0/tapered_buf_4/in1 0.19fF
-C1385 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/B 0.08fF
-C1386 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/nor_0/B 0.22fF
-C1387 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C1388 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/clk 0.01fF
-C1389 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in5 0.22fF
-C1390 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z2 0.23fF
-C1391 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C1392 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/divider_0/clk 1.30fF
-C1393 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C1394 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.40fF
-C1395 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/Out 0.04fF
-C1396 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/clk 0.29fF
-C1397 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C1398 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/tapered_buf_3/in 0.02fF
-C1399 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.30fF
-C1400 io_analog[1] io_analog[0] 8.34fF
-C1401 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF
-C1402 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C1403 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_1/in5 26.29fF
-C1404 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Out1 0.05fF
-C1405 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.02fF
-C1406 io_analog[6] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
-C1407 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in2 0.37fF
-C1408 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF
-C1409 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/nor_0/B 0.42fF
-C1410 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.03fF
-C1411 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF
-C1412 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/A 0.35fF
-C1413 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C1414 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C1415 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/clk 0.51fF
-C1416 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/and_0/B 0.78fF
-C1417 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF
-C1418 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.31fF
-C1419 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C1420 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF
-C1421 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C1422 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.40fF
-C1423 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/clk 0.29fF
-C1424 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z1 0.03fF
-C1425 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z3 0.05fF
-C1426 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Q 0.04fF
-C1427 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C1428 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/divider_0/clk 1.27fF
-C1429 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.05fF
-C1430 gpio_analog[10] div_pd_buffered_0/tapered_buf_3/in1 0.19fF
-C1431 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in4 4.78fF
-C1432 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF
-C1433 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1434 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.09fF
-C1435 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Q 0.04fF
-C1436 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF
-C1437 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C1438 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C1439 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C1440 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
-C1441 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in5 2.89fF
-C1442 io_analog[4] ro_divider_buffered_0/ro_complete_0/a3 0.23fF
-C1443 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a4 0.13fF
-C1444 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF
-C1445 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in2 0.84fF
-C1446 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/R 0.61fF
-C1447 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/nor_0/B 0.47fF
-C1448 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF
-C1449 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1450 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 4.79fF
-C1451 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C1452 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C1453 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C1454 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF
-C1455 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C1456 io_analog[4] ro_complete_buffered_0/ro_complete_0/a2 0.37fF
-C1457 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.18fF
-C1458 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C1459 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z2 0.16fF
-C1460 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1461 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/nor_0/B 0.47fF
-C1462 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z3 0.05fF
-C1463 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
-C1464 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
-C1465 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C1466 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C1467 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C1468 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in5 2.89fF
-C1469 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/B 0.18fF
-C1470 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C1471 ro_divider_buffered_0/tapered_buf_0/in1 ro_divider_buffered_0/divider_0/Out 0.19fF
-C1472 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/out1 0.31fF
-C1473 ro_divider_buffered_0/divider_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/tspc_0/Q 0.15fF
-C1474 divider_buffered_0/tapered_buf_1/in4 divider_buffered_0/tapered_buf_1/in3 4.78fF
-C1475 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/tapered_buf_3/in 5.03fF
-C1476 gpio_analog[7] cp_buffered_0/tapered_buf_2/in1 0.19fF
-C1477 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in4 4.78fF
-C1478 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF
-C1479 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
-C1480 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C1481 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C1482 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF
-C1483 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z1 0.09fF
-C1484 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF
-C1485 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
-C1486 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C1487 gpio_analog[8] cp_buffered_0/tapered_buf_0/in1 0.19fF
-C1488 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C1489 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/out1 0.31fF
-C1490 div_pd_buffered_0/divider_0/tspc_1/Z4 div_pd_buffered_0/divider_0/tspc_0/Q 0.15fF
-C1491 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered2_0/pll_full_0/vco 1.36fF
-C1492 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in2 0.84fF
-C1493 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_1/B 0.35fF
-C1494 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
-C1495 pll_full_buffered2_0/tapered_buf_5/in pll_full_buffered2_0/tapered_buf_5/in1 0.19fF
-C1496 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/and_0/B 0.29fF
-C1497 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.18fF
-C1498 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C1499 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in3 1.27fF
-C1500 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.01fF
-C1501 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF
-C1502 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C1503 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C1504 gpio_noesd[14] gpio_noesd[11] 2.58fF
-C1505 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C1506 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C1507 gpio_noesd[7] gpio_noesd[13] 0.80fF
-C1508 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.04fF
-C1509 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C1510 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in3 1.27fF
-C1511 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/R 0.36fF
-C1512 div_pd_buffered_0/pd_0/tspc_r_1/Z1 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF
-C1513 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF
-C1514 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
-C1515 ro_divider_buffered_0/tapered_buf_5/in5 ro_divider_buffered_0/ro_complete_0/a3 26.29fF
-C1516 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z4 0.36fF
-C1517 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Q 0.05fF
-C1518 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.35fF
-C1519 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z2 0.01fF
-C1520 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/and_0/B 0.78fF
-C1521 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/nor_1/B 0.01fF
-C1522 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF
-C1523 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C1524 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C1525 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.06fF
-C1526 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF
-C1527 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF
-C1528 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/and_0/B 0.29fF
-C1529 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF
-C1530 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in5 2.89fF
-C1531 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/nor_1/B 0.20fF
-C1532 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in4 4.78fF
-C1533 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C1534 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1535 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered1_0/pll_full_0/div 0.04fF
-C1536 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/clk 0.11fF
-C1537 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.00fF
-C1538 io_analog[3] ro_complete_buffered_0/tapered_buf_1/in1 0.19fF
-C1539 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in2 0.84fF
-C1540 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C1541 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1542 io_analog[7] ro_divider_buffered_0/ro_complete_0/a0 0.33fF
-C1543 io_analog[5] io_clamp_high[1] 0.53fF
-C1544 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a1 1.84fF
-C1545 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF
-C1546 divider_buffered_0/divider_0/tspc_0/Z4 divider_buffered_0/divider_0/tspc_0/Z2 0.36fF
-C1547 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C1548 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1549 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF
-C1550 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
-C1551 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1552 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF
-C1553 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z2 0.14fF
-C1554 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z3 0.05fF
-C1555 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
-C1556 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
-C1557 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in5 2.89fF
-C1558 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C1559 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF
-C1560 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1561 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.05fF
-C1562 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/REF 0.19fF
-C1563 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C1564 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C1565 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1566 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in5 2.89fF
-C1567 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF
-C1568 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C1569 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
-C1570 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z2 0.14fF
-C1571 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
-C1572 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
-C1573 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/clk 0.26fF
-C1574 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C1575 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in1 0.22fF
-C1576 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF
-C1577 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C1578 gpio_noesd[8] pll_full_buffered2_0/tapered_buf_3/in 0.23fF
-C1579 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/Out 0.04fF
-C1580 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.06fF
-C1581 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/Out 0.42fF
-C1582 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in5 0.22fF
-C1583 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C1584 ro_complete_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/in1 0.22fF
-C1585 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
-C1586 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z4 0.00fF
-C1587 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.14fF
-C1588 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.00fF
-C1589 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.14fF
-C1590 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/vco 0.51fF
-C1591 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in2 0.37fF
-C1592 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.29fF
-C1593 pd_buffered_0/tapered_buf_3/in1 io_analog[10] 0.19fF
-C1594 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in4 4.78fF
-C1595 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C1596 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Z2 0.16fF
-C1597 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered2_0/pll_full_0/vco 1.58fF
-C1598 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF
-C1599 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C1600 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in3 1.27fF
-C1601 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in1 0.37fF
-C1602 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/nor_1/B 0.38fF
-C1603 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1604 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C1605 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C1606 gpio_noesd[14] gpio_noesd[12] 2.57fF
-C1607 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C1608 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF
-C1609 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z3 0.06fF
-C1610 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C1611 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C1612 io_analog[10] pll_full_buffered2_0/tapered_buf_3/in 0.42fF
-C1613 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Q 0.51fF
-C1614 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z2 0.01fF
-C1615 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C1616 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C1617 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z2 1.07fF
-C1618 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z3 0.38fF
-C1619 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z4 0.12fF
-C1620 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in 0.19fF
-C1621 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C1622 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.32fF
-C1623 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF
-C1624 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.08fF
-C1625 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF
-C1626 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C1627 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
-C1628 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.19fF
-C1629 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF
-C1630 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C1631 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/nor_1/B 1.21fF
-C1632 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in4 4.78fF
-C1633 io_analog[3] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
-C1634 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Q 0.51fF
-C1635 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C1636 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C1637 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/clk 0.51fF
-C1638 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C1639 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF
-C1640 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C1641 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1642 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/pd_0/REF 26.29fF
-C1643 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF
-C1644 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.30fF
-C1645 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.20fF
-C1646 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/out1 0.06fF
-C1647 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/B 0.31fF
-C1648 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/Z1 0.36fF
-C1649 io_analog[6] ro_complete_buffered_0/tapered_buf_4/in1 0.19fF
-C1650 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z3 0.06fF
-C1651 gpio_analog[3] io_analog[1] 1.96fF
-C1652 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z3 0.65fF
-C1653 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.55fF
-C1654 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.11fF
-C1655 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.33fF
-C1656 pd_buffered_0/tapered_buf_1/in4 pd_buffered_0/tapered_buf_1/in5 29.21fF
-C1657 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.22fF
-C1658 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C1659 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF
-C1660 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in5 0.22fF
-C1661 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
-C1662 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C1663 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in2 0.37fF
-C1664 div_pd_buffered_0/pd_0/and_pd_0/Z1 div_pd_buffered_0/pd_0/UP 0.06fF
-C1665 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C1666 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.20fF
-C1667 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1668 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/nor_1/B 1.21fF
-C1669 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF
-C1670 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1671 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.09fF
-C1672 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in5 0.84fF
-C1673 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in4 4.78fF
-C1674 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF
-C1675 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C1676 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1677 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF
-C1678 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/pd_0/REF 26.29fF
-C1679 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/R 0.03fF
-C1680 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z4 0.12fF
-C1681 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C1682 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF
-C1683 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/div 0.04fF
-C1684 io_analog[5] ro_divider_buffered_0/ro_complete_0/a2 0.35fF
-C1685 gpio_noesd[9] cp_buffered_0/cp_0/down 0.38fF
-C1686 io_analog[10] div_pd_buffered_0/tapered_buf_1/in1 0.19fF
-C1687 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C1688 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1689 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in2 0.37fF
-C1690 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF
-C1691 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/and_0/OUT 0.14fF
-C1692 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/clk 0.51fF
-C1693 pd_buffered_0/tapered_buf_1/in3 pd_buffered_0/tapered_buf_1/in4 4.78fF
-C1694 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/vco 0.55fF
-C1695 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1696 gpio_analog[4] gpio_noesd[4] 0.91fF
-C1697 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1698 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C1699 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.01fF
-C1700 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF
-C1701 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
-C1702 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.04fF
-C1703 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF
-C1704 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C1705 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C1706 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C1707 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in5 0.84fF
-C1708 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in4 4.78fF
-C1709 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF
-C1710 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/UP 0.03fF
-C1711 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.36fF
-C1712 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C1713 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C1714 io_analog[4] ro_divider_buffered_0/ro_complete_0/a4 0.19fF
-C1715 io_analog[3] ro_divider_buffered_0/ro_complete_0/a3 0.23fF
-C1716 ro_divider_buffered_0/tapered_buf_3/in5 ro_divider_buffered_0/ro_complete_0/a5 26.29fF
-C1717 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C1718 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.01fF
-C1719 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C1720 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF
-C1721 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/B 0.08fF
-C1722 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF
-C1723 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C1724 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
-C1725 pll_full_buffered2_0/tapered_buf_0/in4 pll_full_buffered2_0/tapered_buf_0/in5 29.21fF
-C1726 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C1727 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C1728 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z3 0.05fF
-C1729 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF
-C1730 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered1_0/pll_full_0/vco 1.36fF
-C1731 io_analog[3] ro_complete_buffered_0/ro_complete_0/a2 0.22fF
-C1732 pll_full_buffered2_0/tapered_buf_5/in5 gpio_noesd[7] 26.29fF
-C1733 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF
-C1734 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Q 0.04fF
-C1735 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.13fF
-C1736 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in5 0.22fF
-C1737 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/clk 0.04fF
-C1738 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C1739 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C1740 div_pd_buffered_0/tapered_buf_0/in5 gpio_noesd[12] 26.29fF
-C1741 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF
-C1742 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C1743 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z2 1.07fF
-C1744 gpio_noesd[11] gpio_noesd[10] 6.19fF
-C1745 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.21fF
-C1746 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/B 0.31fF
-C1747 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C1748 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
-C1749 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF
-C1750 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF
-C1751 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C1752 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C1753 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in3 2.89fF
-C1754 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a3 2.04fF
-C1755 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z4 0.12fF
-C1756 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF
-C1757 io_analog[7] ro_divider_buffered_0/tapered_buf_7/in1 0.19fF
-C1758 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in2 0.84fF
-C1759 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C1760 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.18fF
-C1761 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF
-C1762 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
-C1763 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/div 0.19fF
-C1764 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
-C1765 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1766 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/a3 0.09fF
-C1767 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_1/B 0.06fF
-C1768 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.14fF
-C1769 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C1770 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/B 0.31fF
-C1771 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C1772 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
-C1773 io_analog[10] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.36fF
-C1774 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in5 2.89fF
-C1775 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.00fF
-C1776 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C1777 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1778 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF
-C1779 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1780 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF
-C1781 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
-C1782 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/a0 3.46fF
-C1783 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C1784 io_analog[8] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
-C1785 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z4 0.21fF
-C1786 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.12fF
-C1787 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in5 0.84fF
-C1788 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in4 4.78fF
-C1789 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.01fF
-C1790 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C1791 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C1792 divider_buffered_0/tapered_buf_0/in2 divider_buffered_0/tapered_buf_0/in3 1.27fF
-C1793 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C1794 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1795 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z4 0.00fF
-C1796 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/div 0.01fF
-C1797 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C1798 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF
-C1799 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z3 0.16fF
-C1800 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z4 0.22fF
-C1801 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C1802 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C1803 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
-C1804 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_1/Z2 0.21fF
-C1805 pd_buffered_0/pd_0/tspc_r_1/z5 pd_buffered_0/pd_0/DOWN 0.03fF
-C1806 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1807 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/div 0.12fF
-C1808 gpio_noesd[11] io_analog[9] 3.74fF
-C1809 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z3 0.45fF
-C1810 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF
-C1811 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF
-C1812 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C1813 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C1814 io_analog[4] ro_complete_buffered_0/tapered_buf_6/in1 0.19fF
-C1815 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C1816 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C1817 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1818 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 0.22fF
-C1819 io_analog[6] ro_divider_buffered_0/ro_complete_0/a0 0.21fF
-C1820 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/clk 0.04fF
-C1821 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C1822 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C1823 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/A 0.01fF
-C1824 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.78fF
-C1825 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
-C1826 io_analog[4] ro_divider_buffered_0/ro_complete_0/a1 0.21fF
-C1827 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a5 0.13fF
-C1828 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C1829 divider_buffered_0/divider_0/and_0/A divider_buffered_0/divider_0/and_0/B 0.18fF
-C1830 ro_divider_buffered_0/ro_complete_0/cbank_2/v ro_divider_buffered_0/divider_0/clk 1.36fF
-C1831 gpio_noesd[11] gpio_analog[10] 0.49fF
-C1832 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C1833 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF
-C1834 ashish_0/a io_analog[0] 4.11fF
-C1835 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered1_0/pll_full_0/vco 1.58fF
-C1836 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 0.03fF
-C1837 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C1838 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z3 0.38fF
-C1839 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF
-C1840 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C1841 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C1842 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in3 2.89fF
-C1843 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Q 0.55fF
-C1844 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.06fF
-C1845 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C1846 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1847 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in5 2.89fF
-C1848 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
-C1849 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
-C1850 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C1851 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.35fF
-C1852 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C1853 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C1854 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_0/B 0.06fF
-C1855 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.32fF
-C1856 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF
-C1857 divider_buffered_0/tapered_buf_0/in3 divider_buffered_0/tapered_buf_0/in4 4.78fF
-C1858 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF
-C1859 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C1860 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/tapered_buf_3/in 0.32fF
-C1861 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF
-C1862 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF
-C1863 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/div 0.27fF
-C1864 io_analog[4] ro_complete_buffered_0/ro_complete_0/a0 0.33fF
-C1865 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_1/B 0.51fF
-C1866 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C1867 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in3 1.27fF
-C1868 io_analog[10] gpio_noesd[8] 3.39fF
-C1869 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C1870 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1871 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/ro_complete_0/a1 26.29fF
-C1872 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C1873 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1874 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF
-C1875 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_divider_buffered_0/divider_0/clk 1.30fF
-C1876 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.33fF
-C1877 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in3 1.27fF
-C1878 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
-C1879 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C1880 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/nor_1/A 0.01fF
-C1881 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C1882 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C1883 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF
-C1884 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C1885 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C1886 ro_divider_buffered_0/tapered_buf_4/in4 ro_divider_buffered_0/tapered_buf_4/in5 29.21fF
-C1887 io_analog[9] gpio_noesd[12] 1.79fF
-C1888 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C1889 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.03fF
-C1890 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF
-C1891 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C1892 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C1893 gpio_noesd[9] gpio_noesd[8] 1.97fF
-C1894 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/tapered_buf_4/in1 0.19fF
-C1895 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1896 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF
-C1897 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C1898 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_0/B 0.15fF
-C1899 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in5 0.22fF
-C1900 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a4 0.12fF
-C1901 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C1902 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in2 0.84fF
-C1903 ashish_0/b io_analog[1] 4.11fF
-C1904 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C1905 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1906 gpio_noesd[14] gpio_analog[7] 2.55fF
-C1907 io_analog[6] ro_complete_buffered_0/ro_complete_0/a2 0.25fF
-C1908 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_1/Z4 0.02fF
-C1909 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C1910 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/UP 0.45fF
-C1911 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C1912 gpio_noesd[9] io_analog[10] 1.63fF
-C1913 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C1914 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/clk 0.11fF
-C1915 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF
-C1916 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C1917 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C1918 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
-C1919 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C1920 io_analog[3] ro_divider_buffered_0/tapered_buf_3/in1 0.19fF
-C1921 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 1.07fF
-C1922 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.16fF
-C1923 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C1924 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.01fF
-C1925 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF
-C1926 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF
-C1927 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.05fF
-C1928 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C1929 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
-C1930 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in3 1.27fF
-C1931 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C1932 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF
-C1933 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_0/Qbar 0.02fF
-C1934 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF
-C1935 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C1936 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C1937 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.06fF
-C1938 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/REF 0.02fF
-C1939 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in5 2.89fF
-C1940 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.01fF
-C1941 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z1 0.01fF
-C1942 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C1943 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF
-C1944 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C1945 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/div 0.51fF
-C1946 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in2 0.37fF
-C1947 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_0/in1 0.19fF
-C1948 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/R 0.27fF
-C1949 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/A 0.16fF
-C1950 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C1951 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF
-C1952 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
-C1953 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C1954 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
-C1955 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in5 0.22fF
-C1956 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.65fF
-C1957 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.13fF
-C1958 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.10fF
-C1959 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/a0 0.09fF
-C1960 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C1961 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C1962 io_analog[8] gpio_analog[6] 0.64fF
-C1963 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/DOWN 0.03fF
-C1964 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/UP 0.11fF
-C1965 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/pd_0/R 0.61fF
-C1966 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C1967 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C1968 ro_divider_buffered_0/tapered_buf_8/in4 ro_divider_buffered_0/tapered_buf_8/in5 29.21fF
-C1969 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in5 2.89fF
-C1970 io_analog[3] ro_divider_buffered_0/ro_complete_0/a4 0.19fF
-C1971 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C1972 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C1973 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF
-C1974 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
-C1975 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C1976 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF
-C1977 div_pd_buffered_0/divider_0/tspc_2/Z3 div_pd_buffered_0/divider_0/tspc_2/Z4 0.65fF
-C1978 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C1979 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/Z2 0.14fF
-C1980 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z4 0.20fF
-C1981 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z4 0.36fF
-C1982 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/Out 0.05fF
-C1983 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF
-C1984 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
-C1985 ro_complete_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/ro_complete_0/a4 26.29fF
-C1986 ro_complete_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/ro_complete_0/a3 26.29fF
-C1987 gpio_analog[3] gpio_analog[4] 1.29fF
-C1988 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF
-C1989 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C1990 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in5 2.89fF
-C1991 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C1992 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
-C1993 io_analog[7] ro_divider_buffered_0/ro_complete_0/a1 0.33fF
-C1994 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF
-C1995 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.05fF
-C1996 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1997 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C1998 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C1999 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C2000 pd_buffered_0/pd_0/tspc_r_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF
-C2001 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF
-C2002 io_analog[9] pll_full_buffered2_0/pll_full_0/div 0.68fF
-C2003 io_analog[8] ro_complete_buffered_0/tapered_buf_2/in1 0.19fF
-C2004 pd_buffered_0/tapered_buf_2/in1 pd_buffered_0/tapered_buf_2/in2 0.37fF
-C2005 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C2006 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF
-C2007 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
-C2008 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C2009 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C2010 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C2011 cp_buffered_0/cp_0/out cp_buffered_0/tapered_buf_1/in1 0.19fF
-C2012 io_analog[4] io_clamp_low[0] 0.53fF
-C2013 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/ro_complete_0/a0 26.29fF
-C2014 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C2015 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C2016 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF
-C2017 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF
-C2018 pll_full_buffered2_0/tapered_buf_3/in2 pll_full_buffered2_0/tapered_buf_3/in5 0.84fF
-C2019 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/B 0.01fF
-C2020 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C2021 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C2022 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C2023 filter_buffered_0/filter_0/a_4216_n2998# filter_buffered_0/filter_0/v 0.31fF
-C2024 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.78fF
-C2025 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
-C2026 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
-C2027 gpio_noesd[14] gpio_noesd[10] 2.89fF
-C2028 io_analog[7] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
-C2029 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF
-C2030 io_analog[4] gpio_analog[6] 0.64fF
-C2031 ro_divider_buffered_0/tapered_buf_4/in5 ro_divider_buffered_0/ro_complete_0/a4 26.29fF
-C2032 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in2 1.27fF
-C2033 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF
-C2034 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in5 0.84fF
-C2035 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in4 4.78fF
-C2036 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/divider_0/mc2 26.29fF
-C2037 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF
-C2038 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C2039 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
-C2040 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/B 0.01fF
-C2041 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/nor_1/B 0.03fF
-C2042 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C2043 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/Out 0.05fF
-C2044 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C2045 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C2046 gpio_analog[3] ashish_0/a 0.27fF
-C2047 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C2048 gpio_noesd[11] gpio_noesd[7] 0.79fF
-C2049 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in4 4.78fF
-C2050 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C2051 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF
-C2052 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF
-C2053 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF
-C2054 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C2055 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C2056 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.27fF
-C2057 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C2058 io_analog[5] ro_divider_buffered_0/ro_complete_0/a0 0.31fF
-C2059 gpio_noesd[8] gpio_noesd[13] 0.55fF
-C2060 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C2061 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C2062 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.38fF
-C2063 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.00fF
-C2064 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C2065 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C2066 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in2 0.37fF
-C2067 io_analog[3] ro_divider_buffered_0/ro_complete_0/a1 0.19fF
-C2068 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in5 0.84fF
-C2069 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.18fF
-C2070 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z4 0.12fF
-C2071 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
-C2072 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF
-C2073 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF
-C2074 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF
-C2075 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_0/Q 0.14fF
-C2076 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/clk 0.01fF
-C2077 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
-C2078 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in5 0.22fF
-C2079 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C2080 io_analog[10] gpio_noesd[13] 1.85fF
-C2081 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C2082 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C2083 gpio_noesd[14] io_analog[9] 3.54fF
-C2084 gpio_analog[4] divider_buffered_0/tapered_buf_2/in1 0.19fF
-C2085 io_analog[6] io_clamp_low[2] 0.53fF
-C2086 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C2087 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered2_0/pll_full_0/vco 1.58fF
-C2088 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in5 2.89fF
-C2089 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in2 0.37fF
-C2090 gpio_analog[5] ro_divider_buffered_0/tapered_buf_2/in1 0.19fF
-C2091 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in2 1.27fF
-C2092 pll_full_buffered2_0/tapered_buf_2/in5 gpio_noesd[8] 26.29fF
-C2093 ro_divider_buffered_0/tapered_buf_1/in3 ro_divider_buffered_0/tapered_buf_1/in2 1.27fF
-C2094 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/mc2 0.04fF
-C2095 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C2096 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in2 0.37fF
-C2097 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/nor_1/B 0.35fF
-C2098 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/R 0.29fF
-C2099 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C2100 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF
-C2101 io_clamp_low[2] io_clamp_high[2] 0.53fF
-C2102 io_analog[9] div_pd_buffered_0/tapered_buf_2/in1 0.19fF
-C2103 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in5 0.22fF
-C2104 ro_divider_buffered_0/tapered_buf_0/in1 ro_divider_buffered_0/tapered_buf_0/in2 0.37fF
-C2105 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C2106 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C2107 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF
-C2108 pd_buffered_0/tapered_buf_1/in3 pd_buffered_0/tapered_buf_1/in5 2.89fF
-C2109 pd_buffered_0/tapered_buf_2/in3 pd_buffered_0/tapered_buf_2/in2 1.27fF
-C2110 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C2111 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C2112 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in5 0.84fF
-C2113 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in4 4.78fF
-C2114 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C2115 gpio_noesd[14] gpio_analog[10] 2.60fF
-C2116 io_analog[3] ro_complete_buffered_0/ro_complete_0/a0 0.20fF
-C2117 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in2 0.37fF
-C2118 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in3 1.27fF
-C2119 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF
-C2120 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
-C2121 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z3 0.45fF
-C2122 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/div 0.02fF
-C2123 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in5 29.21fF
-C2124 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C2125 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C2126 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C2127 div_pd_buffered_0/tapered_buf_1/in2 div_pd_buffered_0/tapered_buf_1/in3 1.27fF
-C2128 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C2129 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/tapered_buf_1/in5 0.22fF
-C2130 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.65fF
-C2131 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF
-C2132 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF
-C2133 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.78fF
-C2134 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/divider_0/clk 1.30fF
-C2135 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/UP 0.45fF
-C2136 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C2137 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF
-C2138 pd_buffered_0/tapered_buf_2/in1 pd_buffered_0/pd_0/UP 0.19fF
-C2139 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF
-C2140 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF
-C2141 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C2142 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C2143 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
-C2144 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 4.79fF
-C2145 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C2146 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.09fF
-C2147 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF
-C2148 gpio_noesd[7] gpio_noesd[12] 0.68fF
-C2149 io_analog[5] ro_divider_buffered_0/ro_complete_0/a3 0.27fF
-C2150 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF
-C2151 gpio_noesd[14] gpio_analog[8] 2.77fF
-C2152 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/A 0.80fF
-C2153 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C2154 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF
-C2155 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF
-C2156 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C2157 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C2158 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C2159 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF
-C2160 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C2161 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/div 0.19fF
-C2162 io_analog[5] ro_complete_buffered_0/ro_complete_0/a2 0.25fF
-C2163 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/and_0/OUT 0.14fF
-C2164 pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.04fF
-C2165 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C2166 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.26fF
-C2167 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C2168 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C2169 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in5 0.22fF
-C2170 filter_buffered_0/filter_0/v filter_buffered_0/filter_0/a_4216_n5230# 0.19fF
-C2171 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z1 0.17fF
-C2172 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C2173 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C2174 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF
-C2175 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in3 2.89fF
-C2176 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C2177 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/A 0.16fF
-C2178 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C2179 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/clk 0.11fF
-C2180 pll_full_buffered2_0/pll_full_0/div pll_full_buffered2_0/pll_full_0/vco 2.26fF
-C2181 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/B 0.20fF
-C2182 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in3 1.27fF
-C2183 divider_buffered_0/divider_0/and_0/B divider_buffered_0/divider_0/and_0/Z1 0.07fF
-C2184 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C2185 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in2 0.37fF
-C2186 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.22fF
-C2187 cp_buffered_0/tapered_buf_2/in2 cp_buffered_0/tapered_buf_2/in1 0.37fF
-C2188 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C2189 gpio_analog[7] io_analog[9] 1.40fF
-Xpll_full_buffered1_0 vssa1 vssa1 pll_full_buffered1
+C0 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/nor_0/B 0.47fF
+C1 gpio_noesd[10] io_analog[9] 3.45fF
+C2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.36fF
+C3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 4.79fF
+C4 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C5 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C6 pd_buffered_0/tapered_buf_1/in3 pd_buffered_0/tapered_buf_1/in5 2.89fF
+C7 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.18fF
+C8 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C9 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z2 0.16fF
+C10 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C11 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
+C12 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C13 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C14 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C15 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/nor_0/B 0.47fF
+C16 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z3 0.05fF
+C17 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
+C18 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C19 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/B 0.18fF
+C20 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in2 0.84fF
+C21 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered1_0/pll_full_0/vco 1.36fF
+C22 gpio_noesd[10] gpio_analog[10] 1.36fF
+C23 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C24 ro_divider_buffered_0/tapered_buf_0/in1 ro_divider_buffered_0/divider_0/Out 0.19fF
+C25 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/out1 0.31fF
+C26 ro_divider_buffered_0/divider_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/tspc_0/Q 0.15fF
+C27 divider_buffered_0/tapered_buf_1/in4 divider_buffered_0/tapered_buf_1/in3 4.78fF
+C28 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/tapered_buf_3/in 5.03fF
+C29 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C30 gpio_analog[8] gpio_noesd[7] 1.68fF
+C31 io_analog[3] ro_divider_buffered_0/tapered_buf_3/in1 0.19fF
+C32 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
+C33 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C34 pd_buffered_0/pd_0/DOWN gpio_noesd[10] 0.54fF
+C35 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C36 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered2_0/pll_full_0/vco 1.36fF
+C37 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/out1 0.31fF
+C38 div_pd_buffered_0/divider_0/tspc_1/Z4 div_pd_buffered_0/divider_0/tspc_0/Q 0.15fF
+C39 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/REF 0.02fF
+C40 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF
+C41 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C42 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C43 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in2 0.84fF
+C44 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_1/B 0.35fF
+C45 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
+C46 pd_buffered_0/tapered_buf_1/in4 pd_buffered_0/tapered_buf_1/in5 29.21fF
+C47 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF
+C48 pll_full_buffered2_0/tapered_buf_5/in pll_full_buffered2_0/tapered_buf_5/in1 0.19fF
+C49 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/and_0/B 0.29fF
+C50 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C51 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C52 gpio_noesd[7] gpio_noesd[13] 0.80fF
+C53 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.04fF
+C54 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C55 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in3 1.27fF
+C56 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/R 0.36fF
+C57 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF
+C58 div_pd_buffered_0/pd_0/tspc_r_1/Z1 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF
+C59 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
+C60 ro_divider_buffered_0/tapered_buf_5/in5 ro_divider_buffered_0/ro_complete_0/a3 26.29fF
+C61 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z4 0.36fF
+C62 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Q 0.05fF
+C63 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.35fF
+C64 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z2 0.01fF
+C65 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/and_0/B 0.78fF
+C66 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/nor_1/B 0.01fF
+C67 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF
+C68 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C69 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C70 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.06fF
+C71 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF
+C72 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C73 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C74 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/and_0/B 0.29fF
+C75 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C76 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF
+C77 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
+C78 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in5 2.89fF
+C79 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/nor_1/B 0.20fF
+C80 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF
+C81 pll_full_buffered1_0/tapered_buf_0/in pll_full_buffered1_0/tapered_buf_0/in1 0.19fF
+C82 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in4 4.78fF
+C83 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/clk 0.11fF
+C84 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF
+C85 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in2 0.84fF
+C86 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C87 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C88 pd_buffered_0/tapered_buf_3/in3 pd_buffered_0/tapered_buf_3/in2 1.27fF
+C89 io_analog[7] ro_divider_buffered_0/ro_complete_0/a0 0.33fF
+C90 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.01fF
+C91 io_analog[5] io_clamp_high[1] 0.53fF
+C92 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF
+C93 divider_buffered_0/divider_0/tspc_0/Z4 divider_buffered_0/divider_0/tspc_0/Z2 0.36fF
+C94 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C95 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C96 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF
+C97 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
+C98 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C99 pd_buffered_0/pd_0/tspc_r_0/Z1 pd_buffered_0/pd_0/REF 0.17fF
+C100 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C101 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/div 0.12fF
+C102 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF
+C103 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C104 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z2 0.14fF
+C105 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z3 0.05fF
+C106 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
+C107 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
+C108 ashish_0/b gpio_analog[3] 0.27fF
+C109 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/UP 0.21fF
+C110 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in5 2.89fF
+C111 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C112 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF
+C113 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.05fF
+C114 ro_divider_buffered_0/tapered_buf_2/in1 gpio_analog[5] 0.19fF
+C115 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/REF 0.19fF
+C116 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C117 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C118 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C119 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF
+C120 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C121 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
+C122 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z2 0.14fF
+C123 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
+C124 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
+C125 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/clk 0.26fF
+C126 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C127 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in1 0.22fF
+C128 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF
+C129 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C130 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF
+C131 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/REF 0.61fF
+C132 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered1_0/pll_full_0/vco 1.58fF
+C133 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 0.03fF
+C134 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C135 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF
+C136 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C137 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C138 gpio_noesd[8] pll_full_buffered2_0/tapered_buf_3/in 0.23fF
+C139 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in5 0.22fF
+C140 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/Out 0.04fF
+C141 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.06fF
+C142 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/Out 0.42fF
+C143 ro_complete_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/in1 0.22fF
+C144 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
+C145 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z4 0.00fF
+C146 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF
+C147 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in4 4.78fF
+C148 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C149 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Z2 0.16fF
+C150 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered2_0/pll_full_0/vco 1.58fF
+C151 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF
+C152 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C153 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in3 1.27fF
+C154 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in1 0.37fF
+C155 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/nor_1/B 0.38fF
+C156 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C157 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C158 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C159 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C160 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF
+C161 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z3 0.06fF
+C162 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C163 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C164 io_analog[10] pll_full_buffered2_0/tapered_buf_3/in 0.42fF
+C165 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Q 0.51fF
+C166 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z2 0.01fF
+C167 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C168 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C169 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF
+C170 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z2 1.07fF
+C171 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z3 0.38fF
+C172 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z4 0.12fF
+C173 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF
+C174 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/div 0.27fF
+C175 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in 0.19fF
+C176 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in3 1.27fF
+C177 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.32fF
+C178 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF
+C179 io_analog[4] io_analog[6] 1.25fF
+C180 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.19fF
+C181 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF
+C182 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.33fF
+C183 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C184 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/nor_1/B 1.21fF
+C185 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in4 4.78fF
+C186 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Q 0.51fF
+C187 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C188 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C189 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/clk 0.51fF
+C190 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C191 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C192 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C193 pd_buffered_0/tapered_buf_1/in1 pd_buffered_0/tapered_buf_1/in5 0.22fF
+C194 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/Z3 0.38fF
+C195 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C196 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C197 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF
+C198 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.20fF
+C199 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/out1 0.06fF
+C200 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C201 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/B 0.31fF
+C202 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/Z1 0.36fF
+C203 io_analog[6] ro_complete_buffered_0/tapered_buf_4/in1 0.19fF
+C204 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z3 0.06fF
+C205 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.11fF
+C206 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.33fF
+C207 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF
+C208 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C209 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C210 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in5 0.22fF
+C211 div_pd_buffered_0/pd_0/and_pd_0/Z1 div_pd_buffered_0/pd_0/UP 0.06fF
+C212 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C213 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.20fF
+C214 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C215 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/nor_1/B 1.21fF
+C216 pd_buffered_0/tapered_buf_2/in3 pd_buffered_0/tapered_buf_2/in2 1.27fF
+C217 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C218 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C219 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in4 4.78fF
+C220 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in5 0.84fF
+C221 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C222 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C223 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF
+C224 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in5 0.84fF
+C225 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/pd_0/REF 26.29fF
+C226 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/R 0.03fF
+C227 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z4 0.12fF
+C228 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C229 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.01fF
+C230 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF
+C231 io_analog[5] ro_divider_buffered_0/ro_complete_0/a2 0.35fF
+C232 io_analog[10] div_pd_buffered_0/tapered_buf_1/in1 0.19fF
+C233 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C234 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C235 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF
+C236 pd_buffered_0/pd_0/DIV pd_buffered_0/tapered_buf_1/in5 26.29fF
+C237 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/and_0/OUT 0.14fF
+C238 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/clk 0.51fF
+C239 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/tspc_r_0/Z3 0.11fF
+C240 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF
+C241 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C242 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C243 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.06fF
+C244 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 0.22fF
+C245 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.01fF
+C246 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_0/in1 0.19fF
+C247 gpio_analog[4] gpio_noesd[4] 0.91fF
+C248 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
+C249 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C250 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C251 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.01fF
+C252 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF
+C253 io_analog[3] io_analog[6] 1.03fF
+C254 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in4 4.78fF
+C255 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in5 0.84fF
+C256 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF
+C257 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/UP 0.03fF
+C258 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C259 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C260 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.13fF
+C261 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C262 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.01fF
+C263 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C264 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/B 0.08fF
+C265 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C266 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF
+C267 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
+C268 cp_buffered_0/tapered_buf_2/in1 cp_buffered_0/tapered_buf_2/in5 0.22fF
+C269 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C270 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C271 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in2 0.37fF
+C272 gpio_noesd[10] gpio_noesd[7] 0.73fF
+C273 pll_full_buffered2_0/tapered_buf_0/in4 pll_full_buffered2_0/tapered_buf_0/in5 29.21fF
+C274 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C275 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in5 2.89fF
+C276 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF
+C277 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z3 0.05fF
+C278 pll_full_buffered2_0/tapered_buf_5/in5 gpio_noesd[7] 26.29fF
+C279 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF
+C280 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF
+C281 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Q 0.04fF
+C282 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.13fF
+C283 pd_buffered_0/pd_0/tspc_r_1/z5 pd_buffered_0/pd_0/tspc_r_1/Z3 0.11fF
+C284 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/clk 0.04fF
+C285 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C286 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C287 div_pd_buffered_0/tapered_buf_0/in5 gpio_noesd[12] 26.29fF
+C288 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C289 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF
+C290 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF
+C291 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
+C292 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z2 1.07fF
+C293 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/vco 0.01fF
+C294 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.21fF
+C295 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/B 0.31fF
+C296 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C297 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
+C298 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF
+C299 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in3 2.89fF
+C300 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a3 2.04fF
+C301 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF
+C302 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z4 0.12fF
+C303 io_analog[7] ro_divider_buffered_0/tapered_buf_7/in1 0.19fF
+C304 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF
+C305 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in2 0.84fF
+C306 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C307 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.18fF
+C308 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF
+C309 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
+C310 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/div 0.19fF
+C311 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_1/B 0.06fF
+C312 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.14fF
+C313 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C314 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
+C315 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C316 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/a3 0.09fF
+C317 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/B 0.31fF
+C318 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C319 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
+C320 pd_buffered_0/tapered_buf_2/in4 pd_buffered_0/tapered_buf_2/in5 29.21fF
+C321 io_analog[1] ashish_0/a 8.93fF
+C322 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C323 io_analog[10] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.36fF
+C324 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF
+C325 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.00fF
+C326 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in5 2.89fF
+C327 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF
+C328 cp_buffered_0/cp_0/out cp_buffered_0/tapered_buf_1/in1 0.19fF
+C329 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/a0 3.46fF
+C330 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C331 io_analog[8] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
+C332 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.12fF
+C333 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z4 0.21fF
+C334 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in4 4.78fF
+C335 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in5 0.84fF
+C336 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF
+C337 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.01fF
+C338 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C339 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C340 divider_buffered_0/tapered_buf_0/in2 divider_buffered_0/tapered_buf_0/in3 1.27fF
+C341 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C342 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C343 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C344 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C345 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/div 0.01fF
+C346 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF
+C347 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C348 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z4 0.00fF
+C349 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.78fF
+C350 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
+C351 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z3 0.16fF
+C352 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z4 0.22fF
+C353 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C354 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C355 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
+C356 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF
+C357 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z3 0.45fF
+C358 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF
+C359 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in4 4.78fF
+C360 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in5 0.84fF
+C361 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C362 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C363 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C364 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C365 io_analog[6] ro_divider_buffered_0/ro_complete_0/a0 0.21fF
+C366 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/clk 0.04fF
+C367 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C368 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C369 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/A 0.01fF
+C370 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.78fF
+C371 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
+C372 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C373 gpio_noesd[14] gpio_noesd[12] 2.57fF
+C374 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C375 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C376 divider_buffered_0/divider_0/and_0/A divider_buffered_0/divider_0/and_0/B 0.18fF
+C377 ro_divider_buffered_0/ro_complete_0/cbank_2/v ro_divider_buffered_0/divider_0/clk 1.36fF
+C378 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C379 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z3 0.38fF
+C380 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in2 0.37fF
+C381 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in5 2.89fF
+C382 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in5 0.22fF
+C383 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/R 0.51fF
+C384 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
+C385 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in3 2.89fF
+C386 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Q 0.55fF
+C387 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.06fF
+C388 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C389 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C390 gpio_noesd[11] gpio_noesd[10] 6.19fF
+C391 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
+C392 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
+C393 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C394 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
+C395 divider_buffered_0/tapered_buf_0/in3 divider_buffered_0/tapered_buf_0/in4 4.78fF
+C396 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.35fF
+C397 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C398 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C399 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_0/B 0.06fF
+C400 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C401 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/tapered_buf_3/in 0.32fF
+C402 pll_full_buffered2_0/tapered_buf_4/in4 pll_full_buffered2_0/tapered_buf_4/in5 29.21fF
+C403 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in2 0.37fF
+C404 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/R 0.30fF
+C405 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
+C406 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF
+C407 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C408 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_1/B 0.51fF
+C409 io_analog[10] gpio_noesd[8] 3.39fF
+C410 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C411 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C412 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C413 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/ro_complete_0/a1 26.29fF
+C414 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C415 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C416 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF
+C417 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_divider_buffered_0/divider_0/clk 1.30fF
+C418 filter_buffered_0/filter_0/a_4216_n2998# filter_buffered_0/filter_0/v 0.31fF
+C419 gpio_noesd[10] pd_buffered_0/tapered_buf_2/in5 26.29fF
+C420 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C421 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C422 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 29.21fF
+C423 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/out 0.61fF
+C424 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in3 1.27fF
+C425 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/nor_1/A 0.01fF
+C426 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C427 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
+C428 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF
+C429 io_analog[4] io_analog[5] 20.14fF
+C430 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C431 ro_divider_buffered_0/tapered_buf_4/in4 ro_divider_buffered_0/tapered_buf_4/in5 29.21fF
+C432 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in2 0.37fF
+C433 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/UP 0.45fF
+C434 io_analog[9] gpio_noesd[12] 1.79fF
+C435 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C436 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.03fF
+C437 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF
+C438 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C439 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C440 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/tapered_buf_4/in1 0.19fF
+C441 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C442 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C443 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C444 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_0/B 0.15fF
+C445 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF
+C446 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF
+C447 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C448 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C449 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
+C450 pll_full_buffered1_0/tapered_buf_0/in2 pll_full_buffered1_0/tapered_buf_0/in3 1.27fF
+C451 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in5 0.22fF
+C452 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a4 0.12fF
+C453 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C454 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in5 0.84fF
+C455 io_analog[6] ro_complete_buffered_0/ro_complete_0/a2 0.25fF
+C456 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_1/Z4 0.02fF
+C457 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C458 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/UP 0.45fF
+C459 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF
+C460 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C461 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C462 pd_buffered_0/pd_0/tspc_r_1/z5 pd_buffered_0/pd_0/DOWN 0.03fF
+C463 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C464 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/clk 0.11fF
+C465 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF
+C466 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C467 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C468 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
+C469 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 1.07fF
+C470 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.16fF
+C471 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C472 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C473 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF
+C474 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C475 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/div 0.19fF
+C476 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF
+C477 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.05fF
+C478 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C479 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
+C480 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
+C481 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.26fF
+C482 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in3 1.27fF
+C483 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C484 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF
+C485 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/REF 0.02fF
+C486 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in5 2.89fF
+C487 io_analog[4] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
+C488 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z1 0.01fF
+C489 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C490 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF
+C491 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C492 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/div 0.51fF
+C493 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in2 0.37fF
+C494 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C495 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF
+C496 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
+C497 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C498 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
+C499 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/A 0.16fF
+C500 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C501 filter_buffered_0/filter_0/a_4216_n5230# filter_buffered_0/filter_0/v 0.19fF
+C502 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C503 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in5 0.22fF
+C504 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.65fF
+C505 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/div 0.01fF
+C506 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in2 0.37fF
+C507 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.10fF
+C508 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/a0 0.09fF
+C509 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/tspc_r_1/Z3 0.25fF
+C510 io_analog[3] io_analog[5] 0.93fF
+C511 io_analog[8] gpio_analog[6] 0.64fF
+C512 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C513 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/DOWN 0.03fF
+C514 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/UP 0.11fF
+C515 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/pd_0/R 0.61fF
+C516 pd_buffered_0/tapered_buf_0/in5 gpio_noesd[11] 26.29fF
+C517 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF
+C518 gpio_noesd[14] gpio_noesd[9] 2.58fF
+C519 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C520 ro_divider_buffered_0/tapered_buf_8/in4 ro_divider_buffered_0/tapered_buf_8/in5 29.21fF
+C521 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C522 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C523 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF
+C524 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C525 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C526 div_pd_buffered_0/divider_0/tspc_2/Z3 div_pd_buffered_0/divider_0/tspc_2/Z4 0.65fF
+C527 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C528 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF
+C529 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.38fF
+C530 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z4 0.36fF
+C531 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/Out 0.05fF
+C532 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF
+C533 ro_complete_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/ro_complete_0/a4 26.29fF
+C534 ro_complete_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/ro_complete_0/a3 26.29fF
+C535 filter_buffered_0/tapered_buf_1/in1 gpio_analog[17] 0.19fF
+C536 cp_buffered_0/tapered_buf_0/in4 cp_buffered_0/tapered_buf_0/in5 29.21fF
+C537 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF
+C538 gpio_analog[9] gpio_noesd[8] 1.10fF
+C539 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in5 2.89fF
+C540 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C541 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
+C542 io_analog[7] ro_divider_buffered_0/ro_complete_0/a1 0.33fF
+C543 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF
+C544 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.05fF
+C545 io_analog[4] io_clamp_high[0] 0.53fF
+C546 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C547 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C548 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C549 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C550 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C551 io_analog[9] pll_full_buffered2_0/pll_full_0/div 0.68fF
+C552 io_analog[8] ro_complete_buffered_0/tapered_buf_2/in1 0.19fF
+C553 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF
+C554 gpio_analog[9] io_analog[10] 1.15fF
+C555 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in3 1.27fF
+C556 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
+C557 io_analog[3] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
+C558 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C559 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
+C560 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/pll_full_0/vco 0.19fF
+C561 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C562 cp_buffered_0/tapered_buf_2/in2 cp_buffered_0/tapered_buf_2/in1 0.37fF
+C563 gpio_analog[3] io_analog[0] 3.87fF
+C564 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF
+C565 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/ro_complete_0/a0 26.29fF
+C566 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C567 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C568 pll_full_buffered2_0/tapered_buf_3/in2 pll_full_buffered2_0/tapered_buf_3/in5 0.84fF
+C569 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/B 0.01fF
+C570 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
+C571 gpio_noesd[9] io_analog[9] 1.19fF
+C572 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in3 1.27fF
+C573 io_analog[7] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
+C574 ro_divider_buffered_0/tapered_buf_4/in5 ro_divider_buffered_0/ro_complete_0/a4 26.29fF
+C575 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF
+C576 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF
+C577 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF
+C578 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in2 1.27fF
+C579 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF
+C580 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C581 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C582 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
+C583 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/divider_0/mc2 26.29fF
+C584 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF
+C585 gpio_analog[3] gpio_analog[4] 1.29fF
+C586 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/B 0.01fF
+C587 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.06fF
+C588 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C589 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C590 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/nor_1/B 0.03fF
+C591 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C592 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/Out 0.05fF
+C593 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C594 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C595 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in4 4.78fF
+C596 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C597 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF
+C598 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF
+C599 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF
+C600 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in3 1.27fF
+C601 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C602 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.27fF
+C603 gpio_analog[8] io_analog[10] 1.48fF
+C604 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C605 pd_buffered_0/tapered_buf_1/in2 pd_buffered_0/tapered_buf_1/in5 0.84fF
+C606 io_analog[5] ro_divider_buffered_0/ro_complete_0/a0 0.31fF
+C607 gpio_noesd[8] gpio_noesd[13] 0.55fF
+C608 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C609 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.38fF
+C610 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.00fF
+C611 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C612 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C613 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C614 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C615 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF
+C616 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF
+C617 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in5 0.84fF
+C618 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.18fF
+C619 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z4 0.12fF
+C620 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
+C621 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C622 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered1_0/pll_full_0/vco 1.58fF
+C623 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_0/Q 0.14fF
+C624 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/clk 0.01fF
+C625 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in4 4.78fF
+C626 pll_full_buffered1_0/tapered_buf_0/in2 pll_full_buffered1_0/tapered_buf_0/in5 0.84fF
+C627 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/UP 0.06fF
+C628 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF
+C629 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C630 pll_full_buffered1_0/tapered_buf_1/in4 pll_full_buffered1_0/tapered_buf_1/in5 29.21fF
+C631 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF
+C632 io_analog[10] gpio_noesd[13] 1.85fF
+C633 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C634 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C635 gpio_analog[4] divider_buffered_0/tapered_buf_2/in1 0.19fF
+C636 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C637 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered2_0/pll_full_0/vco 1.58fF
+C638 io_analog[6] io_clamp_low[2] 0.53fF
+C639 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/UP 0.11fF
+C640 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/div 0.51fF
+C641 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in2 0.37fF
+C642 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/nor_1/B 0.35fF
+C643 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in2 1.27fF
+C644 pll_full_buffered2_0/tapered_buf_2/in5 gpio_noesd[8] 26.29fF
+C645 ro_divider_buffered_0/tapered_buf_1/in3 ro_divider_buffered_0/tapered_buf_1/in2 1.27fF
+C646 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/mc2 0.04fF
+C647 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C648 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF
+C649 io_clamp_low[2] io_clamp_high[2] 0.53fF
+C650 io_analog[9] div_pd_buffered_0/tapered_buf_2/in1 0.19fF
+C651 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in5 0.22fF
+C652 ro_divider_buffered_0/tapered_buf_0/in1 ro_divider_buffered_0/tapered_buf_0/in2 0.37fF
+C653 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
+C654 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF
+C655 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in4 4.78fF
+C656 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in5 0.84fF
+C657 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C658 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in2 0.37fF
+C659 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in3 1.27fF
+C660 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF
+C661 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z3 0.45fF
+C662 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/div 0.02fF
+C663 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in5 29.21fF
+C664 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C665 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C666 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C667 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/tapered_buf_1/in5 0.22fF
+C668 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.65fF
+C669 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF
+C670 div_pd_buffered_0/tapered_buf_1/in2 div_pd_buffered_0/tapered_buf_1/in3 1.27fF
+C671 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
+C672 pd_buffered_0/tapered_buf_2/in3 pd_buffered_0/tapered_buf_2/in5 2.89fF
+C673 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
+C674 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF
+C675 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF
+C676 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.78fF
+C677 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/divider_0/clk 1.30fF
+C678 gpio_analog[7] io_analog[10] 2.78fF
+C679 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF
+C680 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in3 1.27fF
+C681 cp_buffered_0/cp_0/upbar cp_buffered_0/cp_0/down 0.02fF
+C682 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C683 pd_buffered_0/pd_0/tspc_r_1/Qbar pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.01fF
+C684 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.09fF
+C685 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF
+C686 io_analog[5] ro_divider_buffered_0/ro_complete_0/a3 0.27fF
+C687 gpio_noesd[7] gpio_noesd[12] 0.68fF
+C688 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/A 0.80fF
+C689 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF
+C690 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C691 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C692 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C693 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/a_1710_0# 0.83fF
+C694 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/UP 0.03fF
+C695 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C696 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF
+C697 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.16fF
+C698 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C699 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C700 io_analog[5] ro_complete_buffered_0/ro_complete_0/a2 0.25fF
+C701 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/and_0/OUT 0.14fF
+C702 pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.04fF
+C703 cp_buffered_0/tapered_buf_0/in5 cp_buffered_0/cp_0/down 26.29fF
+C704 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C705 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C706 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in5 0.22fF
+C707 cp_buffered_0/tapered_buf_2/in4 cp_buffered_0/tapered_buf_2/in5 29.21fF
+C708 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C709 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in3 2.89fF
+C710 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C711 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/A 0.16fF
+C712 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C713 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C714 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF
+C715 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/clk 0.11fF
+C716 pll_full_buffered2_0/pll_full_0/div pll_full_buffered2_0/pll_full_0/vco 2.26fF
+C717 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
+C718 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in3 1.27fF
+C719 divider_buffered_0/divider_0/and_0/B divider_buffered_0/divider_0/and_0/Z1 0.07fF
+C720 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/B 0.20fF
+C721 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.22fF
+C722 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in4 4.78fF
+C723 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in5 0.84fF
+C724 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/REF 0.65fF
+C725 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a2 1.38fF
+C726 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in3 2.89fF
+C727 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in3 2.89fF
+C728 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/divider_0/clk 26.29fF
+C729 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a3 3.17fF
+C730 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C731 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Q 0.55fF
+C732 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.55fF
+C733 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
+C734 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.03fF
+C735 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF
+C736 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C737 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C738 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/clk 0.01fF
+C739 ro_complete_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/ro_complete_0/a2 26.29fF
+C740 io_analog[7] gpio_analog[6] 0.64fF
+C741 io_analog[3] io_analog[4] 0.88fF
+C742 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in4 4.78fF
+C743 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in5 0.84fF
+C744 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF
+C745 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_1/B 0.18fF
+C746 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/A 0.15fF
+C747 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C748 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_3/in3 1.27fF
+C749 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF
+C750 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.22fF
+C751 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in1 0.22fF
+C752 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF
+C753 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C754 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C755 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/divider_0/clk 1.30fF
+C756 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/Z2 0.14fF
+C757 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C758 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.80fF
+C759 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C760 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.35fF
+C761 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/clk 0.60fF
+C762 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/A 0.01fF
+C763 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.05fF
+C764 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in3 2.89fF
+C765 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in5 0.84fF
+C766 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/DIV 0.17fF
+C767 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF
+C768 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
+C769 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in3 1.27fF
+C770 io_analog[6] ro_divider_buffered_0/ro_complete_0/a1 0.20fF
+C771 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in1 0.22fF
+C772 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C773 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.80fF
+C774 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C775 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
+C776 pll_full_buffered2_0/tapered_buf_1/in4 pll_full_buffered2_0/tapered_buf_1/in5 29.21fF
+C777 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C778 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.08fF
+C779 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C780 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/A 0.01fF
+C781 div_pd_buffered_0/divider_0/tspc_0/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.05fF
+C782 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z1 0.01fF
+C783 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF
+C784 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF
+C785 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF
+C786 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.05fF
+C787 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/Out 1.14fF
+C788 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
+C789 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C790 pll_full_buffered1_0/tapered_buf_0/in4 pll_full_buffered1_0/tapered_buf_0/in5 29.21fF
+C791 pll_full_buffered2_0/tapered_buf_2/in4 pll_full_buffered2_0/tapered_buf_2/in5 29.21fF
+C792 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
+C793 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C794 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a4 0.09fF
+C795 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a5 0.09fF
+C796 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Q 0.05fF
+C797 gpio_noesd[10] gpio_noesd[8] 0.51fF
+C798 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF
+C799 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/and_0/OUT 0.03fF
+C800 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF
+C801 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF
+C802 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
+C803 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
+C804 io_analog[6] ro_divider_buffered_0/tapered_buf_6/in1 0.19fF
+C805 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/DOWN 0.03fF
+C806 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C807 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF
+C808 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C809 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C810 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF
+C811 pd_buffered_0/pd_0/tspc_r_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF
+C812 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C813 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/div 0.02fF
+C814 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C815 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/nor_1/B 0.06fF
+C816 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.36fF
+C817 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/pd_0/REF 26.29fF
+C818 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF
+C819 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C820 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in5 2.89fF
+C821 gpio_noesd[10] io_analog[10] 1.21fF
+C822 ro_complete_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/in5 29.21fF
+C823 ro_complete_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_1/in5 0.22fF
+C824 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF
+C825 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF
+C826 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
+C827 gpio_noesd[9] gpio_noesd[7] 3.28fF
+C828 pll_full_buffered1_0/pll_full_0/vco io_analog[10] 0.56fF
+C829 io_analog[6] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
+C830 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/DOWN 0.02fF
+C831 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/R 0.30fF
+C832 divider_buffered_0/tapered_buf_1/in2 divider_buffered_0/tapered_buf_1/in3 1.27fF
+C833 pd_buffered_0/tapered_buf_3/in3 pd_buffered_0/tapered_buf_3/in5 2.89fF
+C834 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
+C835 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.11fF
+C836 io_analog[9] io_analog[8] 1.33fF
+C837 io_analog[10] div_pd_buffered_0/divider_0/mc2 0.64fF
+C838 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z4 0.15fF
+C839 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C840 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in4 4.78fF
+C841 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in5 0.84fF
+C842 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z2 1.07fF
+C843 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C844 gpio_noesd[14] io_analog[9] 3.54fF
+C845 gpio_analog[5] ro_divider_buffered_0/divider_0/Out 0.75fF
+C846 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/tspc_0/Q 0.01fF
+C847 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF
+C848 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C849 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in4 29.21fF
+C850 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_0/Z2 0.21fF
+C851 pd_buffered_0/tapered_buf_3/in1 pd_buffered_0/tapered_buf_3/in2 0.37fF
+C852 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.36fF
+C853 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Q 0.05fF
+C854 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/vco 0.06fF
+C855 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in2 0.37fF
+C856 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_1/in5 26.29fF
+C857 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in4 4.78fF
+C858 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in5 0.84fF
+C859 io_analog[3] ro_complete_buffered_0/tapered_buf_1/in1 0.19fF
+C860 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
+C861 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/tapered_buf_3/in 0.11fF
+C862 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/R 0.51fF
+C863 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C864 gpio_noesd[14] gpio_analog[10] 2.60fF
+C865 io_analog[4] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
+C866 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/Z1 0.00fF
+C867 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.06fF
+C868 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/in1 0.22fF
+C869 div_pd_buffered_0/tapered_buf_1/in1 div_pd_buffered_0/tapered_buf_1/in2 0.37fF
+C870 cp_buffered_0/cp_0/a_10_n50# cp_buffered_0/cp_0/a_1710_0# 0.04fF
+C871 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C872 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C873 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/div 0.03fF
+C874 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/vco 0.06fF
+C875 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C876 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/vco 0.64fF
+C877 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.02fF
+C878 pll_full_buffered1_0/pll_full_0/div pll_full_buffered1_0/pll_full_0/vco 2.26fF
+C879 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/divider_0/mc2 26.29fF
+C880 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C881 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C882 gpio_analog[3] io_analog[1] 1.96fF
+C883 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in5 2.89fF
+C884 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C885 gpio_analog[3] ashish_0/a 0.27fF
+C886 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
+C887 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/vco 0.64fF
+C888 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/clk 0.14fF
+C889 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF
+C890 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C891 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C892 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.04fF
+C893 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF
+C894 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF
+C895 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF
+C896 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF
+C897 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.01fF
+C898 pd_buffered_0/pd_0/DIV io_analog[10] 0.52fF
+C899 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a5 2.39fF
+C900 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C901 filter_buffered_0/tapered_buf_0/in4 filter_buffered_0/tapered_buf_0/in5 29.21fF
+C902 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.29fF
+C903 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/nor_1/A 0.03fF
+C904 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C905 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.12fF
+C906 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C907 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C908 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/div 0.65fF
+C909 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C910 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF
+C911 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF
+C912 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF
+C913 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/A 0.01fF
+C914 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF
+C915 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF
+C916 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in3 1.27fF
+C917 pll_full_buffered2_0/tapered_buf_3/in4 pll_full_buffered2_0/tapered_buf_3/in5 29.21fF
+C918 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/nor_1/B 0.38fF
+C919 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z1 0.00fF
+C920 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C921 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/divider_0/clk 0.05fF
+C922 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z1 0.03fF
+C923 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z3 0.05fF
+C924 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in2 0.37fF
+C925 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.29fF
+C926 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in1 0.37fF
+C927 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/R 0.21fF
+C928 ro_divider_buffered_0/tapered_buf_3/in4 ro_divider_buffered_0/tapered_buf_3/in5 29.21fF
+C929 io_analog[9] gpio_analog[10] 3.28fF
+C930 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in3 2.89fF
+C931 io_analog[4] ro_divider_buffered_0/ro_complete_0/a3 0.23fF
+C932 io_analog[3] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
+C933 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in1 0.37fF
+C934 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/nor_1/A 0.01fF
+C935 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF
+C936 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C937 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_1/Z2 0.15fF
+C938 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF
+C939 io_analog[9] ro_divider_buffered_0/tapered_buf_1/in1 0.19fF
+C940 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C941 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.03fF
+C942 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C943 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF
+C944 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.04fF
+C945 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.26fF
+C946 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z1 0.03fF
+C947 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF
+C948 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C949 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z2 0.01fF
+C950 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/clk 0.05fF
+C951 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF
+C952 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C953 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_divider_buffered_0/divider_0/clk 1.43fF
+C954 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF
+C955 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF
+C956 io_analog[4] ro_complete_buffered_0/ro_complete_0/a2 0.37fF
+C957 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in1 0.22fF
+C958 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in4 4.78fF
+C959 div_pd_buffered_0/pd_0/tspc_r_1/Z4 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
+C960 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in4 29.21fF
+C961 divider_buffered_0/tapered_buf_1/in4 divider_buffered_0/tapered_buf_1/in5 29.21fF
+C962 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C963 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_1/Z4 0.02fF
+C964 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z3 0.06fF
+C965 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF
+C966 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C967 pd_buffered_0/tapered_buf_1/in1 gpio_analog[9] 0.19fF
+C968 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF
+C969 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF
+C970 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.05fF
+C971 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C972 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C973 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/B 0.18fF
+C974 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.65fF
+C975 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF
+C976 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
+C977 divider_buffered_0/divider_0/prescaler_0/nand_0/z1 divider_buffered_0/divider_0/and_0/OUT 0.01fF
+C978 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.09fF
+C979 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.36fF
+C980 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF
+C981 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in2 0.37fF
+C982 pd_buffered_0/tapered_buf_1/in3 pd_buffered_0/tapered_buf_1/in4 4.78fF
+C983 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in5 2.89fF
+C984 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C985 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/UP 0.33fF
+C986 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z1 0.06fF
+C987 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C988 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.45fF
+C989 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF
+C990 ro_complete_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_2/in1 0.37fF
+C991 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/Z1 0.04fF
+C992 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF
+C993 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C994 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C995 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.45fF
+C996 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/A 0.80fF
+C997 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
+C998 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF
+C999 io_clamp_low[1] io_clamp_high[1] 0.53fF
+C1000 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF
+C1001 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C1002 io_analog[6] gpio_analog[6] 0.64fF
+C1003 io_analog[7] ro_complete_buffered_0/ro_complete_0/a1 0.23fF
+C1004 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.32fF
+C1005 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF
+C1006 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF
+C1007 io_analog[7] io_analog[8] 1.38fF
+C1008 io_analog[3] ro_divider_buffered_0/ro_complete_0/a3 0.23fF
+C1009 ro_divider_buffered_0/tapered_buf_7/in4 ro_divider_buffered_0/tapered_buf_7/in5 29.21fF
+C1010 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in5 0.84fF
+C1011 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF
+C1012 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z3 0.16fF
+C1013 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z2 1.07fF
+C1014 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C1015 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in4 29.21fF
+C1016 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF
+C1017 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C1018 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1019 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF
+C1020 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C1021 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z2 0.36fF
+C1022 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.05fF
+C1023 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C1024 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 0.38fF
+C1025 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/div 0.03fF
+C1026 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 0.31fF
+C1027 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/vco 0.26fF
+C1028 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in3 1.27fF
+C1029 cp_buffered_0/tapered_buf_1/in4 cp_buffered_0/tapered_buf_1/in5 29.21fF
+C1030 io_analog[3] ro_complete_buffered_0/ro_complete_0/a2 0.22fF
+C1031 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C1032 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF
+C1033 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF
+C1034 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
+C1035 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF
+C1036 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C1037 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/R 0.01fF
+C1038 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
+C1039 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF
+C1040 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/UP 0.61fF
+C1041 io_analog[5] ro_divider_buffered_0/ro_complete_0/a1 0.30fF
+C1042 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in5 29.21fF
+C1043 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z4 0.00fF
+C1044 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C1045 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C1046 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/clk 0.01fF
+C1047 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C1048 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in5 0.22fF
+C1049 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C1050 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1051 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/vco 0.26fF
+C1052 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Q 0.55fF
+C1053 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_divider_buffered_0/divider_0/clk 1.30fF
+C1054 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.45fF
+C1055 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C1056 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in4 4.78fF
+C1057 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/UP 0.61fF
+C1058 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF
+C1059 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1060 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF
+C1061 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C1062 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1063 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z4 0.00fF
+C1064 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_1/Z3 0.27fF
+C1065 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF
+C1066 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C1067 io_analog[5] io_clamp_low[1] 0.53fF
+C1068 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
+C1069 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C1070 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/div 0.65fF
+C1071 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C1072 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z1 0.01fF
+C1073 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_0/Q 0.22fF
+C1074 pd_buffered_0/tapered_buf_2/in2 pd_buffered_0/tapered_buf_2/in1 0.37fF
+C1075 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF
+C1076 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.05fF
+C1077 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF
+C1078 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
+C1079 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in5 0.84fF
+C1080 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF
+C1081 filter_buffered_0/tapered_buf_0/in5 gpio_analog[17] 26.29fF
+C1082 io_analog[5] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
+C1083 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z2 1.07fF
+C1084 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/REF 0.17fF
+C1085 io_analog[9] io_analog[7] 1.28fF
+C1086 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/div 4.07fF
+C1087 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C1088 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.12fF
+C1089 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C1090 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C1091 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C1092 gpio_noesd[14] gpio_noesd[7] 2.93fF
+C1093 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/out1 0.06fF
+C1094 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF
+C1095 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a1 3.18fF
+C1096 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z1 0.01fF
+C1097 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_0/Q 0.22fF
+C1098 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in5 0.84fF
+C1099 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C1100 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/A 0.80fF
+C1101 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C1102 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF
+C1103 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1104 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C1105 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z2 1.07fF
+C1106 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z3 0.38fF
+C1107 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z4 0.12fF
+C1108 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF
+C1109 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in3 1.27fF
+C1110 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C1111 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/tspc_r_1/Z4 0.14fF
+C1112 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C1113 gpio_analog[3] gpio_noesd[4] 1.38fF
+C1114 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF
+C1115 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.21fF
+C1116 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a0 0.47fF
+C1117 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/clk 0.12fF
+C1118 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF
+C1119 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF
+C1120 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1121 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/B 0.30fF
+C1122 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/divider_0/Out 0.20fF
+C1123 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF
+C1124 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
+C1125 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/REF 0.51fF
+C1126 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z2 1.07fF
+C1127 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z3 0.38fF
+C1128 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z4 0.12fF
+C1129 pll_full_buffered1_0/tapered_buf_1/in1 io_analog[10] 0.19fF
+C1130 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Z4 0.12fF
+C1131 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C1132 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF
+C1133 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.05fF
+C1134 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z2 0.40fF
+C1135 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/Out 0.04fF
+C1136 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/clk 0.29fF
+C1137 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/Z1 0.36fF
+C1138 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF
+C1139 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF
+C1140 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF
+C1141 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in1 0.37fF
+C1142 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1143 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF
+C1144 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.21fF
+C1145 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF
+C1146 gpio_analog[5] ro_divider_buffered_0/divider_0/mc2 0.49fF
+C1147 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/clk 0.26fF
+C1148 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF
+C1149 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Z4 0.12fF
+C1150 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C1151 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/clk 0.64fF
+C1152 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/REF 0.12fF
+C1153 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C1154 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C1155 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF
+C1156 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/div 0.05fF
+C1157 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C1158 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/Z1 0.36fF
+C1159 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF
+C1160 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
+C1161 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF
+C1162 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C1163 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/A 0.26fF
+C1164 pll_full_buffered2_0/tapered_buf_0/in5 pll_full_buffered2_0/pll_full_0/ref 26.29fF
+C1165 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.14fF
+C1166 gpio_noesd[7] io_analog[9] 1.42fF
+C1167 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in3 1.27fF
+C1168 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z2 0.01fF
+C1169 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C1170 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C1171 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C1172 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C1173 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C1174 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.04fF
+C1175 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF
+C1176 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF
+C1177 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C1178 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/nor_1/B 0.22fF
+C1179 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/clk 0.04fF
+C1180 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C1181 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF
+C1182 pd_buffered_0/tapered_buf_0/in3 pd_buffered_0/tapered_buf_0/in4 4.78fF
+C1183 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF
+C1184 gpio_noesd[7] gpio_analog[10] 0.77fF
+C1185 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/R 0.21fF
+C1186 io_analog[4] ro_divider_buffered_0/ro_complete_0/a4 0.19fF
+C1187 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a3 0.13fF
+C1188 ro_divider_buffered_0/tapered_buf_3/in5 ro_divider_buffered_0/ro_complete_0/a5 26.29fF
+C1189 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF
+C1190 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF
+C1191 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.27fF
+C1192 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C1193 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C1194 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/pd_0/DOWN 0.19fF
+C1195 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C1196 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF
+C1197 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C1198 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF
+C1199 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C1200 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/clk 0.04fF
+C1201 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/Z3 0.20fF
+C1202 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/REF 0.04fF
+C1203 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C1204 divider_buffered_0/tapered_buf_2/in1 divider_buffered_0/tapered_buf_2/in5 0.22fF
+C1205 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in2 0.84fF
+C1206 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/clk 0.64fF
+C1207 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 4.79fF
+C1208 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in4 4.78fF
+C1209 gpio_noesd[14] gpio_noesd[11] 2.58fF
+C1210 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C1211 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C1212 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF
+C1213 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF
+C1214 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.27fF
+C1215 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.05fF
+C1216 cp_buffered_0/tapered_buf_1/in5 gpio_noesd[9] 26.29fF
+C1217 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C1218 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in5 0.22fF
+C1219 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF
+C1220 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/divider_0/clk 26.29fF
+C1221 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C1222 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Z4 0.65fF
+C1223 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C1224 gpio_noesd[8] gpio_noesd[12] 0.46fF
+C1225 gpio_noesd[7] pll_full_buffered2_0/tapered_buf_5/in 0.54fF
+C1226 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in5 0.84fF
+C1227 pll_full_buffered2_0/tapered_buf_5/in5 pll_full_buffered2_0/tapered_buf_5/in1 0.22fF
+C1228 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C1229 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C1230 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.15fF
+C1231 ro_complete_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_4/in5 29.21fF
+C1232 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/and_0/B 0.29fF
+C1233 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
+C1234 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/A 0.01fF
+C1235 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in5 2.89fF
+C1236 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/clk 0.64fF
+C1237 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in4 4.78fF
+C1238 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/UP 0.45fF
+C1239 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z2 0.11fF
+C1240 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/div 0.45fF
+C1241 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/DOWN 0.36fF
+C1242 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/Z3 0.20fF
+C1243 io_analog[10] gpio_noesd[12] 1.57fF
+C1244 io_analog[9] div_pd_buffered_0/divider_0/clk 0.65fF
+C1245 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
+C1246 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/out1 0.31fF
+C1247 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/nor_1/B 0.21fF
+C1248 pd_buffered_0/pd_0/tspc_r_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Z3 0.09fF
+C1249 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z4 0.21fF
+C1250 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in4 29.21fF
+C1251 pd_buffered_0/tapered_buf_2/in2 pd_buffered_0/tapered_buf_2/in5 0.84fF
+C1252 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF
+C1253 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z3 0.45fF
+C1254 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.04fF
+C1255 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/A 0.26fF
+C1256 ro_complete_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_1/in5 29.21fF
+C1257 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
+C1258 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1259 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/a3 0.09fF
+C1260 io_analog[5] gpio_analog[6] 0.64fF
+C1261 io_analog[6] ro_complete_buffered_0/ro_complete_0/a1 0.22fF
+C1262 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C1263 io_analog[6] io_analog[8] 1.24fF
+C1264 io_analog[3] ro_divider_buffered_0/ro_complete_0/a4 0.19fF
+C1265 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/nor_1/A 0.15fF
+C1266 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C1267 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z2 0.23fF
+C1268 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1269 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/div 0.17fF
+C1270 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C1271 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.12fF
+C1272 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C1273 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z3 0.45fF
+C1274 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/A 0.26fF
+C1275 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
+C1276 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF
+C1277 gpio_analog[7] cp_buffered_0/tapered_buf_2/in1 0.19fF
+C1278 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_0/Z3 0.29fF
+C1279 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
+C1280 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z4 0.02fF
+C1281 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C1282 gpio_noesd[11] io_analog[9] 3.74fF
+C1283 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF
+C1284 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF
+C1285 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in4 4.78fF
+C1286 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in5 0.84fF
+C1287 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C1288 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.16fF
+C1289 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.22fF
+C1290 io_analog[4] ro_complete_buffered_0/tapered_buf_6/in1 0.19fF
+C1291 io_analog[5] ro_complete_buffered_0/tapered_buf_5/in1 0.19fF
+C1292 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
+C1293 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1294 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.12fF
+C1295 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C1296 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/out 26.29fF
+C1297 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
+C1298 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z3 0.65fF
+C1299 io_analog[4] ro_divider_buffered_0/ro_complete_0/a1 0.21fF
+C1300 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in5 0.22fF
+C1301 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF
+C1302 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C1303 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C1304 cp_buffered_0/tapered_buf_2/in2 cp_buffered_0/tapered_buf_2/in5 0.84fF
+C1305 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C1306 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C1307 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z3 0.16fF
+C1308 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.22fF
+C1309 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF
+C1310 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.65fF
+C1311 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C1312 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/vco 0.01fF
+C1313 gpio_noesd[11] gpio_analog[10] 0.49fF
+C1314 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z3 0.06fF
+C1315 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/Out 0.44fF
+C1316 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Z4 0.21fF
+C1317 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C1318 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/divider_0/clk 0.05fF
+C1319 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/cp_0/upbar 26.29fF
+C1320 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF
+C1321 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF
+C1322 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 0.22fF
+C1323 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/nor_1/A 0.03fF
+C1324 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in3 1.27fF
+C1325 ro_divider_buffered_0/divider_0/and_0/A ro_divider_buffered_0/divider_0/and_0/B 0.18fF
+C1326 gpio_analog[8] cp_buffered_0/cp_0/down 0.25fF
+C1327 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in5 0.22fF
+C1328 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Z4 0.65fF
+C1329 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C1330 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C1331 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C1332 io_analog[5] ro_divider_buffered_0/tapered_buf_5/in1 0.19fF
+C1333 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF
+C1334 pd_buffered_0/tapered_buf_3/in3 pd_buffered_0/tapered_buf_3/in4 4.78fF
+C1335 ashish_0/b io_analog[0] 8.93fF
+C1336 gpio_analog[3] gpio_analog[5] 1.06fF
+C1337 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/out1 0.06fF
+C1338 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Z4 0.21fF
+C1339 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z3 0.45fF
+C1340 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C1341 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C1342 ro_divider_buffered_0/tapered_buf_0/in5 gpio_noesd[5] 26.29fF
+C1343 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A 0.15fF
+C1344 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.09fF
+C1345 div_pd_buffered_0/divider_0/and_0/A div_pd_buffered_0/divider_0/and_0/B 0.18fF
+C1346 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C1347 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1348 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
+C1349 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF
+C1350 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.07fF
+C1351 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/div 0.25fF
+C1352 io_analog[4] ro_complete_buffered_0/ro_complete_0/a0 0.33fF
+C1353 io_analog[6] io_analog[9] 1.28fF
+C1354 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A 0.15fF
+C1355 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.09fF
+C1356 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in4 4.78fF
+C1357 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in5 0.84fF
+C1358 ro_divider_buffered_0/tapered_buf_8/in5 ro_divider_buffered_0/ro_complete_0/a0 26.29fF
+C1359 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
+C1360 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_0/B 0.15fF
+C1361 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C1362 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1363 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C1364 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/tspc_1/Z2 1.07fF
+C1365 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.07fF
+C1366 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
+C1367 io_clamp_low[0] io_clamp_high[0] 0.53fF
+C1368 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in5 2.89fF
+C1369 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/clk 0.26fF
+C1370 io_analog[10] pll_full_buffered2_0/pll_full_0/div 0.47fF
+C1371 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C1372 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C1373 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C1374 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in5 2.89fF
+C1375 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/R 0.36fF
+C1376 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF
+C1377 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF
+C1378 gpio_noesd[9] gpio_noesd[8] 1.97fF
+C1379 io_analog[3] ro_divider_buffered_0/ro_complete_0/a1 0.19fF
+C1380 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/nor_1/B 0.38fF
+C1381 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Q 0.05fF
+C1382 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in3 1.27fF
+C1383 div_pd_buffered_0/pd_0/DOWN gpio_noesd[12] 0.33fF
+C1384 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in3 2.89fF
+C1385 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z2 0.11fF
+C1386 pd_buffered_0/tapered_buf_2/in4 pd_buffered_0/tapered_buf_2/in3 4.78fF
+C1387 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.13fF
+C1388 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C1389 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1390 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/clk 0.26fF
+C1391 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.06fF
+C1392 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
+C1393 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z3 0.45fF
+C1394 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/divider_0/clk 0.05fF
+C1395 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C1396 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C1397 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in2 0.37fF
+C1398 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 3.73fF
+C1399 pll_full_buffered2_0/tapered_buf_2/in4 pll_full_buffered2_0/tapered_buf_2/in3 4.78fF
+C1400 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/vco 0.60fF
+C1401 gpio_analog[6] ro_complete_buffered_0/tapered_buf_0/in1 0.19fF
+C1402 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1403 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
+C1404 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/nor_1/A 0.35fF
+C1405 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C1406 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/R 0.36fF
+C1407 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF
+C1408 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF
+C1409 gpio_noesd[9] io_analog[10] 1.63fF
+C1410 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.13fF
+C1411 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in5 2.89fF
+C1412 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/divider_0/mc2 0.34fF
+C1413 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in2 1.27fF
+C1414 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/R 0.21fF
+C1415 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/z5 0.03fF
+C1416 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF
+C1417 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C1418 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C1419 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.06fF
+C1420 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C1421 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in3 4.78fF
+C1422 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C1423 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/tspc_1/Z2 0.01fF
+C1424 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.35fF
+C1425 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/vco 0.60fF
+C1426 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF
+C1427 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF
+C1428 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C1429 divider_buffered_0/divider_0/tspc_2/Z4 divider_buffered_0/divider_0/nor_1/B 0.02fF
+C1430 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/UP 0.33fF
+C1431 pd_buffered_0/tapered_buf_3/in1 io_analog[10] 0.19fF
+C1432 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in3 1.27fF
+C1433 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in1 0.37fF
+C1434 filter_buffered_0/tapered_buf_1/in4 filter_buffered_0/tapered_buf_1/in5 29.21fF
+C1435 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in5 0.22fF
+C1436 io_analog[3] ro_complete_buffered_0/ro_complete_0/a0 0.20fF
+C1437 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF
+C1438 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C1439 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF
+C1440 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF
+C1441 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z4 0.12fF
+C1442 pd_buffered_0/pd_0/tspc_r_1/z5 pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.20fF
+C1443 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF
+C1444 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C1445 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C1446 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF
+C1447 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C1448 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/div 0.17fF
+C1449 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in3 2.89fF
+C1450 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.06fF
+C1451 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z2 0.11fF
+C1452 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1453 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z4 0.15fF
+C1454 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in2 0.37fF
+C1455 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF
+C1456 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
+C1457 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF
+C1458 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF
+C1459 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in3 1.27fF
+C1460 cp_buffered_0/tapered_buf_2/in4 cp_buffered_0/tapered_buf_2/in3 4.78fF
+C1461 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in4 4.78fF
+C1462 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in2 0.84fF
+C1463 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C1464 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a4 0.13fF
+C1465 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/R 0.03fF
+C1466 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in2 0.84fF
+C1467 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_0/B 0.22fF
+C1468 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_0/Q 0.15fF
+C1469 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C1470 gpio_noesd[13] gpio_noesd[12] 0.45fF
+C1471 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/A 0.04fF
+C1472 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C1473 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.45fF
+C1474 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a3 2.04fF
+C1475 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z4 0.15fF
+C1476 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF
+C1477 io_analog[9] pll_full_buffered2_0/tapered_buf_3/in 0.61fF
+C1478 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in5 0.22fF
+C1479 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF
+C1480 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in3 1.27fF
+C1481 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C1482 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
+C1483 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.36fF
+C1484 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/Out 0.05fF
+C1485 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF
+C1486 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
+C1487 ro_complete_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_6/in5 29.21fF
+C1488 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF
+C1489 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C1490 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/nor_1/A 0.15fF
+C1491 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/R 0.03fF
+C1492 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z3 0.09fF
+C1493 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.05fF
+C1494 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF
+C1495 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/UP 0.03fF
+C1496 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C1497 pll_full_buffered2_0/tapered_buf_2/in1 pll_full_buffered2_0/pll_full_0/div 0.19fF
+C1498 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in5 2.89fF
+C1499 ro_divider_buffered_0/tapered_buf_6/in5 ro_divider_buffered_0/ro_complete_0/a2 26.29fF
+C1500 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF
+C1501 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF
+C1502 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF
+C1503 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C1504 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C1505 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C1506 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.16fF
+C1507 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
+C1508 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in1 0.37fF
+C1509 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in5 2.89fF
+C1510 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/a0 3.46fF
+C1511 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C1512 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C1513 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z4 0.36fF
+C1514 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/UP 1.14fF
+C1515 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.30fF
+C1516 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C1517 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z4 0.00fF
+C1518 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in2 0.37fF
+C1519 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C1520 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF
+C1521 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/div 0.05fF
+C1522 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 3.73fF
+C1523 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in5 2.89fF
+C1524 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1525 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF
+C1526 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in5 0.84fF
+C1527 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in2 0.37fF
+C1528 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C1529 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C1530 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C1531 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.06fF
+C1532 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in4 29.21fF
+C1533 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/B 0.08fF
+C1534 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF
+C1535 io_analog[4] io_clamp_low[0] 0.53fF
+C1536 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C1537 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C1538 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C1539 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in5 0.22fF
+C1540 io_analog[9] divider_buffered_0/tapered_buf_0/in1 0.19fF
+C1541 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C1542 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.47fF
+C1543 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C1544 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.14fF
+C1545 ro_divider_buffered_0/tapered_buf_1/in1 ro_divider_buffered_0/tapered_buf_1/in2 0.37fF
+C1546 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.02fF
+C1547 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C1548 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF
+C1549 gpio_analog[9] gpio_noesd[9] 1.46fF
+C1550 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/UP 0.03fF
+C1551 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/pd_0/DOWN 0.19fF
+C1552 io_analog[4] gpio_analog[6] 0.64fF
+C1553 io_analog[5] ro_complete_buffered_0/ro_complete_0/a1 0.22fF
+C1554 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in4 29.21fF
+C1555 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.06fF
+C1556 io_analog[5] io_analog[8] 1.24fF
+C1557 io_analog[6] io_analog[7] 1.12fF
+C1558 ro_divider_buffered_0/tapered_buf_6/in4 ro_divider_buffered_0/tapered_buf_6/in5 29.21fF
+C1559 pd_buffered_0/tapered_buf_0/in2 pd_buffered_0/tapered_buf_0/in5 0.84fF
+C1560 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C1561 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C1562 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C1563 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C1564 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/clk 0.14fF
+C1565 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C1566 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.14fF
+C1567 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.02fF
+C1568 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C1569 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/clk 0.45fF
+C1570 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C1571 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 1.21fF
+C1572 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C1573 gpio_noesd[11] gpio_noesd[7] 0.79fF
+C1574 pd_buffered_0/tapered_buf_1/in2 pd_buffered_0/tapered_buf_1/in3 1.27fF
+C1575 pd_buffered_0/tapered_buf_2/in1 pd_buffered_0/tapered_buf_2/in5 0.22fF
+C1576 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in5 0.22fF
+C1577 div_pd_buffered_0/tapered_buf_2/in2 div_pd_buffered_0/tapered_buf_2/in3 1.27fF
+C1578 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
+C1579 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF
+C1580 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C1581 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a1 1.84fF
+C1582 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in4 4.78fF
+C1583 pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# 0.04fF
+C1584 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF
+C1585 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF
+C1586 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C1587 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C1588 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.35fF
+C1589 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/out 0.84fF
+C1590 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.04fF
+C1591 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/vco 0.05fF
+C1592 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 io_analog[2] 26.29fF
+C1593 gpio_noesd[9] gpio_analog[8] 2.46fF
+C1594 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/tapered_buf_0/in2 0.37fF
+C1595 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF
+C1596 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF
+C1597 cp_buffered_0/cp_0/out cp_buffered_0/cp_0/down 0.79fF
+C1598 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.43fF
+C1599 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_0/Q 0.45fF
+C1600 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in1 0.22fF
+C1601 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.14fF
+C1602 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in1 0.37fF
+C1603 io_analog[10] pll_full_buffered2_0/tapered_buf_0/in1 0.19fF
+C1604 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF
+C1605 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/and_0/OUT 0.14fF
+C1606 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_0/B 0.15fF
+C1607 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.30fF
+C1608 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in1 0.22fF
+C1609 pd_buffered_0/tapered_buf_3/in1 pd_buffered_0/tapered_buf_3/in5 0.22fF
+C1610 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.04fF
+C1611 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF
+C1612 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/vco 0.05fF
+C1613 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in2 0.37fF
+C1614 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_0/Q 0.01fF
+C1615 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF
+C1616 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in5 0.22fF
+C1617 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z2 0.19fF
+C1618 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in5 0.84fF
+C1619 io_analog[3] gpio_analog[6] 0.53fF
+C1620 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF
+C1621 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in5 2.89fF
+C1622 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF
+C1623 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C1624 io_analog[5] io_analog[9] 1.28fF
+C1625 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in4 29.21fF
+C1626 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C1627 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C1628 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a4 0.12fF
+C1629 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C1630 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_0/Z4 0.02fF
+C1631 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF
+C1632 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
+C1633 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/clk 0.45fF
+C1634 divider_buffered_0/tapered_buf_2/in4 divider_buffered_0/tapered_buf_2/in3 4.78fF
+C1635 io_analog[9] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.53fF
+C1636 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 0.06fF
+C1637 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C1638 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
+C1639 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.31fF
+C1640 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C1641 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in3 1.27fF
+C1642 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF
+C1643 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C1644 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1645 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/mc2 0.04fF
+C1646 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C1647 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in4 4.78fF
+C1648 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/REF 0.04fF
+C1649 div_pd_buffered_0/tapered_buf_4/in4 div_pd_buffered_0/tapered_buf_4/in5 29.21fF
+C1650 io_analog[3] ro_divider_buffered_0/ro_complete_0/a5 0.17fF
+C1651 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z2 0.14fF
+C1652 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1653 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C1654 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C1655 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C1656 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C1657 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C1658 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.09fF
+C1659 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 0.09fF
+C1660 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/clk 0.45fF
+C1661 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_3/in3 4.78fF
+C1662 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/B 0.20fF
+C1663 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.00fF
+C1664 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C1665 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C1666 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/divider_0/clk 0.05fF
+C1667 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.22fF
+C1668 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF
+C1669 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C1670 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C1671 gpio_noesd[14] gpio_noesd[8] 2.61fF
+C1672 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in5 0.84fF
+C1673 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C1674 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 divider_buffered_0/divider_0/clk 0.12fF
+C1675 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/upbar 0.29fF
+C1676 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z4 0.65fF
+C1677 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C1678 ashish_0/b io_analog[1] 4.11fF
+C1679 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C1680 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.09fF
+C1681 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 0.09fF
+C1682 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/DOWN 0.11fF
+C1683 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.17fF
+C1684 ashish_0/b ashish_0/a 7.45fF
+C1685 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF
+C1686 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C1687 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C1688 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C1689 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C1690 gpio_noesd[14] io_analog[10] 2.21fF
+C1691 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/nor_1/A 0.15fF
+C1692 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/a0 0.09fF
+C1693 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF
+C1694 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C1695 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1696 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF
+C1697 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.51fF
+C1698 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C1699 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/vco 0.15fF
+C1700 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/tspc_2/Z4 0.65fF
+C1701 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.05fF
+C1702 pd_buffered_0/tapered_buf_2/in1 pd_buffered_0/pd_0/UP 0.19fF
+C1703 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 29.21fF
+C1704 pll_full_buffered2_0/tapered_buf_3/in5 pll_full_buffered2_0/tapered_buf_3/out 26.29fF
+C1705 ro_divider_buffered_0/divider_0/and_0/B ro_divider_buffered_0/divider_0/and_0/Z1 0.07fF
+C1706 io_analog[4] ro_complete_buffered_0/ro_complete_0/a4 0.20fF
+C1707 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/mc2 0.33fF
+C1708 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
+C1709 divider_buffered_0/tapered_buf_1/in2 divider_buffered_0/tapered_buf_1/in1 0.37fF
+C1710 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF
+C1711 pll_full_buffered2_0/tapered_buf_5/in4 pll_full_buffered2_0/tapered_buf_5/in5 29.21fF
+C1712 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in3 1.27fF
+C1713 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C1714 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C1715 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF
+C1716 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C1717 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/vco 0.15fF
+C1718 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in3 4.78fF
+C1719 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C1720 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1721 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C1722 div_pd_buffered_0/divider_0/and_0/B div_pd_buffered_0/divider_0/and_0/Z1 0.07fF
+C1723 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.00fF
+C1724 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/A 0.16fF
+C1725 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.06fF
+C1726 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
+C1727 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF
+C1728 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in3 4.78fF
+C1729 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a3 3.17fF
+C1730 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C1731 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
+C1732 pd_buffered_0/tapered_buf_1/in2 pd_buffered_0/tapered_buf_1/in1 0.37fF
+C1733 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in5 0.22fF
+C1734 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
+C1735 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C1736 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
+C1737 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C1738 io_analog[9] gpio_noesd[8] 0.91fF
+C1739 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF
+C1740 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF
+C1741 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z3 0.38fF
+C1742 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
+C1743 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF
+C1744 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C1745 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C1746 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
+C1747 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF
+C1748 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C1749 gpio_analog[3] gpio_noesd[5] 0.96fF
+C1750 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.35fF
+C1751 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/clk 0.60fF
+C1752 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C1753 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
+C1754 ro_divider_buffered_0/tapered_buf_2/in4 ro_divider_buffered_0/tapered_buf_2/in5 29.21fF
+C1755 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.19fF
+C1756 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C1757 pll_full_buffered2_0/pll_full_0/cp_0/vbias pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# 0.19fF
+C1758 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
+C1759 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in5 0.22fF
+C1760 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
+C1761 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.11fF
+C1762 gpio_noesd[8] gpio_analog[10] 0.48fF
+C1763 io_analog[9] io_analog[10] 1065.06fF
+C1764 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.33fF
+C1765 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
+C1766 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C1767 div_pd_buffered_0/tapered_buf_0/in4 div_pd_buffered_0/tapered_buf_0/in5 29.21fF
+C1768 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF
+C1769 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1770 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C1771 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.22fF
+C1772 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C1773 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C1774 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.35fF
+C1775 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/clk 0.60fF
+C1776 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C1777 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z2 1.07fF
+C1778 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/divider_0/clk 0.05fF
+C1779 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in5 2.89fF
+C1780 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_0/Qbar 0.02fF
+C1781 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/UP 0.45fF
+C1782 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C1783 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF
+C1784 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C1785 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
+C1786 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/nor_1/B 0.30fF
+C1787 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 gpio_noesd[14] 26.29fF
+C1788 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.35fF
+C1789 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/vco 0.29fF
+C1790 ro_divider_buffered_0/tapered_buf_2/in4 ro_divider_buffered_0/tapered_buf_2/in3 4.78fF
+C1791 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in2 0.84fF
+C1792 filter_buffered_0/filter_0/v gpio_analog[17] 0.54fF
+C1793 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in5 0.22fF
+C1794 io_analog[3] ro_complete_buffered_0/ro_complete_0/a4 0.17fF
+C1795 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.08fF
+C1796 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C1797 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C1798 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C1799 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.11fF
+C1800 io_analog[10] gpio_analog[10] 1.17fF
+C1801 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1802 pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered1_0/pll_full_0/cp_0/vbias 0.19fF
+C1803 divider_buffered_0/tapered_buf_1/in2 divider_buffered_0/tapered_buf_1/in5 0.84fF
+C1804 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF
+C1805 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C1806 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
+C1807 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in2 0.37fF
+C1808 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z2 0.23fF
+C1809 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1810 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF
+C1811 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C1812 io_analog[9] ro_divider_buffered_0/divider_0/Out 1.19fF
+C1813 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF
+C1814 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/div 0.04fF
+C1815 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/vco 0.29fF
+C1816 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in5 2.89fF
+C1817 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C1818 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.45fF
+C1819 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C1820 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/vco 1.27fF
+C1821 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in5 2.89fF
+C1822 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF
+C1823 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in2 0.84fF
+C1824 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 0.38fF
+C1825 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C1826 ro_divider_buffered_0/tapered_buf_2/in2 ro_divider_buffered_0/tapered_buf_2/in3 1.27fF
+C1827 io_analog[4] ro_complete_buffered_0/ro_complete_0/a1 0.32fF
+C1828 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.20fF
+C1829 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF
+C1830 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C1831 io_analog[4] io_analog[8] 1.24fF
+C1832 io_analog[5] io_analog[7] 1.11fF
+C1833 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF
+C1834 gpio_noesd[14] gpio_analog[9] 2.63fF
+C1835 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
+C1836 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.06fF
+C1837 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C1838 pd_buffered_0/pd_0/tspc_r_1/z5 pd_buffered_0/pd_0/tspc_r_0/z5 0.02fF
+C1839 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF
+C1840 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/B 0.01fF
+C1841 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/clk 0.12fF
+C1842 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C1843 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.04fF
+C1844 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C1845 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/vco 1.27fF
+C1846 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C1847 io_analog[6] io_clamp_high[2] 0.53fF
+C1848 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF
+C1849 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.16fF
+C1850 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
+C1851 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in4 4.78fF
+C1852 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in5 0.84fF
+C1853 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF
+C1854 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in5 2.89fF
+C1855 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/R 0.29fF
+C1856 div_pd_buffered_0/tapered_buf_4/in5 gpio_noesd[13] 26.29fF
+C1857 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/divider_0/mc2 26.29fF
+C1858 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a5 0.13fF
+C1859 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in5 0.22fF
+C1860 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.03fF
+C1861 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/B 0.06fF
+C1862 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/nor_1/A 0.21fF
+C1863 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1864 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_0/B 0.06fF
+C1865 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered2_0/pll_full_0/div 0.04fF
+C1866 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.47fF
+C1867 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C1868 div_pd_buffered_0/divider_0/tspc_0/Z2 div_pd_buffered_0/divider_0/tspc_0/Z3 0.16fF
+C1869 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
+C1870 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in3 2.89fF
+C1871 divider_buffered_0/tapered_buf_1/in5 gpio_noesd[4] 26.29fF
+C1872 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
+C1873 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.00fF
+C1874 div_pd_buffered_0/tapered_buf_3/in4 div_pd_buffered_0/tapered_buf_3/in5 29.21fF
+C1875 io_analog[9] divider_buffered_0/divider_0/clk 0.40fF
+C1876 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/tapered_buf_3/in 0.03fF
+C1877 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in5 0.22fF
+C1878 pd_buffered_0/pd_0/tspc_r_1/Qbar pd_buffered_0/pd_0/DOWN 0.21fF
+C1879 io_analog[4] ro_divider_buffered_0/tapered_buf_4/in1 0.19fF
+C1880 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF
+C1881 gpio_noesd[14] gpio_analog[8] 2.77fF
+C1882 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
+C1883 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/B 0.18fF
+C1884 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C1885 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 0.31fF
+C1886 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.15fF
+C1887 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C1888 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1889 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF
+C1890 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C1891 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C1892 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.14fF
+C1893 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/down 0.32fF
+C1894 gpio_analog[9] io_analog[9] 0.93fF
+C1895 io_analog[3] ro_complete_buffered_0/ro_complete_0/a1 0.17fF
+C1896 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
+C1897 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
+C1898 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.04fF
+C1899 io_analog[4] io_analog[9] 1.28fF
+C1900 io_analog[3] io_analog[8] 1.02fF
+C1901 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in4 4.78fF
+C1902 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in5 0.84fF
+C1903 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/Out 0.05fF
+C1904 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/UP 2.89fF
+C1905 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C1906 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C1907 gpio_noesd[14] gpio_noesd[13] 2.55fF
+C1908 div_pd_buffered_0/tapered_buf_0/in5 div_pd_buffered_0/tapered_buf_0/in1 0.22fF
+C1909 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z3 0.65fF
+C1910 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C1911 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/B 0.20fF
+C1912 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.35fF
+C1913 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C1914 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in2 0.37fF
+C1915 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.29fF
+C1916 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z2 0.15fF
+C1917 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C1918 pd_buffered_0/tapered_buf_0/in2 pd_buffered_0/tapered_buf_0/in3 1.27fF
+C1919 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.05fF
+C1920 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/and_0/OUT 0.06fF
+C1921 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C1922 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C1923 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in5 2.89fF
+C1924 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/REF 0.12fF
+C1925 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/R 0.61fF
+C1926 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.06fF
+C1927 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.15fF
+C1928 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C1929 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.05fF
+C1930 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C1931 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in5 2.89fF
+C1932 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/nor_1/B 0.30fF
+C1933 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C1934 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF
+C1935 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
+C1936 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/Z1 0.04fF
+C1937 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z2 0.01fF
+C1938 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/clk 0.05fF
+C1939 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
+C1940 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/R 0.61fF
+C1941 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.09fF
+C1942 gpio_analog[8] io_analog[9] 1.10fF
+C1943 gpio_noesd[14] gpio_analog[7] 2.55fF
+C1944 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/mc2 0.05fF
+C1945 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in5 2.89fF
+C1946 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.02fF
+C1947 io_analog[8] ro_divider_buffered_0/tapered_buf_8/in1 0.19fF
+C1948 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.04fF
+C1949 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z2 0.36fF
+C1950 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C1951 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_0/B 0.06fF
+C1952 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.08fF
+C1953 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C1954 gpio_analog[3] gpio_analog[6] 1.30fF
+C1955 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/Z1 0.04fF
+C1956 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z2 0.01fF
+C1957 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/clk 0.05fF
+C1958 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/clk 0.45fF
+C1959 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF
+C1960 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.05fF
+C1961 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF
+C1962 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C1963 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF
+C1964 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
+C1965 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C1966 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF
+C1967 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in5 29.21fF
+C1968 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF
+C1969 gpio_analog[8] cp_buffered_0/tapered_buf_0/in1 0.19fF
+C1970 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/DIV 0.19fF
+C1971 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
+C1972 io_analog[9] gpio_noesd[13] 2.15fF
+C1973 io_analog[3] io_analog[9] 1.00fF
+C1974 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF
+C1975 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C1976 divider_buffered_0/tapered_buf_1/in3 divider_buffered_0/tapered_buf_1/in5 2.89fF
+C1977 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C1978 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
+C1979 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C1980 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in2 1.27fF
+C1981 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C1982 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.18fF
+C1983 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C1984 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/B 0.18fF
+C1985 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z2 0.14fF
+C1986 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF
+C1987 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/div 0.27fF
+C1988 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.01fF
+C1989 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF
+C1990 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C1991 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C1992 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/A 0.01fF
+C1993 ro_divider_buffered_0/tapered_buf_0/in3 ro_divider_buffered_0/tapered_buf_0/in2 1.27fF
+C1994 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.00fF
+C1995 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C1996 ro_divider_buffered_0/tapered_buf_2/in2 ro_divider_buffered_0/tapered_buf_2/in1 0.37fF
+C1997 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF
+C1998 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.45fF
+C1999 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF
+C2000 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C2001 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/DOWN 0.11fF
+C2002 io_analog[8] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
+C2003 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C2004 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a4 0.09fF
+C2005 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a5 0.09fF
+C2006 div_pd_buffered_0/tapered_buf_1/in4 div_pd_buffered_0/tapered_buf_1/in3 4.78fF
+C2007 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.00fF
+C2008 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_0/Q 0.14fF
+C2009 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C2010 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/clk 0.01fF
+C2011 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.51fF
+C2012 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF
+C2013 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C2014 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C2015 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z1 0.03fF
+C2016 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C2017 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C2018 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C2019 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C2020 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered1_0/pll_full_0/div 0.04fF
+C2021 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.00fF
+C2022 ro_complete_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_5/in5 29.21fF
+C2023 gpio_analog[7] io_analog[9] 1.40fF
+C2024 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF
+C2025 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C2026 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C2027 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/tapered_buf_0/in5 0.22fF
+C2028 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF
+C2029 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF
+C2030 gpio_noesd[7] io_analog[10] 5.73fF
+C2031 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C2032 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C2033 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in5 2.89fF
+C2034 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z3 0.06fF
+C2035 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/Out 0.05fF
+C2036 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF
+C2037 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF
+C2038 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.65fF
+C2039 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C2040 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/divider_0/clk 0.10fF
+C2041 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/tspc_r_0/Qbar 0.03fF
+C2042 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C2043 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in5 2.89fF
+C2044 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
+C2045 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C2046 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF
+C2047 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in2 0.37fF
+C2048 pll_full_buffered1_0/tapered_buf_1/in5 pll_full_buffered1_0/pll_full_0/ref 26.29fF
+C2049 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF
+C2050 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/R 0.27fF
+C2051 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/UP 0.21fF
+C2052 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/Z2 0.36fF
+C2053 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.16fF
+C2054 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C2055 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 1.21fF
+C2056 div_pd_buffered_0/pd_0/UP div_pd_buffered_0/tapered_buf_0/in1 0.19fF
+C2057 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/nor_1/B 1.21fF
+C2058 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
+C2059 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C2060 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z3 0.38fF
+C2061 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.14fF
+C2062 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.00fF
+C2063 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.14fF
+C2064 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/vco 0.51fF
+C2065 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/nor_1/B 0.47fF
+C2066 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z3 0.65fF
+C2067 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.29fF
+C2068 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.08fF
+C2069 io_analog[4] io_analog[7] 1.11fF
+C2070 io_analog[5] io_analog[6] 21.00fF
+C2071 ro_divider_buffered_0/tapered_buf_5/in4 ro_divider_buffered_0/tapered_buf_5/in5 29.21fF
+C2072 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF
+C2073 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
+C2074 cp_buffered_0/tapered_buf_2/in2 cp_buffered_0/tapered_buf_2/in3 1.27fF
+C2075 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.14fF
+C2076 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/vco 0.51fF
+C2077 ro_divider_buffered_0/tapered_buf_7/in5 ro_divider_buffered_0/ro_complete_0/a1 26.29fF
+C2078 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C2079 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
+C2080 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C2081 pll_full_buffered2_0/tapered_buf_2/in2 pll_full_buffered2_0/tapered_buf_2/in1 0.37fF
+C2082 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/nor_0/B 0.22fF
+C2083 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C2084 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
+C2085 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.08fF
+C2086 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C2087 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF
+C2088 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
+C2089 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF
+C2090 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/tapered_buf_3/in1 0.22fF
+C2091 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a1 3.18fF
+C2092 gpio_noesd[14] gpio_noesd[10] 2.89fF
+C2093 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C2094 ro_complete_buffered_0/tapered_buf_3/in1 io_analog[7] 0.19fF
+C2095 io_analog[9] pll_full_buffered2_0/tapered_buf_1/in1 0.19fF
+C2096 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF
+C2097 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.30fF
+C2098 gpio_noesd[14] pll_full_buffered1_0/pll_full_0/vco 0.69fF
+C2099 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C2100 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C2101 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/div 0.12fF
+C2102 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z3 0.65fF
+C2103 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C2104 io_analog[10] div_pd_buffered_0/divider_0/clk 0.61fF
+C2105 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C2106 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.08fF
+C2107 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C2108 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF
+C2109 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
+C2110 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a5 2.39fF
+C2111 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C2112 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/B 0.08fF
+C2113 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/nor_0/B 0.22fF
+C2114 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C2115 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/clk 0.01fF
+C2116 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.55fF
+C2117 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in5 0.22fF
+C2118 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z2 0.23fF
+C2119 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C2120 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/divider_0/clk 1.30fF
+C2121 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.40fF
+C2122 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/Out 0.04fF
+C2123 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/clk 0.29fF
+C2124 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.22fF
+C2125 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C2126 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF
+C2127 gpio_noesd[11] gpio_noesd[8] 0.55fF
+C2128 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/tapered_buf_3/in 0.02fF
+C2129 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.30fF
+C2130 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in2 0.37fF
+C2131 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_1/in5 26.29fF
+C2132 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Out1 0.05fF
+C2133 io_analog[6] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
+C2134 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in2 0.37fF
+C2135 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/clk 0.51fF
+C2136 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/and_0/B 0.78fF
+C2137 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF
+C2138 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF
+C2139 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/nor_0/B 0.42fF
+C2140 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.03fF
+C2141 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF
+C2142 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/A 0.35fF
+C2143 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C2144 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C2145 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF
+C2146 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C2147 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.09fF
+C2148 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.31fF
+C2149 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C2150 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF
+C2151 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C2152 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.40fF
+C2153 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/clk 0.29fF
+C2154 io_analog[1] io_analog[0] 8.34fF
+C2155 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF
+C2156 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Q 0.04fF
+C2157 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C2158 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/divider_0/clk 1.27fF
+C2159 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z1 0.03fF
+C2160 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z3 0.05fF
+C2161 gpio_noesd[11] io_analog[10] 1.30fF
+C2162 ashish_0/a io_analog[0] 4.11fF
+C2163 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF
+C2164 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/div 0.04fF
+C2165 gpio_analog[9] gpio_noesd[7] 1.96fF
+C2166 gpio_noesd[9] cp_buffered_0/cp_0/down 0.38fF
+C2167 io_analog[3] ro_complete_buffered_0/ro_complete_0/a5 0.15fF
+C2168 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in2 0.37fF
+C2169 gpio_analog[10] div_pd_buffered_0/tapered_buf_3/in1 0.19fF
+C2170 io_analog[3] io_analog[7] 0.92fF
+C2171 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in4 4.78fF
+C2172 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF
+C2173 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C2174 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.09fF
+C2175 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Q 0.04fF
+C2176 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF
+C2177 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C2178 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C2179 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C2180 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
+C2181 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/vco 0.55fF
+C2182 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C2183 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF
+C2184 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in2 0.84fF
+C2185 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.04fF
+C2186 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF
+C2187 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C2188 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C2189 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
+Xpll_full_buffered1_0 vssa1 vdda1 pll_full_buffered1
 Xashish_0 io_analog[1] io_analog[0] gpio_analog[3] vssa1 vdd ashish_0/a ashish_0/b
 + ashish
 Xpd_buffered_0 vssa1 vssa1 pd_buffered
-Xcp_buffered_0 vssa1 vssa1 cp_buffered
+Xcp_buffered_0 vssa1 vdda1 cp_buffered
 Xfilter_buffered_0 vssa1 gpio_analog[17] filter_buffered
-Xro_divider_buffered_0 vssa1 vssa1 ro_divider_buffered
-Xpll_full_buffered2_0 vssa1 vdd pll_full_buffered2
-Xdivider_buffered_0 vssa1 vssa1 divider_buffered
+Xro_divider_buffered_0 vssa1 vdda1 ro_divider_buffered
+Xpll_full_buffered2_0 vssa1 vdda1 pll_full_buffered2
+Xdivider_buffered_0 vssa1 vdda1 divider_buffered
 Xro_complete_buffered_0 vssa1 ro_complete_buffered
-Xdiv_pd_buffered_0 vdd vssa1 div_pd_buffered
+Xdiv_pd_buffered_0 vdda1 vssa1 div_pd_buffered
 C2190 io_in_3v3[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
 C2191 io_oeb[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
 C2192 io_in[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF