final gds oasis
87 files changed
tree: e1e7eb4f19a160fa9f97dc52cabb40f079bb56a0
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. mpw_precheck/
  9. openlane/
  10. signoff/
  11. spi/
  12. tapeout/
  13. verilog/
  14. .gitignore
  16. Makefile

Caravel User Project

License UPRJ_CI Caravel Build

Demonstration of the fully open FABulous eFPGA using the OpenLane flow.

This repo experiments an implementation of an eFPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 576x LUT4s (12x6 CLBs), 48x LUT5s (12x1 RegFiles), 6x DSPs and 6x BRAMs (6x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g., to RISC-V core) were also implemented in this version.

The fabrics were fully implemented using the OpenLane flow then integrated onto eFabless caravel.