| # Caravel User Project |
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| [](https://opensource.org/licenses/Apache-2.0) [](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml) |
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| | :exclamation: Important Note | |
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| # OSU gf180mcuC 3.3V standard cell caravel test - ffra |
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| [](https://opensource.org/licenses/Apache-2.0) [](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) |
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| ## An 32-bit ffra adder implementation using OSU standard cells |
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| This design is an adder implementation of Anton Blanchard's [vlsiffra](docs/source/index.rst) architecture. The purpose of this is to make OpenLane's gf180mcuC pdk and overall flow compatible with a 3.3V standard cell kit, as well as to test the functionality of OSU's standard cell library for the gf180 process node. |
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| The use of this design is very simple, and should be compatible with any external controller. Caravel's GPIO is setup exclusively with user input settings, so that the IO of the chip and be interacted with directly. |
