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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-18h1 / slot-002 / refs/heads/main / . / verilog / rtl / project
tree: a66c02c0d765bda3261f185581088941ee9335d5 [path history] [tgz]
  1. README.md
  2. top.v
verilog/rtl/project/README.md

This is a basic DES HDL design.