|author||Jeff DiCorpo <firstname.lastname@example.org>||Wed Dec 14 22:22:04 2022 -0800|
|committer||Jeff DiCorpo <email@example.com>||Wed Dec 14 22:22:04 2022 -0800|
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.