| commit | dfa22ac188f55b03656cb88268f796c758444398 | [log] [tgz] |
|---|---|---|
| author | james <james@neptune.cassia.ai> | Mon Dec 05 13:12:34 2022 -0800 |
| committer | james <james@neptune.cassia.ai> | Mon Dec 05 13:12:34 2022 -0800 |
| tree | d0ede4b03e349cf24367e0321b9213fd27382565 | |
| parent | a6b0c77505e756f217b821b21619b86a4f5434af [diff] |
user_defines.v fix precheck again
A basic pulse with modulation core with 8 PWMs controled by a wishbone bus slave interface. The PWMs are 8-bit programmable with full range of duty cycle control. All PWMS run synchronized to a single counter.
A simple pulse width modulator connected to a wishbone bus. Given an input clock signal, it is capable of dividing the signal by 2^n where 0 <= n < 24. This allows a 100MHz core fequency to be stepped down to just under 6 Hz if need be. The frequency of each PWM is individually controlled by the Divider registers which store the value n_i for PWM i. The Threshold register sets the duty cycle for each PWM such that its value v_i has duty cycle (256-v_i)/256 and valid v_i values are 0 < v_i <= 255. Note that v_i=0 turns off PWM i.