| commit | cddad610d2e2c214367ba77af97ed1b576b5374a | [log] [tgz] |
|---|---|---|
| author | james <james@neptune.cassia.ai> | Mon Dec 05 14:25:44 2022 -0800 |
| committer | james <james@neptune.cassia.ai> | Mon Dec 05 14:25:44 2022 -0800 |
| tree | e5739c0857bc2e38fb1017f3e49ebdf6cd4c72b4 | |
| parent | 90f990d4a361e291e3b51bbdb5a37d7c2d6e2882 [diff] |
spdx again
A basic pulse with modulation core with 8 PWMs controled by a wishbone bus slave interface. The PWMs are 8-bit programmable with full range of duty cycle control. All PWMS run synchronized to a single counter.
A simple pulse width modulator connected to a wishbone bus. Given an input clock signal, it is capable of dividing the signal by 2^n where 0 <= n < 24. This allows a 100MHz core fequency to be stepped down to just under 6 Hz if need be. The frequency of each PWM is individually controlled by the Divider registers which store the value n_i for PWM i. The Threshold register sets the duty cycle for each PWM such that its value v_i has duty cycle (256-v_i)/256 and valid v_i values are 0 < v_i <= 255. Note that v_i=0 turns off PWM i.