| commit | 7a053b8dfe5933f5a79bf8118705179231655886 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Wed Dec 14 22:28:26 2022 -0800 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Wed Dec 14 22:28:26 2022 -0800 |
| tree | 9cb81c4f7596503b0b15c7c7c3391460c22c0fd6 | |
| parent | b46529b35ce439c4431ddf082d0a9ed335fd4995 [diff] |
update repo
A basic pulse with modulation core with 8 PWMs controled by a wishbone bus slave interface. The PWMs are 8-bit programmable with full range of duty cycle control. All PWMS run synchronized to a single counter.
A simple pulse width modulator connected to a wishbone bus. Given an input clock signal, it is capable of dividing the signal by 2^n where 0 <= n < 24. This allows a 100MHz core fequency to be stepped down to just under 6 Hz if need be. The frequency of each PWM is individually controlled by the Divider registers which store the value n_i for PWM i. The Threshold register sets the duty cycle for each PWM such that its value v_i has duty cycle (256-v_i)/256 and valid v_i values are 0 < v_i <= 255. Note that v_i=0 turns off PWM i.