commit | 1561f1af79740cf5c9ca413454d3fd6be0226304 | [log] [tgz] |
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author | james <james@neptune.cassia.ai> | Mon Dec 05 13:53:42 2022 -0800 |
committer | james <james@neptune.cassia.ai> | Mon Dec 05 13:53:42 2022 -0800 |
tree | f0da166f58bfe803bebcb2dad5aa70e73bc13246 | |
parent | 90f990d4a361e291e3b51bbdb5a37d7c2d6e2882 [diff] |
fix spdx
A basic pulse with modulation core with 8 PWMs controled by a wishbone bus slave interface. The PWMs are 8-bit programmable with full range of duty cycle control. All PWMS run synchronized to a single counter.
A simple pulse width modulator connected to a wishbone bus. Given an input clock signal, it is capable of dividing the signal by 2^n where 0 <= n < 24. This allows a 100MHz core fequency to be stepped down to just under 6 Hz if need be. The frequency of each PWM is individually controlled by the Divider registers which store the value n_i for PWM i. The Threshold register sets the duty cycle for each PWM such that its value v_i has duty cycle (256-v_i)/256 and valid v_i values are 0 < v_i <= 255. Note that v_i=0 turns off PWM i.