- status: 0 - openlane design prep
  runtime_s: 2.7
  runtime_ts: 0h0m2s702ms
- status: 1 - synthesis - yosys
  runtime_s: 3.26
  runtime_ts: 0h0m3s261ms
- status: 2 - sta - openroad
  runtime_s: 0.91
  runtime_ts: 0h0m0s912ms
- status: 3 - floorplan initialization - openroad
  runtime_s: 2.08
  runtime_ts: 0h0m2s81ms
- status: 4 - io_place - openlane
  runtime_s: 0.46
  runtime_ts: 0h0m0s464ms
- status: 5 - tap/decap insertion - openroad
  runtime_s: 1.06
  runtime_ts: 0h0m1s58ms
- status: 6 - pdn generation - openroad
  runtime_s: 1.19
  runtime_ts: 0h0m1s193ms
- status: 7 - global placement - openroad
  runtime_s: 3.38
  runtime_ts: 0h0m3s383ms
- status: 8 - resizer design optimizations - openroad
  runtime_s: 1.4
  runtime_ts: 0h0m1s401ms
- status: 9 - detailed placement - openroad
  runtime_s: 1.13
  runtime_ts: 0h0m1s132ms
- status: 10 - cts - openroad
  runtime_s: 38.79
  runtime_ts: 0h0m38s787ms
- status: 11 - resizer timing optimizations - openroad
  runtime_s: 1.33
  runtime_ts: 0h0m1s326ms
- status: 12 - resizer timing optimizations - openroad
  runtime_s: 1.44
  runtime_ts: 0h0m1s437ms
- status: 14 - detailed placement - openroad
  runtime_s: 1.14
  runtime_ts: 0h0m1s135ms
- status: 14 - diode insertion - openlane
  runtime_s: 1.26
  runtime_ts: 0h0m1s262ms
- status: 15 - fill insertion - openroad
  runtime_s: 1.34
  runtime_ts: 0h0m1s338ms
- status: 17 - write verilog - openroad
  runtime_s: 0.99
  runtime_ts: 0h0m0s991ms
- status: 17 - global routing - openroad
  runtime_s: 1.12
  runtime_ts: 0h0m1s125ms
- status: 18 - detailed_routing - openroad
  runtime_s: 14.84
  runtime_ts: 0h0m14s843ms
- status: 19 - wire lengths - openlane
  runtime_s: 0.48
  runtime_ts: 0h0m0s478ms
- status: 20 - parasitics extraction - openroad
  runtime_s: 1.05
  runtime_ts: 0h0m1s46ms
- status: 21 - sta - openroad
  runtime_s: 3.38
  runtime_ts: 0h0m3s382ms
- status: 22 - sta - openroad
  runtime_s: 1.35
  runtime_ts: 0h0m1s347ms
- status: 23 - gdsii - magic
  runtime_s: 3.38
  runtime_ts: 0h0m3s375ms
- status: 24 - spice extraction - magic
  runtime_s: 6.91
  runtime_ts: 0h0m6s910ms
- status: 26 - write verilog - openroad
  runtime_s: 1.06
  runtime_ts: 0h0m1s56ms
- status: 26 - write powered verilog - openlane
  runtime_s: 1.21
  runtime_ts: 0h0m1s209ms
- status: 27 - lvs - netgen
  runtime_s: 0.48
  runtime_ts: 0h0m0s476ms
- status: 28 - drc - magic
  runtime_s: 50.34
  runtime_ts: 0h0m50s335ms
- status: 29 - antenna check - openroad
  runtime_s: 1.04
  runtime_ts: 0h0m1s36ms
---
- status: routed
  runtime_s: 84.0
  runtime_ts: 0h1m24s0ms
- status: flow completed
  runtime_s: 155.0
  runtime_ts: 0h2m35s0ms