[INFO]: Run Directory: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22
[INFO]: Preparing LEF files for the nom corner...
[INFO]: Running Synthesis (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/synthesis/1-synthesis.log)...
[INFO]: Running Single-Corner Static Timing Analysis (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/synthesis/2-sta.log)...
[INFO]: Running Initial Floorplanning (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/floorplan/3-initial_fp.log)...
[INFO]: Floorplanned with width 886.48 and height 568.4.
[INFO]: Running IO Placement (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/floorplan/4-place_io.log)...
[INFO]: Running Tap/Decap Insertion (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/floorplan/5-tap.log)...
[INFO]: Power planning with power {vdd} and ground {vss}...
[INFO]: Generating PDN (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/floorplan/6-pdn.log)...
[INFO]: Running Global Placement (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/placement/7-global.log)...
[INFO]: Running Placement Resizer Design Optimizations (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/placement/8-resizer.log)...
[INFO]: Running Detailed Placement (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/placement/9-detailed.log)...
[INFO]: Running Clock Tree Synthesis (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/cts/10-cts.log)...
[INFO]: Running Placement Resizer Timing Optimizations (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/cts/11-resizer.log)...
[INFO]: Running Global Routing Resizer Timing Optimizations (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/12-resizer.log)...
[INFO]: Running Diode Insertion (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/13-diodes.log)...
[INFO]: Running Detailed Placement (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/14-diode_legalization.log)...
[INFO]: Running Fill Insertion (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/15-fill.log)...
[INFO]: Running Global Routing (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/16-global.log)...
[INFO]: Writing Verilog (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/16-global_write_netlist.log)...
[INFO]: Running Detailed Routing (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/18-detailed.log)...
[INFO]: No DRC violations after detailed routing.
[INFO]: Checking Wire Lengths (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/19-wire_lengths.log)...
[INFO]: Running SPEF Extraction at the nom process corner (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/20-parasitics_extraction.nom.log)...
[INFO]: Running Multi-Corner Static Timing Analysis at the nom process corner (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/21-rcx_mcsta.nom.log)...
[INFO]: Running Single-Corner Static Timing Analysis at the nom process corner (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/22-rcx_sta.log)...
[INFO]: Running Magic to generate various views...
[INFO]: Streaming out GDSII with Magic (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/23-gdsii.log)...
[INFO]: Generating MAGLEF views...
[INFO]: Running Magic Spice Export from LEF (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/24-spice.log)...
[INFO]: Writing Powered Verilog (logs: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/25-write_powered_def.log, ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/25-write_powered_verilog.log)...
[INFO]: Writing Verilog (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/25-write_powered_verilog.log)...
[INFO]: Running LVS (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/27-lvs.lef.log)...
[INFO]: Running Magic DRC (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/28-drc.log)...
[INFO]: Converting Magic DRC database to various tool-readable formats...
[INFO]: No DRC violations after GDS streaming out.
[INFO]: Running OpenROAD Antenna Rule Checker (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/29-antenna.log)...
[WARNING]: This PDK does not support the Circuit Validity Checker, skipping...
[INFO]: Saving current set of views in '../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/final'...
[INFO]: Saving current set of views in '../home/xb4syf/ASIC/gf180-demo'...
[INFO]: Saving runtime environment...
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at '../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/manufacturability.rpt'.
[INFO]: Created metrics report at '../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/metrics.csv'.
[WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff/22-rcx_sta.slew.rpt'.
[INFO]: There are no hold violations in the design at the typical corner.
[INFO]: There are no setup violations in the design at the typical corner.
[SUCCESS]: Flow complete.
[INFO]: Note that the following warnings have been generated: