diff --git a/openlane/user_project_wrapper/run/user_project_wrapper/OPENLANE_VERSION b/openlane/user_project_wrapper/run/user_project_wrapper/OPENLANE_VERSION
new file mode 100644
index 0000000..33889e4
--- /dev/null
+++ b/openlane/user_project_wrapper/run/user_project_wrapper/OPENLANE_VERSION
@@ -0,0 +1 @@
+OpenLane 235fa7a4a2872e779588919c58fc4fa32568e075
diff --git a/openlane/user_project_wrapper/run/user_project_wrapper/PDK_SOURCES b/openlane/user_project_wrapper/run/user_project_wrapper/PDK_SOURCES
new file mode 100644
index 0000000..c5eb502
--- /dev/null
+++ b/openlane/user_project_wrapper/run/user_project_wrapper/PDK_SOURCES
@@ -0,0 +1 @@
+open_pdks 35c7265f51749ad8d9fdbb575af22c7c8fab974e
diff --git a/openlane/user_project_wrapper/run/user_project_wrapper/cmds.log b/openlane/user_project_wrapper/run/user_project_wrapper/cmds.log
new file mode 100644
index 0000000..b461ed5
--- /dev/null
+++ b/openlane/user_project_wrapper/run/user_project_wrapper/cmds.log
@@ -0,0 +1,116 @@
+Mon Dec 05 16:20:13 UTC 2022 - Executing "/openlane/scripts/mergeLef.py -o /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/merged.nom.lef -i /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/lef/gf180mcu_fd_sc_mcu7t5v0.lef |& tee /dev/null"
+
+Mon Dec 05 16:20:13 UTC 2022 - Executing "/openlane/scripts/mergeLef.py -o /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/merged.nom.lef -i /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/merged.nom.lef /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/../../lef/plant_example.lef |& tee /dev/null"
+
+Mon Dec 05 16:20:13 UTC 2022 - Executing "python3 /openlane/scripts/mergeLib.py --output /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis/merged.lib --name gf180mcuC_merged /localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib"
+
+Mon Dec 05 16:20:14 UTC 2022 - Executing "python3 /openlane/scripts/libtrim.py --cell-file /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis/trimmed.lib.exclude.list --output /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis/trimmed.lib /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis/merged.lib"
+
+Mon Dec 05 16:20:14 UTC 2022 - Executing "python3 /openlane/scripts/libtrim.py --cell-file /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/cts/cts.lib.exclude.list --output /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/cts/cts.lib /localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib"
+
+Mon Dec 05 16:20:15 UTC 2022 - Executing "python3 /openlane/scripts/new_tracks.py -i /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info -o /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/routing/config.tracks"
+
+Mon Dec 05 16:20:15 UTC 2022 - Executing "echo {OpenLane 235fa7a4a2872e779588919c58fc4fa32568e075} > /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/OPENLANE_VERSION"
+
+Mon Dec 05 16:20:15 UTC 2022 - Executing "sed -E {s/^([[:space:]]+)pg_pin(.*)/\1pin\2\n\1    direction : "inout";/g} /localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib > /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis/1-gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.no_pg.lib"
+
+Mon Dec 05 16:20:15 UTC 2022 - Executing "sed -E {s/^([[:space:]]+)pg_pin(.*)/\1pin\2\n\1    direction : "inout";/g} /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis/trimmed.lib > /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis/1-trimmed.no_pg.lib"
+
+Mon Dec 05 16:20:16 UTC 2022 - Executing "yosys -c /openlane/scripts/yosys/elaborate.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/synthesis/1-synthesis.log"
+
+Mon Dec 05 16:20:16 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/xb4syf\/ASIC\/gf180-demo\/openlane\/user_project_wrapper\/runs\/22_12_05_11_20\/results\/synthesis\/user_project_wrapper.v/} /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/config.tcl"
+
+Mon Dec 05 16:20:16 UTC 2022 - Executing "sed -i /defparam/d /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/synthesis/user_project_wrapper.v"
+
+Mon Dec 05 16:20:17 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/sta.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/synthesis/2-sta.log"
+
+Mon Dec 05 16:20:18 UTC 2022 - Executing "sed -E {s/^([[:space:]]+)pg_pin(.*)/\1pin\2\n\1    direction : "inout";/g} /localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib > /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis/2-gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.no_pg.lib"
+
+Mon Dec 05 16:20:18 UTC 2022 - Executing "sed -E {s/^([[:space:]]+)pg_pin(.*)/\1pin\2\n\1    direction : "inout";/g} /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis/trimmed.lib > /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis/2-trimmed.no_pg.lib"
+
+Mon Dec 05 16:20:18 UTC 2022 - Executing "yosys -c /openlane/scripts/yosys/elaborate.tcl |& tee /dev/null /dev/null"
+
+Mon Dec 05 16:20:19 UTC 2022 - Executing "sed -i /defparam/d /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/synthesis/user_project_wrapper.v"
+
+Mon Dec 05 16:20:19 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/floorplan.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/floorplan/3-initial_fp.log"
+
+Mon Dec 05 16:20:20 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/floorplan.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/floorplan/3-initial_fp.log"
+
+Mon Dec 05 16:20:21 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/defutil.py extract_core_dims --output-data /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/dimensions.txt --input-lef /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/merged.nom.lef /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/floorplan/3-initial_fp.def"
+
+Mon Dec 05 16:20:22 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/io_place.py --config /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/pin_order.cfg --hor-layer Metal3 --ver-layer Metal2 --ver-width-mult 4 --hor-width-mult 4 --hor-extension 4.8 --ver-extension 4.8 --length 2.4 --unmatched-error --input-lef /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/merged.nom.lef --output-def /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/floorplan/4-io.def --output /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/floorplan/4-io.odb /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/floorplan/3-initial_fp.odb |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/floorplan/4-place_io.log"
+
+Mon Dec 05 16:20:23 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/manual_macro_place.py --config /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/placement/macro_placement.cfg --fixed --input-lef /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/merged.nom.lef --output-def /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/floorplan/4-io.macro_placement.def --output /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/floorplan/4-io.macro_placement.odb /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/floorplan/4-io.odb |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/placement/5-macro_placement.log"
+
+Mon Dec 05 16:20:23 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/pdn.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/floorplan/6-pdn.log"
+
+Mon Dec 05 16:20:24 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/random_place.py --input-lef /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/merged.nom.lef --output-def /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/placement/7-global.def --output /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/placement/7-global.odb /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/floorplan/6-pdn.odb |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/placement/7-global.log"
+
+Mon Dec 05 16:20:25 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/dpl.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/placement/8-detailed.log"
+
+Mon Dec 05 16:20:26 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/xb4syf\/ASIC\/gf180-demo\/openlane\/user_project_wrapper\/runs\/22_12_05_11_20\/results\/placement\/user_project_wrapper.nl.v/} /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/config.tcl"
+
+Mon Dec 05 16:20:26 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/resizer_routing_timing.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/routing/9-resizer.log"
+
+Mon Dec 05 16:20:29 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/xb4syf\/ASIC\/gf180-demo\/openlane\/user_project_wrapper\/runs\/22_12_05_11_20\/tmp\/9-user_project_wrapper.nl.v/} /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/config.tcl"
+
+Mon Dec 05 16:20:29 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/dpl.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/routing/10-diode_legalization.log"
+
+Mon Dec 05 16:20:30 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/xb4syf\/ASIC\/gf180-demo\/openlane\/user_project_wrapper\/runs\/22_12_05_11_20\/tmp\/routing\/diode.nl.v/} /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/config.tcl"
+
+Mon Dec 05 16:20:31 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/groute.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/routing/11-global.log"
+
+Mon Dec 05 16:20:33 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/write_views.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/routing/11-global_write_netlist.log"
+
+Mon Dec 05 16:20:34 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/xb4syf\/ASIC\/gf180-demo\/openlane\/user_project_wrapper\/runs\/22_12_05_11_20\/tmp\/routing\/global.nl.v/} /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/config.tcl"
+
+Mon Dec 05 16:20:35 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/droute.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/routing/13-detailed.log"
+
+Mon Dec 05 16:20:46 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/xb4syf\/ASIC\/gf180-demo\/openlane\/user_project_wrapper\/runs\/22_12_05_11_20\/results\/routing\/user_project_wrapper.nl.v/} /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/config.tcl"
+
+Mon Dec 05 16:20:46 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py tr to_klayout -o /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/routing/drt.klayout.xml --design-name user_project_wrapper /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/routing/drt.drc"
+
+Mon Dec 05 16:20:46 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/wire_lengths.py --report-out /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/routing/14-wire_lengths.csv --input-lef /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/merged.nom.lef --output-def /dev/null --output /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/routing/user_project_wrapper.odb /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/routing/user_project_wrapper.odb |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/routing/14-wire_lengths.log"
+
+Mon Dec 05 16:20:47 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/rcx.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/15-parasitics_extraction.nom.log"
+
+Mon Dec 05 16:20:48 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/sta_multi_corner.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/16-rcx_mcsta.nom.log"
+
+Mon Dec 05 16:20:51 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/sta.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/17-rcx_sta.log"
+
+Mon Dec 05 16:20:53 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/def/mag_gds.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/18-gdsii.log"
+
+Mon Dec 05 16:20:56 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/gds/mag_with_pointers.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/18-gds_ptrs.log"
+
+Mon Dec 05 16:20:58 UTC 2022 - Executing "sed -i -n {/^<< properties >>/,/^<< end >>/p} /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/signoff/gds_ptrs.mag"
+
+Mon Dec 05 16:20:58 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/mag/lef.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/18-lef.log"
+
+Mon Dec 05 16:20:59 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/lef/maglef.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/18-maglef.log"
+
+Mon Dec 05 16:21:00 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/extract_spice.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/19-spice.log"
+
+Mon Dec 05 16:21:04 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/power_utils.py write_powered_def --output /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/signoff/19-user_project_wrapper.p.def --input-lef /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/merged.nom.lef --power-port vdd --ground-port vss --powered-netlist /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis/pg_define.v /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/routing/user_project_wrapper.def |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/20-write_powered_def.log"
+
+Mon Dec 05 16:21:07 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/write_views.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/20-write_powered_verilog.log"
+
+Mon Dec 05 16:21:08 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/xb4syf\/ASIC\/gf180-demo\/openlane\/user_project_wrapper\/runs\/22_12_05_11_20\/tmp\/signoff\/19-user_project_wrapper.nl.v/} /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/config.tcl"
+
+Mon Dec 05 16:21:08 UTC 2022 - Executing "netgen -batch source /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/signoff/22-setup_file.lef.lvs |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/22-lvs.lef.log"
+
+Mon Dec 05 16:21:09 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/drc.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/23-drc.log"
+
+Mon Dec 05 16:22:04 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_tcl -o /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff/drc.tcl /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff/drc.rpt"
+
+Mon Dec 05 16:22:04 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_tr -o /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff/drc.tr /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff/drc.rpt"
+
+Mon Dec 05 16:22:04 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py tr to_klayout -o /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff/drc.klayout.xml --design-name user_project_wrapper /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff/drc.tr"
+
+Mon Dec 05 16:22:04 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_rdb -o /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff/drc.rdb /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff/drc.rpt"
+
+Mon Dec 05 16:22:05 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/antenna_check.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/24-antenna.log"
+
+Mon Dec 05 16:22:06 UTC 2022 - Executing "python3 /openlane/scripts/extract_antenna_violators.py --output /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff/24-antenna_violators.rpt /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/24-antenna.log"
+
+Mon Dec 05 16:22:07 UTC 2022 - Executing "python3 /openlane/scripts/generate_reports.py -d /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper --design_name user_project_wrapper --tag 22_12_05_11_20 --output_file /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/metrics.csv --man_report /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/manufacturability.rpt --run_path /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20"
+
diff --git a/openlane/user_project_wrapper/run/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/run/user_project_wrapper/config.tcl
new file mode 100644
index 0000000..3886209
--- /dev/null
+++ b/openlane/user_project_wrapper/run/user_project_wrapper/config.tcl
@@ -0,0 +1,739 @@
+# Run configs
+set ::env(PDK_ROOT) {/localtmp/asic/gf180/pdk/}
+set ::env(BASE_SDC_FILE) {/openlane/scripts/base.sdc}
+set ::env(BOTTOM_MARGIN_MULT) {4}
+set ::env(CARRY_SELECT_ADDER_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/csa_map.v}
+set ::env(CELLS_LEF) {/localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/lef/gf180mcu_fd_sc_mcu7t5v0.lef}
+set ::env(CELL_PAD_EXCLUDE) {gf180mcu_fd_sc_mcu7t5v0__filltie_* gf180mcu_fd_sc_mcu7t5v0__filldecap_* gf180mcu_fd_sc_mcu7t5v0__fill_* gf180mcu_fd_sc_mcu7t5v0__endcap_*}
+set ::env(CHECK_ASSIGN_STATEMENTS) {0}
+set ::env(CHECK_UNMAPPED_CELLS) {1}
+set ::env(CLOCK_BUFFER_FANOUT) {16}
+set ::env(CLOCK_NET) {plant_example_1.clk}
+set ::env(CLOCK_PERIOD) {50}
+set ::env(CLOCK_PORT) {user_clock2}
+set ::env(CLOCK_TREE_SYNTH) {0}
+set ::env(CLOCK_WIRE_RC_LAYER) {Metal4}
+set ::env(CONFIGS) {general.tcl checkers.tcl synthesis.tcl floorplan.tcl cts.tcl placement.tcl routing.tcl extraction.tcl}
+set ::env(CORE_AREA) {12 12 2968.2 2968.2}
+set ::env(CTS_CLK_BUFFER_LIST) {gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 gf180mcu_fd_sc_mcu7t5v0__clkbuf_8}
+set ::env(CTS_CLK_MAX_WIRE_LENGTH) {0}
+set ::env(CTS_DISABLE_POST_PROCESSING) {0}
+set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) {0}
+set ::env(CTS_MAX_CAP) {0.5}
+set ::env(CTS_REPORT_TIMING) {1}
+set ::env(CTS_ROOT_BUFFER) {gf180mcu_fd_sc_mcu7t5v0__clkbuf_16}
+set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) {50}
+set ::env(CTS_SINK_CLUSTERING_SIZE) {25}
+set ::env(CTS_TARGET_SKEW) {200}
+set ::env(CTS_TOLERANCE) {100}
+set ::env(DATA_WIRE_RC_LAYER) {Metal2}
+set ::env(DECAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__fillcap_*}
+set ::env(DEFAULT_MAX_TRAN) {3}
+set ::env(DEF_UNITS_PER_MICRON) {2000}
+set ::env(DESIGN_CONFIG) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/config.tcl}
+set ::env(DESIGN_IS_CORE) {1}
+set ::env(DESIGN_NAME) {user_project_wrapper}
+set ::env(DETAILED_ROUTER) {tritonroute}
+set ::env(DIE_AREA) {0 0 2980.2 2980.2}
+set ::env(DIODE_CELL) {gf180mcu_fd_sc_mcu7t5v0__antenna}
+set ::env(DIODE_CELL_PIN) {I}
+set ::env(DIODE_INSERTION_STRATEGY) {0}
+set ::env(DIODE_PADDING) {2}
+set ::env(DPL_CELL_PADDING) {2}
+set ::env(DRC_EXCLUDE_CELL_LIST) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
+set ::env(DRC_EXCLUDE_CELL_LIST_OPT) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
+set ::env(DRT_MIN_LAYER) {Metal1}
+set ::env(DRT_OPT_ITERS) {64}
+set ::env(ECO_ENABLE) {0}
+set ::env(ECO_FINISH) {0}
+set ::env(ECO_ITER) {0}
+set ::env(ECO_SKIP_PIN) {1}
+set ::env(EXTRA_GDS_FILES) { /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/../../gds/plant_example.gds}
+set ::env(EXTRA_LEFS) { /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/../../lef/plant_example.lef}
+set ::env(FILL_CELL) {gf180mcu_fd_sc_mcu7t5v0__fill_*}
+set ::env(FP_ASPECT_RATIO) {1}
+set ::env(FP_CORE_UTIL) {50}
+set ::env(FP_ENDCAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__endcap}
+set ::env(FP_IO_HEXTEND) {4.8}
+set ::env(FP_IO_HLAYER) {Metal3}
+set ::env(FP_IO_HLENGTH) {2.4}
+set ::env(FP_IO_HTHICKNESS_MULT) {4}
+set ::env(FP_IO_MIN_DISTANCE) {3}
+set ::env(FP_IO_MODE) {1}
+set ::env(FP_IO_UNMATCHED_ERROR) {1}
+set ::env(FP_IO_VEXTEND) {4.8}
+set ::env(FP_IO_VLAYER) {Metal2}
+set ::env(FP_IO_VLENGTH) {2.4}
+set ::env(FP_IO_VTHICKNESS_MULT) {4}
+set ::env(FP_PDN_AUTO_ADJUST) {1}
+set ::env(FP_PDN_CHECK_NODES) {0}
+set ::env(FP_PDN_CORE_RING) {1}
+set ::env(FP_PDN_CORE_RING_HOFFSET) {16}
+set ::env(FP_PDN_CORE_RING_HSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_HWIDTH) {3.1}
+set ::env(FP_PDN_CORE_RING_VOFFSET) {14}
+set ::env(FP_PDN_CORE_RING_VSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_VWIDTH) {3.1}
+set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) {1}
+set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
+set ::env(FP_PDN_ENABLE_RAILS) {0}
+set ::env(FP_PDN_HOFFSET) {5}
+set ::env(FP_PDN_HORIZONTAL_HALO) {10}
+set ::env(FP_PDN_HPITCH) {90}
+set ::env(FP_PDN_HPITCH_MULT) {1}
+set ::env(FP_PDN_HSPACING) {26.9}
+set ::env(FP_PDN_HWIDTH) {3.1}
+set ::env(FP_PDN_IRDROP) {1}
+set ::env(FP_PDN_LOWER_LAYER) {Metal4}
+set ::env(FP_PDN_MACRO_HOOKS) { plant_example_1 vdd vss vdd vss}
+set ::env(FP_PDN_RAILS_LAYER) {Metal1}
+set ::env(FP_PDN_RAIL_OFFSET) {0}
+set ::env(FP_PDN_RAIL_WIDTH) {0.6}
+set ::env(FP_PDN_SKIPTRIM) {0}
+set ::env(FP_PDN_UPPER_LAYER) {Metal5}
+set ::env(FP_PDN_VERTICAL_HALO) {10}
+set ::env(FP_PDN_VOFFSET) {5}
+set ::env(FP_PDN_VPITCH) {90}
+set ::env(FP_PDN_VSPACING) {15.5}
+set ::env(FP_PDN_VWIDTH) {3.1}
+set ::env(FP_PIN_ORDER_CFG) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/pin_order.cfg}
+set ::env(FP_SIZING) {absolute}
+set ::env(FP_TAPCELL_DIST) {20}
+set ::env(FP_TAP_HORIZONTAL_HALO) {10}
+set ::env(FP_TAP_VERTICAL_HALO) {10}
+set ::env(FP_WELLTAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__filltie}
+set ::env(FULL_ADDER_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/fa_map.v}
+set ::env(GDS_FILES) {/localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/gds/gf180mcu_fd_sc_mcu7t5v0.gds}
+set ::env(GENERATE_FINAL_SUMMARY_REPORT) {1}
+set ::env(GLB_CFG_FILE) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/config.tcl}
+set ::env(GLB_OPTIMIZE_MIRRORING) {1}
+set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) {0}
+set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
+set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) {0.05}
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {10}
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {10}
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {0}
+set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
+set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) {0.025}
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(GLOBAL_ROUTER) {fastroute}
+set ::env(GND_NETS) {vss}
+set ::env(GND_PIN) {VSS}
+set ::env(GPIO_PADS_LEF) { /localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_io/lef/GF018green_ipio_5p0c_75_5lm.lef
+}
+set ::env(GPIO_PADS_VERILOG) { /localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_io/verilog/GF018green_ipio_5p0c_75_5lm.v
+}
+set ::env(GPL_CELL_PADDING) {0}
+set ::env(GRT_ADJUSTMENT) {0.3}
+set ::env(GRT_ALLOW_CONGESTION) {0}
+set ::env(GRT_ANT_ITERS) {3}
+set ::env(GRT_ESTIMATE_PARASITICS) {1}
+set ::env(GRT_LAYER_ADJUSTMENTS) {0,0,0,0,0}
+set ::env(GRT_MACRO_EXTENSION) {0}
+set ::env(GRT_MAX_DIODE_INS_ITERS) {1}
+set ::env(GRT_OVERFLOW_ITERS) {50}
+set ::env(IO_PCT) {0.2}
+set ::env(KLAYOUT_DRC_KLAYOUT_GDS) {0}
+set ::env(KLAYOUT_DRC_TECH_SCRIPT) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/klayout/gf180mcuC_mr.drc}
+set ::env(KLAYOUT_PROPERTIES) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/klayout/gf180mcuC.lyp}
+set ::env(KLAYOUT_TECH) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/klayout/gf180mcuC.lyt}
+set ::env(KLAYOUT_XOR_GDS) {1}
+set ::env(KLAYOUT_XOR_XML) {1}
+set ::env(LEC_ENABLE) {0}
+set ::env(LEFT_MARGIN_MULT) {12}
+set ::env(LIB_FASTEST) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ff_n40C_5v50.lib}
+set ::env(LIB_SLOWEST) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ss_125C_4v50.lib}
+set ::env(LIB_SYNTH) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(LIB_TYPICAL) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(LOGS_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs}
+set ::env(LVS_CONNECT_BY_LABEL) {0}
+set ::env(LVS_INSERT_POWER_PINS) {1}
+set ::env(MACRO_BLOCKAGES_LAYER) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(MACRO_PLACEMENT_CFG) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/macro.cfg}
+set ::env(MAGIC_CONVERT_DRC_TO_RDB) {1}
+set ::env(MAGIC_DEF_LABELS) {1}
+set ::env(MAGIC_DEF_NO_BLOCKAGES) {1}
+set ::env(MAGIC_DISABLE_HIER_GDS) {1}
+set ::env(MAGIC_DRC_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
+set ::env(MAGIC_GENERATE_GDS) {1}
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_GENERATE_MAGLEF) {1}
+set ::env(MAGIC_INCLUDE_GDS_POINTERS) {0}
+set ::env(MAGIC_MAGICRC) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc}
+set ::env(MAGIC_PAD) {0}
+set ::env(MAGIC_TECH_FILE) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.tech}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+set ::env(MAGIC_ZEROIZE_ORIGIN) {0}
+set ::env(METAL_LAYER_NAMES) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(NETGEN_SETUP_FILE) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/netgen/gf180mcuC_setup.tcl}
+set ::env(NO_SYNTH_CELL_LIST) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells}
+set ::env(OPENLANE_VERBOSE) {0}
+set ::env(PDKPATH) {/localtmp/asic/gf180/pdk//gf180mcuC}
+set ::env(PDN_CFG) {/openlane/scripts/openroad/common/pdn_cfg.tcl}
+set ::env(PLACE_SITE) {GF018hv5v_mcu_sc7}
+set ::env(PLACE_SITE_HEIGHT) {3.92}
+set ::env(PLACE_SITE_WIDTH) {0.56}
+set ::env(PL_BASIC_PLACEMENT) {0}
+set ::env(PL_ESTIMATE_PARASITICS) {1}
+set ::env(PL_LIB) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(PL_MACRO_CHANNEL) {0 0}
+set ::env(PL_MACRO_HALO) {0 0}
+set ::env(PL_MAX_DISPLACEMENT_X) {500}
+set ::env(PL_MAX_DISPLACEMENT_Y) {100}
+set ::env(PL_OPTIMIZE_MIRRORING) {1}
+set ::env(PL_RANDOM_GLB_PLACEMENT) {1}
+set ::env(PL_RANDOM_INITIAL_PLACEMENT) {0}
+set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) {0}
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {0}
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {0}
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {0}
+set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) {0.1}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {20}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {20}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {0}
+set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) {1}
+set ::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
+set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) {0.05}
+set ::env(PL_RESIZER_TIE_SEPERATION) {0}
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {0}
+set ::env(PL_ROUTABILITY_DRIVEN) {1}
+set ::env(PL_SKIP_INITIAL_PLACEMENT) {0}
+set ::env(PL_TARGET_DENSITY) {0.55}
+set ::env(PL_TIME_DRIVEN) {1}
+set ::env(PRIMARY_SIGNOFF_TOOL) {magic}
+set ::env(PROCESS) {180}
+set ::env(QUIT_ON_HOLD_VIOLATIONS) {1}
+set ::env(QUIT_ON_ILLEGAL_OVERLAPS) {1}
+set ::env(QUIT_ON_LONG_WIRE) {0}
+set ::env(QUIT_ON_LVS_ERROR) {1}
+set ::env(QUIT_ON_MAGIC_DRC) {1}
+set ::env(QUIT_ON_SETUP_VIOLATIONS) {1}
+set ::env(QUIT_ON_TIMING_VIOLATIONS) {1}
+set ::env(QUIT_ON_TR_DRC) {1}
+set ::env(RCX_CC_MODEL) {10}
+set ::env(RCX_CONTEXT_DEPTH) {5}
+set ::env(RCX_CORNER_COUNT) {1}
+set ::env(RCX_COUPLING_THRESHOLD) {0.1}
+set ::env(RCX_MAX_RESISTANCE) {50}
+set ::env(RCX_MERGE_VIA_WIRE_RES) {1}
+set ::env(RCX_RULES) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.nom}
+set ::env(RCX_RULES_MAX) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.max}
+set ::env(RCX_RULES_MIN) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.min}
+set ::env(REPORTS_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports}
+set ::env(RESULTS_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results}
+set ::env(RIGHT_MARGIN_MULT) {12}
+set ::env(RIPPLE_CARRY_ADDER_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/rca_map.v}
+set ::env(ROUTING_CORES) {2}
+set ::env(RSZ_DONT_TOUCH_RX) {$^}
+set ::env(RSZ_USE_OLD_REMOVER) {0}
+set ::env(RT_MAX_LAYER) {Metal4}
+set ::env(RT_MIN_LAYER) {Metal2}
+set ::env(RUN_CVC) {0}
+set ::env(RUN_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20}
+set ::env(RUN_DRT) {1}
+set ::env(RUN_FILL_INSERTION) {0}
+set ::env(RUN_IRDROP_REPORT) {0}
+set ::env(RUN_KLAYOUT) {0}
+set ::env(RUN_KLAYOUT_DRC) {0}
+set ::env(RUN_KLAYOUT_XOR) {0}
+set ::env(RUN_LVS) {1}
+set ::env(RUN_MAGIC) {1}
+set ::env(RUN_MAGIC_DRC) {1}
+set ::env(RUN_SPEF_EXTRACTION) {1}
+set ::env(RUN_TAG) {22_12_05_11_20}
+set ::env(RUN_TAP_DECAP_INSERTION) {0}
+set ::env(SCLPATH) {/localtmp/asic/gf180/pdk//gf180mcuC/gf180mcu_fd_sc_mcu7t5v0}
+set ::env(SPEF_EXTRACTOR) {openrcx}
+set ::env(START_TIME) {2022.12.05_16.20.12}
+set ::env(STA_REPORT_POWER) {1}
+set ::env(STA_WRITE_LIB) {1}
+set ::env(STD_CELL_GROUND_PINS) {VSS}
+set ::env(STD_CELL_LIBRARY) {gf180mcu_fd_sc_mcu7t5v0}
+set ::env(STD_CELL_LIBRARY_CDL) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/cdl/gf180mcu_fd_sc_mcu7t5v0.cdl}
+set ::env(STD_CELL_LIBRARY_OPT) {gf180mcu_fd_sc_mcu7t5v0}
+set ::env(STD_CELL_POWER_PINS) {VDD}
+set ::env(SYNTH_ADDER_TYPE) {YOSYS}
+set ::env(SYNTH_BIN) {yosys}
+set ::env(SYNTH_BUFFERING) {1}
+set ::env(SYNTH_CAP_LOAD) {72.91}
+set ::env(SYNTH_CLK_DRIVING_CELL) {gf180mcu_fd_sc_mcu7t5v0__inv_4}
+set ::env(SYNTH_CLK_DRIVING_CELL_PIN) {ZN}
+set ::env(SYNTH_CLOCK_TRANSITION) {0.15}
+set ::env(SYNTH_CLOCK_UNCERTAINTY) {0.25}
+set ::env(SYNTH_DRIVING_CELL) {gf180mcu_fd_sc_mcu7t5v0__inv_1}
+set ::env(SYNTH_DRIVING_CELL_PIN) {ZN}
+set ::env(SYNTH_ELABORATE_ONLY) {1}
+set ::env(SYNTH_EXTRA_MAPPING_FILE) {}
+set ::env(SYNTH_FLAT_TOP) {0}
+set ::env(SYNTH_LATCH_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/latch_map.v}
+set ::env(SYNTH_MAX_FANOUT) {10}
+set ::env(SYNTH_MIN_BUF_PORT) {gf180mcu_fd_sc_mcu7t5v0__buf_1 I Z}
+set ::env(SYNTH_NO_FLAT) {0}
+set ::env(SYNTH_READ_BLACKBOX_LIB) {0}
+set ::env(SYNTH_SCRIPT) {/openlane/scripts/yosys/synth.tcl}
+set ::env(SYNTH_SHARE_RESOURCES) {1}
+set ::env(SYNTH_SIZING) {0}
+set ::env(SYNTH_STRATEGY) {AREA 0}
+set ::env(SYNTH_TIEHI_PORT) {gf180mcu_fd_sc_mcu7t5v0__tieh Z}
+set ::env(SYNTH_TIELO_PORT) {gf180mcu_fd_sc_mcu7t5v0__tiel ZN}
+set ::env(SYNTH_TIMING_DERATE) {0.05}
+set ::env(SYNTH_USE_PG_PINS_DEFINES) {USE_POWER_PINS}
+set ::env(TAKE_LAYOUT_SCROT) {0}
+set ::env(TECH_LEF) {/localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef}
+set ::env(TERMINAL_OUTPUT) {/dev/null}
+set ::env(TMP_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp}
+set ::env(TOP_MARGIN_MULT) {4}
+set ::env(TRACKS_INFO_FILE) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info}
+set ::env(TRISTATE_BUFFER_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tribuff_map.v}
+set ::env(USE_ARC_ANTENNA_CHECK) {1}
+set ::env(USE_GPIO_PADS) {0}
+set ::env(VDD_NETS) {vdd}
+set ::env(VDD_PIN) {VDD}
+set ::env(VERILOG_FILES) { /home/xb4syf/ASIC/gf180-demo/caravel/verilog/rtl/defines.v  /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v}
+set ::env(VERILOG_FILES_BLACKBOX) { /home/xb4syf/ASIC/gf180-demo/caravel/verilog/rtl/defines.v  /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/../../verilog/rtl/plant_example.v}
+set ::env(WIRE_RC_LAYER) {Metal2}
+set ::env(YOSYS_REWRITE_VERILOG) {0}
+set ::env(cts_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/cts}
+set ::env(cts_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/cts}
+set ::env(cts_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/cts}
+set ::env(cts_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/cts}
+set ::env(eco_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/eco}
+set ::env(eco_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/eco}
+set ::env(eco_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/eco}
+set ::env(eco_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/eco}
+set ::env(floorplan_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/floorplan}
+set ::env(floorplan_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/floorplan}
+set ::env(floorplan_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/floorplan}
+set ::env(floorplan_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/floorplan}
+set ::env(placement_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/placement}
+set ::env(placement_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/placement}
+set ::env(placement_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/placement}
+set ::env(placement_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/placement}
+set ::env(routing_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/routing}
+set ::env(routing_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/routing}
+set ::env(routing_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/routing}
+set ::env(routing_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/routing}
+set ::env(signoff_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff}
+set ::env(signoff_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff}
+set ::env(signoff_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/signoff}
+set ::env(signoff_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/signoff}
+set ::env(synthesis_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/synthesis}
+set ::env(synthesis_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/synthesis}
+set ::env(synthesis_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/synthesis}
+set ::env(synthesis_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis}
+set ::env(SYNTH_MAX_TRAN) {3}
+set ::env(CURRENT_INDEX) 24
+set ::env(CURRENT_DEF) /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/routing/user_project_wrapper.def
+set ::env(CURRENT_GUIDE) /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/routing/11-global.guide
+set ::env(CURRENT_NETLIST) /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/signoff/19-user_project_wrapper.nl.v
+set ::env(CURRENT_POWERED_NETLIST) {0}
+set ::env(CURRENT_ODB) /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/routing/user_project_wrapper.odb
+set ::env(PDK_ROOT) {/localtmp/asic/gf180/pdk/}
+set ::env(ANTENNA_CHECK_CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/signoff/19-user_project_wrapper.p.def}
+set ::env(ANTENNA_VIOLATOR_LIST) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff/24-antenna_violators.rpt}
+set ::env(BASE_SDC_FILE) {/openlane/scripts/base.sdc}
+set ::env(BASIC_PREP_COMPLETE) {1}
+set ::env(BOTTOM_MARGIN_MULT) {4}
+set ::env(CARAVEL_ROOT) {/home/xb4syf/ASIC/gf180-demo/caravel}
+set ::env(CARRY_SELECT_ADDER_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/csa_map.v}
+set ::env(CELLS_LEF) {/localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/lef/gf180mcu_fd_sc_mcu7t5v0.lef}
+set ::env(CELL_PAD_EXCLUDE) {gf180mcu_fd_sc_mcu7t5v0__filltie_* gf180mcu_fd_sc_mcu7t5v0__filldecap_* gf180mcu_fd_sc_mcu7t5v0__fill_* gf180mcu_fd_sc_mcu7t5v0__endcap_*}
+set ::env(CHECK_ASSIGN_STATEMENTS) {0}
+set ::env(CHECK_UNMAPPED_CELLS) {1}
+set ::env(CLOCK_BUFFER_FANOUT) {16}
+set ::env(CLOCK_NET) {plant_example_1.clk}
+set ::env(CLOCK_PERIOD) {50}
+set ::env(CLOCK_PORT) {user_clock2}
+set ::env(CLOCK_TREE_SYNTH) {0}
+set ::env(CLOCK_WIRE_RC_LAYER) {Metal4}
+set ::env(CONFIGS) {general.tcl checkers.tcl synthesis.tcl floorplan.tcl cts.tcl placement.tcl routing.tcl extraction.tcl}
+set ::env(CORE_AREA) {12.32 15.68 2968.0 2967.44}
+set ::env(CORE_HEIGHT) {2951.76}
+set ::env(CORE_WIDTH) {2955.68}
+set ::env(CTS_CLK_BUFFER_LIST) {gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 gf180mcu_fd_sc_mcu7t5v0__clkbuf_8}
+set ::env(CTS_CLK_MAX_WIRE_LENGTH) {0}
+set ::env(CTS_CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/placement/user_project_wrapper.def}
+set ::env(CTS_DISABLE_POST_PROCESSING) {0}
+set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) {0}
+set ::env(CTS_MAX_CAP) {0.5}
+set ::env(CTS_REPORT_TIMING) {1}
+set ::env(CTS_ROOT_BUFFER) {gf180mcu_fd_sc_mcu7t5v0__clkbuf_16}
+set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) {50}
+set ::env(CTS_SINK_CLUSTERING_SIZE) {25}
+set ::env(CTS_TARGET_SKEW) {200}
+set ::env(CTS_TOLERANCE) {100}
+set ::env(CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/signoff/19-user_project_wrapper.p.def}
+set ::env(CURRENT_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/routing}
+set ::env(CURRENT_GDS) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/signoff/user_project_wrapper.gds}
+set ::env(CURRENT_GUIDE) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/routing/11-global.guide}
+set ::env(CURRENT_INDEX) {24}
+set ::env(CURRENT_LIB) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/routing/mca/process_corner_nom/user_project_wrapper.lib}
+set ::env(CURRENT_NETLIST) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/signoff/19-user_project_wrapper.nl.v}
+set ::env(CURRENT_ODB) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/routing/user_project_wrapper.odb}
+set ::env(CURRENT_POWERED_NETLIST) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/signoff/19-user_project_wrapper.pnl.v}
+set ::env(CURRENT_SDC) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/9-user_project_wrapper.sdc}
+set ::env(CURRENT_SDF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/routing/mca/process_corner_nom/user_project_wrapper.sdf}
+set ::env(CURRENT_SPEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/routing/mca/process_corner_nom/user_project_wrapper.spef}
+set ::env(CURRENT_STEP) {}
+set ::env(DATA_WIRE_RC_LAYER) {Metal2}
+set ::env(DECAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__fillcap_*}
+set ::env(DEFAULT_MAX_TRAN) {3}
+set ::env(DEF_UNITS_PER_MICRON) {2000}
+set ::env(DESIGN_CONFIG) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/config.tcl}
+set ::env(DESIGN_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper}
+set ::env(DESIGN_IS_CORE) {1}
+set ::env(DESIGN_NAME) {user_project_wrapper}
+set ::env(DETAILED_ROUTER) {tritonroute}
+set ::env(DIE_AREA) {0.0 0.0 2980.2 2980.2}
+set ::env(DIODE_CELL) {gf180mcu_fd_sc_mcu7t5v0__antenna}
+set ::env(DIODE_CELL_PIN) {I}
+set ::env(DIODE_INSERTION_CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/routing/user_project_wrapper.def}
+set ::env(DIODE_INSERTION_STRATEGY) {0}
+set ::env(DIODE_PADDING) {2}
+set ::env(DONT_USE_CELLS) {gf180mcu_fd_sc_mcu7t5v0__mux2_1 gf180mcu_fd_sc_mcu7t5v0__oai33_2 }
+set ::env(DPL_CELL_PADDING) {2}
+set ::env(DRC_CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/signoff/19-user_project_wrapper.p.def}
+set ::env(DRC_EXCLUDE_CELL_LIST) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
+set ::env(DRC_EXCLUDE_CELL_LIST_OPT) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
+set ::env(DRT_MIN_LAYER) {Metal1}
+set ::env(DRT_OPT_ITERS) {64}
+set ::env(ECO_ENABLE) {0}
+set ::env(ECO_FINISH) {0}
+set ::env(ECO_ITER) {0}
+set ::env(ECO_SKIP_PIN) {1}
+set ::env(EXTRA_GDS_FILES) { /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/../../gds/plant_example.gds}
+set ::env(EXTRA_LEFS) { /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/../../lef/plant_example.lef}
+set ::env(EXT_NETLIST) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/signoff/user_project_wrapper.spice}
+set ::env(FILL_CELL) {gf180mcu_fd_sc_mcu7t5v0__fill_*}
+set ::env(FP_ASPECT_RATIO) {1}
+set ::env(FP_CORE_UTIL) {50}
+set ::env(FP_ENDCAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__endcap}
+set ::env(FP_IO_HEXTEND) {4.8}
+set ::env(FP_IO_HLAYER) {Metal3}
+set ::env(FP_IO_HLENGTH) {2.4}
+set ::env(FP_IO_HTHICKNESS_MULT) {4}
+set ::env(FP_IO_MIN_DISTANCE) {3}
+set ::env(FP_IO_MODE) {1}
+set ::env(FP_IO_UNMATCHED_ERROR) {1}
+set ::env(FP_IO_VEXTEND) {4.8}
+set ::env(FP_IO_VLAYER) {Metal2}
+set ::env(FP_IO_VLENGTH) {2.4}
+set ::env(FP_IO_VTHICKNESS_MULT) {4}
+set ::env(FP_PDN_AUTO_ADJUST) {1}
+set ::env(FP_PDN_CHECK_NODES) {0}
+set ::env(FP_PDN_CORE_RING) {1}
+set ::env(FP_PDN_CORE_RING_HOFFSET) {16}
+set ::env(FP_PDN_CORE_RING_HSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_HWIDTH) {3.1}
+set ::env(FP_PDN_CORE_RING_VOFFSET) {14}
+set ::env(FP_PDN_CORE_RING_VSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_VWIDTH) {3.1}
+set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) {1}
+set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
+set ::env(FP_PDN_ENABLE_RAILS) {0}
+set ::env(FP_PDN_HOFFSET) {5}
+set ::env(FP_PDN_HORIZONTAL_HALO) {10}
+set ::env(FP_PDN_HPITCH) {90}
+set ::env(FP_PDN_HPITCH_MULT) {1}
+set ::env(FP_PDN_HSPACING) {26.9}
+set ::env(FP_PDN_HWIDTH) {3.1}
+set ::env(FP_PDN_IRDROP) {1}
+set ::env(FP_PDN_LOWER_LAYER) {Metal4}
+set ::env(FP_PDN_MACRO_HOOKS) { plant_example_1 vdd vss vdd vss}
+set ::env(FP_PDN_RAILS_LAYER) {Metal1}
+set ::env(FP_PDN_RAIL_OFFSET) {0}
+set ::env(FP_PDN_RAIL_WIDTH) {0.6}
+set ::env(FP_PDN_SKIPTRIM) {0}
+set ::env(FP_PDN_UPPER_LAYER) {Metal5}
+set ::env(FP_PDN_VERTICAL_HALO) {10}
+set ::env(FP_PDN_VOFFSET) {5}
+set ::env(FP_PDN_VPITCH) {90}
+set ::env(FP_PDN_VSPACING) {15.5}
+set ::env(FP_PDN_VWIDTH) {3.1}
+set ::env(FP_PIN_ORDER_CFG) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/pin_order.cfg}
+set ::env(FP_SIZING) {absolute}
+set ::env(FP_TAPCELL_DIST) {20}
+set ::env(FP_TAP_HORIZONTAL_HALO) {10}
+set ::env(FP_TAP_VERTICAL_HALO) {10}
+set ::env(FP_WELLTAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__filltie}
+set ::env(FULL_ADDER_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/fa_map.v}
+set ::env(GDS_FILES) {/localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/gds/gf180mcu_fd_sc_mcu7t5v0.gds}
+set ::env(GENERATE_FINAL_SUMMARY_REPORT) {1}
+set ::env(GLB_CFG_FILE) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/config.tcl}
+set ::env(GLB_OPTIMIZE_MIRRORING) {1}
+set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) {0}
+set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
+set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) {0.05}
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {10}
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {10}
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {0}
+set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
+set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) {0.025}
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(GLOBAL_ROUTER) {fastroute}
+set ::env(GND_NET) {vss}
+set ::env(GND_NETS) {vss}
+set ::env(GND_PIN) {vss}
+set ::env(GPIO_PADS_LEF) { /localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_io/lef/GF018green_ipio_5p0c_75_5lm.lef
+}
+set ::env(GPIO_PADS_VERILOG) { /localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_io/verilog/GF018green_ipio_5p0c_75_5lm.v
+}
+set ::env(GPL_CELL_PADDING) {0}
+set ::env(GRT_ADJUSTMENT) {0.3}
+set ::env(GRT_ALLOW_CONGESTION) {0}
+set ::env(GRT_ANT_ITERS) {3}
+set ::env(GRT_ESTIMATE_PARASITICS) {1}
+set ::env(GRT_LAYER_ADJUSTMENTS) {0,0,0,0,0}
+set ::env(GRT_MACRO_EXTENSION) {0}
+set ::env(GRT_MAX_DIODE_INS_ITERS) {1}
+set ::env(GRT_OVERFLOW_ITERS) {50}
+set ::env(HOME) {/}
+set ::env(HOSTNAME) {27ea051f9351}
+set ::env(IO_PCT) {0.2}
+set ::env(KLAYOUT_DRC_KLAYOUT_GDS) {0}
+set ::env(KLAYOUT_DRC_TECH_SCRIPT) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/klayout/gf180mcuC_mr.drc}
+set ::env(KLAYOUT_PROPERTIES) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/klayout/gf180mcuC.lyp}
+set ::env(KLAYOUT_TECH) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/klayout/gf180mcuC.lyt}
+set ::env(KLAYOUT_XOR_GDS) {1}
+set ::env(KLAYOUT_XOR_XML) {1}
+set ::env(LANG) {en_US.UTF-8}
+set ::env(LAST_TIMING_REPORT_TAG) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff/17-rcx_sta}
+set ::env(LC_ALL) {en_US.UTF-8}
+set ::env(LC_CTYPE) {en_US.UTF-8}
+set ::env(LD_LIBRARY_PATH) {/build//lib:/build//lib/Linux-x86_64:}
+set ::env(LEC_ENABLE) {0}
+set ::env(LEFT_MARGIN_MULT) {12}
+set ::env(LIB_CTS) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/cts/cts.lib}
+set ::env(LIB_FASTEST) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ff_n40C_5v50.lib}
+set ::env(LIB_SLOWEST) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ss_125C_4v50.lib}
+set ::env(LIB_SYNTH) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis/trimmed.lib}
+set ::env(LIB_SYNTH_COMPLETE) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(LIB_SYNTH_COMPLETE_NO_PG) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis/2-gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.no_pg.lib}
+set ::env(LIB_SYNTH_MERGED) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis/merged.lib}
+set ::env(LIB_SYNTH_NO_PG) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis/2-trimmed.no_pg.lib}
+set ::env(LIB_TYPICAL) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(LOGS_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs}
+set ::env(LVS_CONNECT_BY_LABEL) {0}
+set ::env(LVS_CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/routing/user_project_wrapper.def}
+set ::env(LVS_INSERT_POWER_PINS) {1}
+set ::env(MACRO_BLOCKAGES_LAYER) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(MACRO_PLACEMENT_CFG) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/macro.cfg}
+set ::env(MAGIC_CONVERT_DRC_TO_RDB) {1}
+set ::env(MAGIC_DEF_LABELS) {1}
+set ::env(MAGIC_DEF_NO_BLOCKAGES) {1}
+set ::env(MAGIC_DISABLE_HIER_GDS) {1}
+set ::env(MAGIC_DRC_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
+set ::env(MAGIC_GDS) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/signoff/user_project_wrapper.magic.gds}
+set ::env(MAGIC_GENERATE_GDS) {1}
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_GENERATE_MAGLEF) {1}
+set ::env(MAGIC_INCLUDE_GDS_POINTERS) {0}
+set ::env(MAGIC_MAGICRC) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc}
+set ::env(MAGIC_PAD) {0}
+set ::env(MAGIC_TECH_FILE) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.tech}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+set ::env(MAGIC_ZEROIZE_ORIGIN) {0}
+set ::env(MAGTYPE) {maglef}
+set ::env(MANPATH) {/build//share/man:}
+set ::env(MAX_METAL_LAYER) {5}
+set ::env(MCW_ROOT) {/home/xb4syf/ASIC/gf180-demo/mgmt_core_wrapper}
+set ::env(MC_SDF_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/routing/mca/sdf}
+set ::env(MC_SPEF_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/routing/mca/spef}
+set ::env(MERGED_LEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/merged.nom.lef}
+set ::env(METAL_LAYER_NAMES) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(MISMATCHES_OK) {1}
+set ::env(NETGEN_SETUP_FILE) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/netgen/gf180mcuC_setup.tcl}
+set ::env(NO_SYNTH_CELL_LIST) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells}
+set ::env(OPENLANE_ROOT) {/openlane}
+set ::env(OPENLANE_RUN_TAG) {22_12_05_11_20}
+set ::env(OPENLANE_VERBOSE) {0}
+set ::env(OPENLANE_VERSION) {235fa7a4a2872e779588919c58fc4fa32568e075}
+set ::env(OPENROAD) {/build/}
+set ::env(OPENROAD_BIN) {openroad}
+set ::env(PARSITICS_CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/routing/user_project_wrapper.def}
+set ::env(PATH) {/openlane:/openlane/scripts:/build//bin:/build//bin/Linux-x86_64:/build//pdn/scripts:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin}
+set ::env(PDK) {gf180mcuC}
+set ::env(PDKPATH) {/localtmp/asic/gf180/pdk//gf180mcuC}
+set ::env(PDK_ROOT) {/localtmp/asic/gf180/pdk/}
+set ::env(PDN_CFG) {/openlane/scripts/openroad/common/pdn_cfg.tcl}
+set ::env(PLACEMENT_CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/floorplan/6-pdn.def}
+set ::env(PLACE_SITE) {GF018hv5v_mcu_sc7}
+set ::env(PLACE_SITE_HEIGHT) {3.92}
+set ::env(PLACE_SITE_WIDTH) {0.56}
+set ::env(PL_BASIC_PLACEMENT) {0}
+set ::env(PL_ESTIMATE_PARASITICS) {1}
+set ::env(PL_INIT_COEFF) {0.00002}
+set ::env(PL_IO_ITER) {5}
+set ::env(PL_LIB) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(PL_MACRO_CHANNEL) {0 0}
+set ::env(PL_MACRO_HALO) {0 0}
+set ::env(PL_MAX_DISPLACEMENT_X) {500}
+set ::env(PL_MAX_DISPLACEMENT_Y) {100}
+set ::env(PL_OPTIMIZE_MIRRORING) {1}
+set ::env(PL_RANDOM_GLB_PLACEMENT) {1}
+set ::env(PL_RANDOM_INITIAL_PLACEMENT) {0}
+set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) {0}
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {0}
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {0}
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {0}
+set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) {0.1}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {20}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {20}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {0}
+set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) {1}
+set ::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
+set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) {0.05}
+set ::env(PL_RESIZER_TIE_SEPERATION) {0}
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {0}
+set ::env(PL_ROUTABILITY_DRIVEN) {1}
+set ::env(PL_SKIP_INITIAL_PLACEMENT) {0}
+set ::env(PL_TARGET_DENSITY) {0.55}
+set ::env(PL_TIME_DRIVEN) {1}
+set ::env(PRIMARY_SIGNOFF_TOOL) {magic}
+set ::env(PROCESS) {180}
+set ::env(PWD) {/openlane}
+set ::env(QUIT_ON_HOLD_VIOLATIONS) {1}
+set ::env(QUIT_ON_ILLEGAL_OVERLAPS) {1}
+set ::env(QUIT_ON_LONG_WIRE) {0}
+set ::env(QUIT_ON_LVS_ERROR) {1}
+set ::env(QUIT_ON_MAGIC_DRC) {1}
+set ::env(QUIT_ON_SETUP_VIOLATIONS) {1}
+set ::env(QUIT_ON_TIMING_VIOLATIONS) {1}
+set ::env(QUIT_ON_TR_DRC) {1}
+set ::env(RCX_CC_MODEL) {10}
+set ::env(RCX_CONTEXT_DEPTH) {5}
+set ::env(RCX_CORNER_COUNT) {1}
+set ::env(RCX_COUPLING_THRESHOLD) {0.1}
+set ::env(RCX_MAX_RESISTANCE) {50}
+set ::env(RCX_MERGE_VIA_WIRE_RES) {1}
+set ::env(RCX_RULES) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.nom}
+set ::env(RCX_RULES_MAX) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.max}
+set ::env(RCX_RULES_MIN) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.min}
+set ::env(RCX_SDC_FILE) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/9-user_project_wrapper.sdc}
+set ::env(REPORTS_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports}
+set ::env(RESULTS_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results}
+set ::env(RIGHT_MARGIN_MULT) {12}
+set ::env(RIPPLE_CARRY_ADDER_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/rca_map.v}
+set ::env(ROUTING_CORES) {2}
+set ::env(ROUTING_CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/placement/user_project_wrapper.def}
+set ::env(RSZ_DONT_TOUCH_RX) {\$^}
+set ::env(RSZ_LIB) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis/resizer_gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(RSZ_USE_OLD_REMOVER) {0}
+set ::env(RT_MAX_LAYER) {Metal4}
+set ::env(RT_MIN_LAYER) {Metal2}
+set ::env(RUN_CVC) {0}
+set ::env(RUN_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20}
+set ::env(RUN_DRT) {1}
+set ::env(RUN_FILL_INSERTION) {0}
+set ::env(RUN_IRDROP_REPORT) {0}
+set ::env(RUN_KLAYOUT) {0}
+set ::env(RUN_KLAYOUT_DRC) {0}
+set ::env(RUN_KLAYOUT_XOR) {0}
+set ::env(RUN_LVS) {1}
+set ::env(RUN_MAGIC) {1}
+set ::env(RUN_MAGIC_DRC) {1}
+set ::env(RUN_SPEF_EXTRACTION) {1}
+set ::env(RUN_STANDALONE) {1}
+set ::env(RUN_TAG) {22_12_05_11_20}
+set ::env(RUN_TAP_DECAP_INSERTION) {0}
+set ::env(SCLPATH) {/localtmp/asic/gf180/pdk//gf180mcuC/gf180mcu_fd_sc_mcu7t5v0}
+set ::env(SCRIPTS_DIR) {/openlane/scripts}
+set ::env(SHLVL) {1}
+set ::env(SPEF_EXTRACTOR) {openrcx}
+set ::env(START_TIME) {2022.12.05_16.20.12}
+set ::env(STA_PRE_CTS) {0}
+set ::env(STA_REPORT_POWER) {1}
+set ::env(STA_WRITE_LIB) {1}
+set ::env(STD_CELL_GROUND_PINS) {VSS}
+set ::env(STD_CELL_LIBRARY) {gf180mcu_fd_sc_mcu7t5v0}
+set ::env(STD_CELL_LIBRARY_CDL) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/cdl/gf180mcu_fd_sc_mcu7t5v0.cdl}
+set ::env(STD_CELL_LIBRARY_OPT) {gf180mcu_fd_sc_mcu7t5v0}
+set ::env(STD_CELL_POWER_PINS) {VDD}
+set ::env(SYNTH_ADDER_TYPE) {YOSYS}
+set ::env(SYNTH_BIN) {yosys}
+set ::env(SYNTH_BUFFERING) {1}
+set ::env(SYNTH_CAP_LOAD) {72.91}
+set ::env(SYNTH_CLK_DRIVING_CELL) {gf180mcu_fd_sc_mcu7t5v0__inv_4}
+set ::env(SYNTH_CLK_DRIVING_CELL_PIN) {ZN}
+set ::env(SYNTH_CLOCK_TRANSITION) {0.15}
+set ::env(SYNTH_CLOCK_UNCERTAINTY) {0.25}
+set ::env(SYNTH_DEFINES) {USE_POWER_PINS}
+set ::env(SYNTH_DRIVING_CELL) {gf180mcu_fd_sc_mcu7t5v0__inv_1}
+set ::env(SYNTH_DRIVING_CELL_PIN) {ZN}
+set ::env(SYNTH_ELABORATE_ONLY) {1}
+set ::env(SYNTH_EXTRA_MAPPING_FILE) {}
+set ::env(SYNTH_FLAT_TOP) {0}
+set ::env(SYNTH_LATCH_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/latch_map.v}
+set ::env(SYNTH_MAX_FANOUT) {10}
+set ::env(SYNTH_MAX_TRAN) {3}
+set ::env(SYNTH_MIN_BUF_PORT) {gf180mcu_fd_sc_mcu7t5v0__buf_1 I Z}
+set ::env(SYNTH_NO_FLAT) {0}
+set ::env(SYNTH_OPT) {0}
+set ::env(SYNTH_READ_BLACKBOX_LIB) {0}
+set ::env(SYNTH_SCRIPT) {/openlane/scripts/yosys/elaborate.tcl}
+set ::env(SYNTH_SHARE_RESOURCES) {1}
+set ::env(SYNTH_SIZING) {0}
+set ::env(SYNTH_STRATEGY) {AREA 0}
+set ::env(SYNTH_TIEHI_PORT) {gf180mcu_fd_sc_mcu7t5v0__tieh Z}
+set ::env(SYNTH_TIELO_PORT) {gf180mcu_fd_sc_mcu7t5v0__tiel ZN}
+set ::env(SYNTH_TIMING_DERATE) {0.05}
+set ::env(SYNTH_USE_PG_PINS_DEFINES) {USE_POWER_PINS}
+set ::env(TAKE_LAYOUT_SCROT) {0}
+set ::env(TECH_LEF) {/localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef}
+set ::env(TECH_METAL_LAYERS) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(TERM) {xterm}
+set ::env(TERMINAL_OUTPUT) {/dev/null}
+set ::env(TMP_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp}
+set ::env(TOP_MARGIN_MULT) {4}
+set ::env(TRACKS_INFO_FILE) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info}
+set ::env(TRACKS_INFO_FILE_PROCESSED) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/routing/config.tracks}
+set ::env(TRISTATE_BUFFER_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tribuff_map.v}
+set ::env(USE_ARC_ANTENNA_CHECK) {1}
+set ::env(USE_GPIO_PADS) {0}
+set ::env(VCHECK_OUTPUT) {}
+set ::env(VDD_NET) {vdd}
+set ::env(VDD_NETS) {vdd}
+set ::env(VDD_PIN) {vdd}
+set ::env(VERILOG_FILES) { /home/xb4syf/ASIC/gf180-demo/caravel/verilog/rtl/defines.v  /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/../../verilog/rtl/user_project_wrapper.v}
+set ::env(VERILOG_FILES_BLACKBOX) { /home/xb4syf/ASIC/gf180-demo/caravel/verilog/rtl/defines.v  /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/../../verilog/rtl/plant_example.v}
+set ::env(WIRE_RC_LAYER) {Metal2}
+set ::env(YOSYS_REWRITE_VERILOG) {0}
+set ::env(_) {/openlane/flow.tcl}
+set ::env(cts_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/cts}
+set ::env(cts_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/cts}
+set ::env(cts_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/cts}
+set ::env(cts_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/cts}
+set ::env(drc_prefix) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff/drc}
+set ::env(eco_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/eco}
+set ::env(eco_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/eco}
+set ::env(eco_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/eco}
+set ::env(eco_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/eco}
+set ::env(floorplan_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/floorplan}
+set ::env(floorplan_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/floorplan}
+set ::env(floorplan_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/floorplan}
+set ::env(floorplan_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/floorplan}
+set ::env(fp_report_prefix) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/floorplan/3-initial_fp}
+set ::env(placement_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/placement}
+set ::env(placement_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/placement}
+set ::env(placement_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/placement}
+set ::env(placement_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/placement}
+set ::env(routing_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/routing}
+set ::env(routing_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/routing}
+set ::env(routing_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/routing}
+set ::env(routing_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/routing}
+set ::env(signoff_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff}
+set ::env(signoff_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff}
+set ::env(signoff_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/signoff}
+set ::env(signoff_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/signoff}
+set ::env(synth_report_prefix) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/synthesis/2-synthesis}
+set ::env(synthesis_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/synthesis}
+set ::env(synthesis_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/synthesis}
+set ::env(synthesis_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/synthesis}
+set ::env(synthesis_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/tmp/synthesis}
+set ::env(timer_end) {1670257326}
+set ::env(timer_routed) {1670257247}
+set ::env(timer_start) {1670257212}
diff --git a/openlane/user_project_wrapper/run/user_project_wrapper/config_in.tcl b/openlane/user_project_wrapper/run/user_project_wrapper/config_in.tcl
new file mode 100644
index 0000000..31e736d
--- /dev/null
+++ b/openlane/user_project_wrapper/run/user_project_wrapper/config_in.tcl
@@ -0,0 +1,83 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Base Configurations. Don't Touch
+# section begin
+
+set ::env(PDK) "gf180mcuC"
+set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
+
+# YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL
+source $::env(DESIGN_DIR)/fixed_dont_change/default_wrapper_cfgs.tcl
+
+set ::env(DESIGN_NAME) user_project_wrapper
+#section end
+
+# User Configurations
+
+## Source Verilog Files
+set ::env(VERILOG_FILES) "\
+	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+	$::env(DESIGN_DIR)/../../verilog/rtl/user_project_wrapper.v"
+
+## Clock configurations
+set ::env(CLOCK_PORT) "user_clock2"
+set ::env(CLOCK_NET) "plant_example_1.clk"
+
+set ::env(CLOCK_PERIOD) "50"
+
+## Internal Macros
+### Macro PDN Connections
+set ::env(FP_PDN_MACRO_HOOKS) "\
+	plant_example_1 vdd vss vdd vss"
+
+### Macro Placement
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
+
+### Black-box verilog and views
+set ::env(VERILOG_FILES_BLACKBOX) "\
+	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+	$::env(DESIGN_DIR)/../../verilog/rtl/plant_example.v"
+
+set ::env(EXTRA_LEFS) "\
+	$::env(DESIGN_DIR)/../../lef/plant_example.lef"
+
+set ::env(EXTRA_GDS_FILES) "\
+	$::env(DESIGN_DIR)/../../gds/plant_example.gds"
+
+set ::env(RT_MAX_LAYER) {Metal4}
+
+# disable pdn check nodes becuase it hangs with multiple power domains.
+# any issue with pdn connections will be flagged with LVS so it is not a critical check.
+set ::env(FP_PDN_CHECK_NODES) 0
+
+# The following is because there are no std cells in the example wrapper project.
+set ::env(SYNTH_ELABORATE_ONLY) 1
+set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+
+set ::env(FP_PDN_ENABLE_RAILS) 0
+
+set ::env(DIODE_INSERTION_STRATEGY) 0
+set ::env(RUN_FILL_INSERTION) 0
+set ::env(RUN_TAP_DECAP_INSERTION) 0
+set ::env(CLOCK_TREE_SYNTH) 0
+
+# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS 
+source $::env(DESIGN_DIR)/fixed_dont_change/fixed_wrapper_cfgs.tcl
diff --git a/openlane/user_project_wrapper/run/user_project_wrapper/openlane.log b/openlane/user_project_wrapper/run/user_project_wrapper/openlane.log
index d00491f..f5112f7 100644
--- a/openlane/user_project_wrapper/run/user_project_wrapper/openlane.log
+++ b/openlane/user_project_wrapper/run/user_project_wrapper/openlane.log
@@ -1 +1,48 @@
-1
+[INFO]: Run Directory: /home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20
+[INFO]: Preparing LEF files for the nom corner...
+[INFO]: Running Synthesis (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/synthesis/1-synthesis.log)...
+[INFO]: Running Single-Corner Static Timing Analysis (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/synthesis/2-sta.log)...
+[INFO]: Creating a netlist with power/ground pins.
+[INFO]: Running Initial Floorplanning (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/floorplan/3-initial_fp.log)...
+[INFO]: Floorplanned with width 2955.68 and height 2951.76.
+[INFO]: Running IO Placement (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/floorplan/4-place_io.log)...
+[INFO]: Performing Manual Macro Placement (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/placement/5-macro_placement.log)...
+[INFO]: Power planning with power {vdd} and ground {vss}...
+[INFO]: Generating PDN (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/floorplan/6-pdn.log)...
+[INFO]: Performing Random Global Placement (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/placement/7-global.log)...
+[INFO]: Skipping Placement Resizer Design Optimizations.
+[INFO]: Running Detailed Placement (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/placement/8-detailed.log)...
+[INFO]: Skipping Placement Resizer Timing Optimizations.
+[INFO]: Running Global Routing Resizer Timing Optimizations (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/routing/9-resizer.log)...
+[INFO]: Running Detailed Placement (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/routing/10-diode_legalization.log)...
+[INFO]: Running Global Routing (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/routing/11-global.log)...
+[INFO]: Writing Verilog (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/routing/11-global_write_netlist.log)...
+[INFO]: Running Detailed Routing (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/routing/13-detailed.log)...
+[INFO]: No DRC violations after detailed routing.
+[INFO]: Checking Wire Lengths (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/routing/14-wire_lengths.log)...
+[INFO]: Running SPEF Extraction at the nom process corner (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/15-parasitics_extraction.nom.log)...
+[INFO]: Running Multi-Corner Static Timing Analysis at the nom process corner (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/16-rcx_mcsta.nom.log)...
+[INFO]: Running Single-Corner Static Timing Analysis at the nom process corner (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/17-rcx_sta.log)...
+[INFO]: Running Magic to generate various views...
+[INFO]: Streaming out GDSII with Magic (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/18-gdsii.log)...
+[INFO]: Generating MAGLEF views...
+[INFO]: Running Magic Spice Export from LEF (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/19-spice.log)...
+[INFO]: Writing Powered Verilog (logs: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/20-write_powered_def.log, ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/20-write_powered_verilog.log)...
+[INFO]: Writing Verilog (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/20-write_powered_verilog.log)...
+[INFO]: Running LVS (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/22-lvs.lef.log)...
+[INFO]: Running Magic DRC (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/23-drc.log)...
+[INFO]: Converting Magic DRC database to various tool-readable formats...
+[INFO]: No DRC violations after GDS streaming out.
+[INFO]: Running OpenROAD Antenna Rule Checker (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/logs/signoff/24-antenna.log)...
+[INFO]: Saving current set of views in '../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/results/final'...
+[INFO]: Saving current set of views in '../home/xb4syf/ASIC/gf180-demo'...
+[INFO]: Saving runtime environment...
+[INFO]: Generating final set of reports...
+[INFO]: Created manufacturability report at '../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/manufacturability.rpt'.
+[INFO]: Created metrics report at '../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/metrics.csv'.
+[WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff/17-rcx_sta.slew.rpt'.
+[WARNING]: There are max capacitance violations in the design at the typical corner. Please refer to '../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff/17-rcx_sta.slew.rpt'.
+[INFO]: There are no hold violations in the design at the typical corner.
+[INFO]: There are no setup violations in the design at the typical corner.
+[SUCCESS]: Flow complete.
+[INFO]: Note that the following warnings have been generated:
diff --git a/openlane/user_project_wrapper/run/user_project_wrapper/runtime.yaml b/openlane/user_project_wrapper/run/user_project_wrapper/runtime.yaml
new file mode 100644
index 0000000..f88acb9
--- /dev/null
+++ b/openlane/user_project_wrapper/run/user_project_wrapper/runtime.yaml
@@ -0,0 +1,79 @@
+- status: 0 - openlane design prep
+  runtime_s: 2.77
+  runtime_ts: 0h0m2s772ms
+- status: 1 - synthesis - yosys
+  runtime_s: 1.42
+  runtime_ts: 0h0m1s415ms
+- status: 2 - sta - openroad
+  runtime_s: 0.99
+  runtime_ts: 0h0m0s995ms
+- status: 3 - floorplan initialization - openroad
+  runtime_s: 2.23
+  runtime_ts: 0h0m2s228ms
+- status: 4 - io_place - openlane
+  runtime_s: 0.68
+  runtime_ts: 0h0m0s678ms
+- status: 6 - pdn generation - openroad
+  runtime_s: 1.07
+  runtime_ts: 0h0m1s70ms
+- status: 7 - random global placement - openlane
+  runtime_s: 0.49
+  runtime_ts: 0h0m0s486ms
+- status: 8 - detailed placement - openroad
+  runtime_s: 1.34
+  runtime_ts: 0h0m1s338ms
+- status: 9 - resizer timing optimizations - openroad
+  runtime_s: 2.25
+  runtime_ts: 0h0m2s249ms
+- status: 10 - detailed placement - openroad
+  runtime_s: 1.74
+  runtime_ts: 0h0m1s738ms
+- status: 12 - write verilog - openroad
+  runtime_s: 1.17
+  runtime_ts: 0h0m1s173ms
+- status: 12 - global routing - openroad
+  runtime_s: 1.31
+  runtime_ts: 0h0m1s310ms
+- status: 13 - detailed_routing - openroad
+  runtime_s: 11.4
+  runtime_ts: 0h0m11s396ms
+- status: 14 - wire lengths - openlane
+  runtime_s: 1.0
+  runtime_ts: 0h0m1s0ms
+- status: 15 - parasitics extraction - openroad
+  runtime_s: 1.01
+  runtime_ts: 0h0m1s14ms
+- status: 16 - sta - openroad
+  runtime_s: 2.98
+  runtime_ts: 0h0m2s979ms
+- status: 17 - sta - openroad
+  runtime_s: 1.46
+  runtime_ts: 0h0m1s457ms
+- status: 18 - gdsii - magic
+  runtime_s: 6.4
+  runtime_ts: 0h0m6s397ms
+- status: 19 - spice extraction - magic
+  runtime_s: 4.4
+  runtime_ts: 0h0m4s400ms
+- status: 21 - write verilog - openroad
+  runtime_s: 1.41
+  runtime_ts: 0h0m1s409ms
+- status: 21 - write powered verilog - openlane
+  runtime_s: 1.56
+  runtime_ts: 0h0m1s555ms
+- status: 22 - lvs - netgen
+  runtime_s: 0.2
+  runtime_ts: 0h0m0s198ms
+- status: 23 - drc - magic
+  runtime_s: 55.66
+  runtime_ts: 0h0m55s661ms
+- status: 24 - antenna check - openroad
+  runtime_s: 1.38
+  runtime_ts: 0h0m1s378ms
+---
+- status: routed
+  runtime_s: 35.0
+  runtime_ts: 0h0m35s0ms
+- status: flow completed
+  runtime_s: 114.0
+  runtime_ts: 0h1m54s0ms
diff --git a/openlane/user_project_wrapper/run/user_project_wrapper/warnings.log b/openlane/user_project_wrapper/run/user_project_wrapper/warnings.log
new file mode 100644
index 0000000..552dde0
--- /dev/null
+++ b/openlane/user_project_wrapper/run/user_project_wrapper/warnings.log
@@ -0,0 +1,2 @@
+[WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff/17-rcx_sta.slew.rpt'.
+[WARNING]: There are max capacitance violations in the design at the typical corner. Please refer to '../home/xb4syf/ASIC/gf180-demo/openlane/user_project_wrapper/runs/22_12_05_11_20/reports/signoff/17-rcx_sta.slew.rpt'.