Add files via upload
diff --git a/openlane/user_proj_example/runs/user_proj_example/OPENLANE_VERSION b/openlane/user_proj_example/runs/user_proj_example/OPENLANE_VERSION
new file mode 100644
index 0000000..33889e4
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/OPENLANE_VERSION
@@ -0,0 +1 @@
+OpenLane 235fa7a4a2872e779588919c58fc4fa32568e075
diff --git a/openlane/user_proj_example/runs/user_proj_example/PDK_SOURCES b/openlane/user_proj_example/runs/user_proj_example/PDK_SOURCES
new file mode 100644
index 0000000..c5eb502
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/PDK_SOURCES
@@ -0,0 +1 @@
+open_pdks 35c7265f51749ad8d9fdbb575af22c7c8fab974e
diff --git a/openlane/user_proj_example/runs/user_proj_example/cmds.log b/openlane/user_proj_example/runs/user_proj_example/cmds.log
new file mode 100644
index 0000000..db4f01f
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/cmds.log
@@ -0,0 +1,122 @@
+Mon Dec 05 15:22:01 UTC 2022 - Executing "/openlane/scripts/mergeLef.py -o /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/merged.nom.lef -i /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/lef/gf180mcu_fd_sc_mcu7t5v0.lef |& tee /dev/null"
+
+Mon Dec 05 15:22:01 UTC 2022 - Executing "python3 /openlane/scripts/mergeLib.py --output /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/merged.lib --name gf180mcuC_merged /localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib"
+
+Mon Dec 05 15:22:02 UTC 2022 - Executing "python3 /openlane/scripts/libtrim.py --cell-file /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/trimmed.lib.exclude.list --output /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/trimmed.lib /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/merged.lib"
+
+Mon Dec 05 15:22:02 UTC 2022 - Executing "python3 /openlane/scripts/libtrim.py --cell-file /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/cts/cts.lib.exclude.list --output /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/cts/cts.lib /localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib"
+
+Mon Dec 05 15:22:03 UTC 2022 - Executing "python3 /openlane/scripts/new_tracks.py -i /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info -o /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/config.tracks"
+
+Mon Dec 05 15:22:03 UTC 2022 - Executing "echo {OpenLane 235fa7a4a2872e779588919c58fc4fa32568e075} > /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/OPENLANE_VERSION"
+
+Mon Dec 05 15:22:03 UTC 2022 - Executing "sed -E {s/^([[:space:]]+)pg_pin(.*)/\1pin\2\n\1 direction : "inout";/g} /localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib > /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/1-gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.no_pg.lib"
+
+Mon Dec 05 15:22:04 UTC 2022 - Executing "sed -E {s/^([[:space:]]+)pg_pin(.*)/\1pin\2\n\1 direction : "inout";/g} /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/trimmed.lib > /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/1-trimmed.no_pg.lib"
+
+Mon Dec 05 15:22:04 UTC 2022 - Executing "yosys -c /openlane/scripts/yosys/synth.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/synthesis/1-synthesis.log"
+
+Mon Dec 05 15:22:07 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/xb4syf\/ASIC\/gf180-demo\/openlane\/user_proj_example\/runs\/22_12_05_10_22\/results\/synthesis\/plant_example.v/} /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/config.tcl"
+
+Mon Dec 05 15:22:07 UTC 2022 - Executing "sed -i /defparam/d /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/synthesis/plant_example.v"
+
+Mon Dec 05 15:22:07 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/sta.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/synthesis/2-sta.log"
+
+Mon Dec 05 15:22:08 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/floorplan.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/floorplan/3-initial_fp.log"
+
+Mon Dec 05 15:22:09 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/floorplan.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/floorplan/3-initial_fp.log"
+
+Mon Dec 05 15:22:10 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/defutil.py extract_core_dims --output-data /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/dimensions.txt --input-lef /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/merged.nom.lef /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/floorplan/3-initial_fp.def"
+
+Mon Dec 05 15:22:10 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/io_place.py --config /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/pin_order.cfg --hor-layer Metal3 --ver-layer Metal2 --ver-width-mult 2 --hor-width-mult 2 --hor-extension -1 --ver-extension -1 --length 4 --unmatched-error --input-lef /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/merged.nom.lef --output-def /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/floorplan/4-io.def --output /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/floorplan/4-io.odb /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/floorplan/3-initial_fp.odb |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/floorplan/4-place_io.log"
+
+Mon Dec 05 15:22:11 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/tapcell.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/floorplan/5-tap.log"
+
+Mon Dec 05 15:22:12 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/pdn.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/floorplan/6-pdn.log"
+
+Mon Dec 05 15:22:13 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/gpl.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/placement/7-global.log"
+
+Mon Dec 05 15:22:17 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/resizer.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/placement/8-resizer.log"
+
+Mon Dec 05 15:22:18 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/xb4syf\/ASIC\/gf180-demo\/openlane\/user_proj_example\/runs\/22_12_05_10_22\/tmp\/placement\/8-resizer.nl.v/} /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/config.tcl"
+
+Mon Dec 05 15:22:19 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/dpl.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/placement/9-detailed.log"
+
+Mon Dec 05 15:22:20 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/xb4syf\/ASIC\/gf180-demo\/openlane\/user_proj_example\/runs\/22_12_05_10_22\/results\/placement\/plant_example.nl.v/} /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/config.tcl"
+
+Mon Dec 05 15:22:20 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/cts.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/cts/10-cts.log"
+
+Mon Dec 05 15:22:59 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/resizer_timing.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/cts/11-resizer.log"
+
+Mon Dec 05 15:23:00 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/xb4syf\/ASIC\/gf180-demo\/openlane\/user_proj_example\/runs\/22_12_05_10_22\/tmp\/cts\/11-plant_example.resized.nl.v/} /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/config.tcl"
+
+Mon Dec 05 15:23:00 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/resizer_routing_timing.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/12-resizer.log"
+
+Mon Dec 05 15:23:02 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/xb4syf\/ASIC\/gf180-demo\/openlane\/user_proj_example\/runs\/22_12_05_10_22\/tmp\/12-plant_example.nl.v/} /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/config.tcl"
+
+Mon Dec 05 15:23:02 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/diodes.py place --diode-cell gf180mcu_fd_sc_mcu7t5v0__antenna --diode-pin I --fake-diode-cell gf180mcu_fd_sc_mcu7t5v0__antenna --input-lef /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/merged.nom.lef --output-def /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/13-diodes.def --output /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/13-diodes.odb /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/12-plant_example.odb |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/13-diodes.log"
+
+Mon Dec 05 15:23:02 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/dpl.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/14-diode_legalization.log"
+
+Mon Dec 05 15:23:03 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/xb4syf\/ASIC\/gf180-demo\/openlane\/user_proj_example\/runs\/22_12_05_10_22\/tmp\/routing\/diodes.nl.v/} /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/config.tcl"
+
+Mon Dec 05 15:23:04 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/fill.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/15-fill.log"
+
+Mon Dec 05 15:23:05 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/xb4syf\/ASIC\/gf180-demo\/openlane\/user_proj_example\/runs\/22_12_05_10_22\/tmp\/routing\/15-fill.nl.v/} /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/config.tcl"
+
+Mon Dec 05 15:23:05 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/groute.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/16-global.log"
+
+Mon Dec 05 15:23:07 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/write_views.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/16-global_write_netlist.log"
+
+Mon Dec 05 15:23:08 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/xb4syf\/ASIC\/gf180-demo\/openlane\/user_proj_example\/runs\/22_12_05_10_22\/tmp\/routing\/global.nl.v/} /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/config.tcl"
+
+Mon Dec 05 15:23:08 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/droute.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/18-detailed.log"
+
+Mon Dec 05 15:23:23 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/xb4syf\/ASIC\/gf180-demo\/openlane\/user_proj_example\/runs\/22_12_05_10_22\/results\/routing\/plant_example.nl.v/} /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/config.tcl"
+
+Mon Dec 05 15:23:23 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py tr to_klayout -o /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/routing/drt.klayout.xml --design-name plant_example /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/routing/drt.drc"
+
+Mon Dec 05 15:23:23 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/wire_lengths.py --report-out /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/routing/19-wire_lengths.csv --input-lef /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/merged.nom.lef --output-def /dev/null --output /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.odb /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.odb |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/19-wire_lengths.log"
+
+Mon Dec 05 15:23:24 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/rcx.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/20-parasitics_extraction.nom.log"
+
+Mon Dec 05 15:23:25 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/sta_multi_corner.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/21-rcx_mcsta.nom.log"
+
+Mon Dec 05 15:23:28 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/sta.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/22-rcx_sta.log"
+
+Mon Dec 05 15:23:30 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/def/mag_gds.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/23-gdsii.log"
+
+Mon Dec 05 15:23:31 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/gds/mag_with_pointers.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/23-gds_ptrs.log"
+
+Mon Dec 05 15:23:32 UTC 2022 - Executing "sed -i -n {/^<< properties >>/,/^<< end >>/p} /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/signoff/gds_ptrs.mag"
+
+Mon Dec 05 15:23:32 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/mag/lef.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/23-lef.log"
+
+Mon Dec 05 15:23:33 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/lef/maglef.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/23-maglef.log"
+
+Mon Dec 05 15:23:33 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/extract_spice.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/24-spice.log"
+
+Mon Dec 05 15:23:41 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/power_utils.py write_powered_def --output /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/signoff/24-plant_example.p.def --input-lef /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/merged.nom.lef --power-port vdd --ground-port vss --powered-netlist {} /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.def |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/25-write_powered_def.log"
+
+Mon Dec 05 15:23:41 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/write_views.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/25-write_powered_verilog.log"
+
+Mon Dec 05 15:23:42 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/xb4syf\/ASIC\/gf180-demo\/openlane\/user_proj_example\/runs\/22_12_05_10_22\/tmp\/signoff\/24-plant_example.nl.v/} /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/config.tcl"
+
+Mon Dec 05 15:23:43 UTC 2022 - Executing "netgen -batch source /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/signoff/27-setup_file.lef.lvs |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/27-lvs.lef.log"
+
+Mon Dec 05 15:23:43 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/drc.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/28-drc.log"
+
+Mon Dec 05 15:24:33 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_tcl -o /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff/drc.tcl /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff/drc.rpt"
+
+Mon Dec 05 15:24:33 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_tr -o /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff/drc.tr /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff/drc.rpt"
+
+Mon Dec 05 15:24:33 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py tr to_klayout -o /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff/drc.klayout.xml --design-name plant_example /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff/drc.tr"
+
+Mon Dec 05 15:24:33 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_rdb -o /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff/drc.rdb /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff/drc.rpt"
+
+Mon Dec 05 15:24:34 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/antenna_check.tcl |& tee /dev/null /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/29-antenna.log"
+
+Mon Dec 05 15:24:35 UTC 2022 - Executing "python3 /openlane/scripts/extract_antenna_violators.py --output /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff/29-antenna_violators.rpt /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/29-antenna.log"
+
+Mon Dec 05 15:24:35 UTC 2022 - Executing "python3 /openlane/scripts/generate_reports.py -d /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example --design_name plant_example --tag 22_12_05_10_22 --output_file /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/metrics.csv --man_report /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/manufacturability.rpt --run_path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22"
+
diff --git a/openlane/user_proj_example/runs/user_proj_example/config.tcl b/openlane/user_proj_example/runs/user_proj_example/config.tcl
new file mode 100644
index 0000000..4eaf591
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/config.tcl
@@ -0,0 +1,722 @@
+# Run configs
+set ::env(PDK_ROOT) {/localtmp/asic/gf180/pdk/}
+set ::env(BASE_SDC_FILE) {/openlane/scripts/base.sdc}
+set ::env(BOTTOM_MARGIN_MULT) {4}
+set ::env(CARRY_SELECT_ADDER_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/csa_map.v}
+set ::env(CELLS_LEF) {/localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/lef/gf180mcu_fd_sc_mcu7t5v0.lef}
+set ::env(CELL_PAD_EXCLUDE) {gf180mcu_fd_sc_mcu7t5v0__filltie_* gf180mcu_fd_sc_mcu7t5v0__filldecap_* gf180mcu_fd_sc_mcu7t5v0__fill_* gf180mcu_fd_sc_mcu7t5v0__endcap_*}
+set ::env(CHECK_ASSIGN_STATEMENTS) {0}
+set ::env(CHECK_UNMAPPED_CELLS) {1}
+set ::env(CLOCK_BUFFER_FANOUT) {16}
+set ::env(CLOCK_PERIOD) {30.0}
+set ::env(CLOCK_PORT) {wb_clk_i}
+set ::env(CLOCK_TREE_SYNTH) {1}
+set ::env(CLOCK_WIRE_RC_LAYER) {Metal4}
+set ::env(CONFIGS) {general.tcl checkers.tcl synthesis.tcl floorplan.tcl cts.tcl placement.tcl routing.tcl extraction.tcl}
+set ::env(CTS_CLK_BUFFER_LIST) {gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 gf180mcu_fd_sc_mcu7t5v0__clkbuf_8}
+set ::env(CTS_CLK_MAX_WIRE_LENGTH) {0}
+set ::env(CTS_DISABLE_POST_PROCESSING) {0}
+set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) {0}
+set ::env(CTS_MAX_CAP) {0.5}
+set ::env(CTS_REPORT_TIMING) {1}
+set ::env(CTS_ROOT_BUFFER) {gf180mcu_fd_sc_mcu7t5v0__clkbuf_16}
+set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) {50}
+set ::env(CTS_SINK_CLUSTERING_SIZE) {25}
+set ::env(CTS_TARGET_SKEW) {200}
+set ::env(CTS_TOLERANCE) {100}
+set ::env(DATA_WIRE_RC_LAYER) {Metal2}
+set ::env(DECAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__fillcap_*}
+set ::env(DEFAULT_MAX_TRAN) {3}
+set ::env(DEF_UNITS_PER_MICRON) {2000}
+set ::env(DESIGN_CONFIG) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/config.tcl}
+set ::env(DESIGN_IS_CORE) {0}
+set ::env(DESIGN_NAME) {plant_example}
+set ::env(DETAILED_ROUTER) {tritonroute}
+set ::env(DIE_AREA) {0 0 900 600}
+set ::env(DIODE_CELL) {gf180mcu_fd_sc_mcu7t5v0__antenna}
+set ::env(DIODE_CELL_PIN) {I}
+set ::env(DIODE_INSERTION_STRATEGY) {4}
+set ::env(DIODE_PADDING) {2}
+set ::env(DPL_CELL_PADDING) {2}
+set ::env(DRC_EXCLUDE_CELL_LIST) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
+set ::env(DRC_EXCLUDE_CELL_LIST_OPT) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
+set ::env(DRT_MIN_LAYER) {Metal1}
+set ::env(DRT_OPT_ITERS) {64}
+set ::env(ECO_ENABLE) {0}
+set ::env(ECO_FINISH) {0}
+set ::env(ECO_ITER) {0}
+set ::env(ECO_SKIP_PIN) {1}
+set ::env(FILL_CELL) {gf180mcu_fd_sc_mcu7t5v0__fill_*}
+set ::env(FP_ASPECT_RATIO) {1}
+set ::env(FP_CORE_UTIL) {40}
+set ::env(FP_ENDCAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__endcap}
+set ::env(FP_IO_HEXTEND) {-1}
+set ::env(FP_IO_HLAYER) {Metal3}
+set ::env(FP_IO_HLENGTH) {4}
+set ::env(FP_IO_HTHICKNESS_MULT) {2}
+set ::env(FP_IO_MIN_DISTANCE) {3}
+set ::env(FP_IO_MODE) {1}
+set ::env(FP_IO_UNMATCHED_ERROR) {1}
+set ::env(FP_IO_VEXTEND) {-1}
+set ::env(FP_IO_VLAYER) {Metal2}
+set ::env(FP_IO_VLENGTH) {4}
+set ::env(FP_IO_VTHICKNESS_MULT) {2}
+set ::env(FP_PDN_AUTO_ADJUST) {1}
+set ::env(FP_PDN_CHECK_NODES) {1}
+set ::env(FP_PDN_CORE_RING) {0}
+set ::env(FP_PDN_CORE_RING_HOFFSET) {6}
+set ::env(FP_PDN_CORE_RING_HSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_HWIDTH) {1.6}
+set ::env(FP_PDN_CORE_RING_VOFFSET) {6}
+set ::env(FP_PDN_CORE_RING_VSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_VWIDTH) {1.6}
+set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) {1}
+set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
+set ::env(FP_PDN_ENABLE_RAILS) {1}
+set ::env(FP_PDN_HOFFSET) {16.65}
+set ::env(FP_PDN_HORIZONTAL_HALO) {10}
+set ::env(FP_PDN_HPITCH) {153.18}
+set ::env(FP_PDN_HSPACING) {1.7}
+set ::env(FP_PDN_HWIDTH) {1.6}
+set ::env(FP_PDN_IRDROP) {1}
+set ::env(FP_PDN_LOWER_LAYER) {Metal4}
+set ::env(FP_PDN_RAILS_LAYER) {Metal1}
+set ::env(FP_PDN_RAIL_OFFSET) {0}
+set ::env(FP_PDN_RAIL_WIDTH) {0.6}
+set ::env(FP_PDN_SKIPTRIM) {0}
+set ::env(FP_PDN_UPPER_LAYER) {Metal5}
+set ::env(FP_PDN_VERTICAL_HALO) {10}
+set ::env(FP_PDN_VOFFSET) {16.32}
+set ::env(FP_PDN_VPITCH) {153.6}
+set ::env(FP_PDN_VSPACING) {1.7}
+set ::env(FP_PDN_VWIDTH) {1.6}
+set ::env(FP_PIN_ORDER_CFG) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/pin_order.cfg}
+set ::env(FP_SIZING) {absolute}
+set ::env(FP_TAPCELL_DIST) {20}
+set ::env(FP_TAP_HORIZONTAL_HALO) {10}
+set ::env(FP_TAP_VERTICAL_HALO) {10}
+set ::env(FP_WELLTAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__filltie}
+set ::env(FULL_ADDER_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/fa_map.v}
+set ::env(GDS_FILES) {/localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/gds/gf180mcu_fd_sc_mcu7t5v0.gds}
+set ::env(GENERATE_FINAL_SUMMARY_REPORT) {1}
+set ::env(GLB_CFG_FILE) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/config.tcl}
+set ::env(GLB_OPTIMIZE_MIRRORING) {1}
+set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) {0}
+set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
+set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) {0.05}
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {10}
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {10}
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {0}
+set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
+set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) {0.025}
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(GLOBAL_ROUTER) {fastroute}
+set ::env(GND_NETS) {vss}
+set ::env(GND_PIN) {VSS}
+set ::env(GPIO_PADS_LEF) { /localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_io/lef/GF018green_ipio_5p0c_75_5lm.lef
+}
+set ::env(GPIO_PADS_VERILOG) { /localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_io/verilog/GF018green_ipio_5p0c_75_5lm.v
+}
+set ::env(GPL_CELL_PADDING) {0}
+set ::env(GRT_ADJUSTMENT) {0.3}
+set ::env(GRT_ALLOW_CONGESTION) {0}
+set ::env(GRT_ANT_ITERS) {3}
+set ::env(GRT_ESTIMATE_PARASITICS) {1}
+set ::env(GRT_LAYER_ADJUSTMENTS) {0,0,0,0,0}
+set ::env(GRT_MACRO_EXTENSION) {0}
+set ::env(GRT_MAX_DIODE_INS_ITERS) {1}
+set ::env(GRT_OVERFLOW_ITERS) {50}
+set ::env(IO_PCT) {0.2}
+set ::env(KLAYOUT_DRC_KLAYOUT_GDS) {0}
+set ::env(KLAYOUT_DRC_TECH_SCRIPT) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/klayout/gf180mcuC_mr.drc}
+set ::env(KLAYOUT_PROPERTIES) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/klayout/gf180mcuC.lyp}
+set ::env(KLAYOUT_TECH) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/klayout/gf180mcuC.lyt}
+set ::env(KLAYOUT_XOR_GDS) {1}
+set ::env(KLAYOUT_XOR_XML) {1}
+set ::env(LEC_ENABLE) {0}
+set ::env(LEFT_MARGIN_MULT) {12}
+set ::env(LIB_FASTEST) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ff_n40C_5v50.lib}
+set ::env(LIB_SLOWEST) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ss_125C_4v50.lib}
+set ::env(LIB_SYNTH) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(LIB_TYPICAL) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(LOGS_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs}
+set ::env(LVS_CONNECT_BY_LABEL) {0}
+set ::env(LVS_INSERT_POWER_PINS) {1}
+set ::env(MACRO_BLOCKAGES_LAYER) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(MAGIC_CONVERT_DRC_TO_RDB) {1}
+set ::env(MAGIC_DEF_LABELS) {1}
+set ::env(MAGIC_DEF_NO_BLOCKAGES) {1}
+set ::env(MAGIC_DISABLE_HIER_GDS) {1}
+set ::env(MAGIC_DRC_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
+set ::env(MAGIC_GENERATE_GDS) {1}
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_GENERATE_MAGLEF) {1}
+set ::env(MAGIC_INCLUDE_GDS_POINTERS) {0}
+set ::env(MAGIC_MAGICRC) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc}
+set ::env(MAGIC_PAD) {0}
+set ::env(MAGIC_TECH_FILE) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.tech}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+set ::env(MAGIC_ZEROIZE_ORIGIN) {0}
+set ::env(METAL_LAYER_NAMES) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(NETGEN_SETUP_FILE) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/netgen/gf180mcuC_setup.tcl}
+set ::env(NO_SYNTH_CELL_LIST) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells}
+set ::env(OPENLANE_VERBOSE) {0}
+set ::env(PDKPATH) {/localtmp/asic/gf180/pdk//gf180mcuC}
+set ::env(PDN_CFG) {/openlane/scripts/openroad/common/pdn_cfg.tcl}
+set ::env(PLACE_SITE) {GF018hv5v_mcu_sc7}
+set ::env(PLACE_SITE_HEIGHT) {3.92}
+set ::env(PLACE_SITE_WIDTH) {0.56}
+set ::env(PL_BASIC_PLACEMENT) {0}
+set ::env(PL_ESTIMATE_PARASITICS) {1}
+set ::env(PL_LIB) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(PL_MACRO_CHANNEL) {0 0}
+set ::env(PL_MACRO_HALO) {0 0}
+set ::env(PL_MAX_DISPLACEMENT_X) {500}
+set ::env(PL_MAX_DISPLACEMENT_Y) {100}
+set ::env(PL_OPTIMIZE_MIRRORING) {1}
+set ::env(PL_RANDOM_GLB_PLACEMENT) {0}
+set ::env(PL_RANDOM_INITIAL_PLACEMENT) {0}
+set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) {0}
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {1}
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {1}
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {1}
+set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) {0.1}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {20}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {20}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {0}
+set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) {1}
+set ::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
+set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) {0.05}
+set ::env(PL_RESIZER_TIE_SEPERATION) {0}
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(PL_ROUTABILITY_DRIVEN) {1}
+set ::env(PL_SKIP_INITIAL_PLACEMENT) {0}
+set ::env(PL_TARGET_DENSITY) {0.45}
+set ::env(PL_TIME_DRIVEN) {1}
+set ::env(PRIMARY_SIGNOFF_TOOL) {magic}
+set ::env(PROCESS) {180}
+set ::env(QUIT_ON_HOLD_VIOLATIONS) {1}
+set ::env(QUIT_ON_ILLEGAL_OVERLAPS) {1}
+set ::env(QUIT_ON_LONG_WIRE) {0}
+set ::env(QUIT_ON_LVS_ERROR) {1}
+set ::env(QUIT_ON_MAGIC_DRC) {1}
+set ::env(QUIT_ON_SETUP_VIOLATIONS) {1}
+set ::env(QUIT_ON_TIMING_VIOLATIONS) {1}
+set ::env(QUIT_ON_TR_DRC) {1}
+set ::env(RCX_CC_MODEL) {10}
+set ::env(RCX_CONTEXT_DEPTH) {5}
+set ::env(RCX_CORNER_COUNT) {1}
+set ::env(RCX_COUPLING_THRESHOLD) {0.1}
+set ::env(RCX_MAX_RESISTANCE) {50}
+set ::env(RCX_MERGE_VIA_WIRE_RES) {1}
+set ::env(RCX_RULES) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.nom}
+set ::env(RCX_RULES_MAX) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.max}
+set ::env(RCX_RULES_MIN) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.min}
+set ::env(REPORTS_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports}
+set ::env(RESULTS_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results}
+set ::env(RIGHT_MARGIN_MULT) {12}
+set ::env(RIPPLE_CARRY_ADDER_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/rca_map.v}
+set ::env(ROUTING_CORES) {2}
+set ::env(RSZ_DONT_TOUCH_RX) {$^}
+set ::env(RSZ_USE_OLD_REMOVER) {0}
+set ::env(RT_MAX_LAYER) {Metal4}
+set ::env(RT_MIN_LAYER) {Metal2}
+set ::env(RUN_CVC) {1}
+set ::env(RUN_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22}
+set ::env(RUN_DRT) {1}
+set ::env(RUN_FILL_INSERTION) {1}
+set ::env(RUN_IRDROP_REPORT) {0}
+set ::env(RUN_KLAYOUT) {0}
+set ::env(RUN_KLAYOUT_DRC) {0}
+set ::env(RUN_KLAYOUT_XOR) {0}
+set ::env(RUN_LVS) {1}
+set ::env(RUN_MAGIC) {1}
+set ::env(RUN_MAGIC_DRC) {1}
+set ::env(RUN_SPEF_EXTRACTION) {1}
+set ::env(RUN_TAG) {22_12_05_10_22}
+set ::env(RUN_TAP_DECAP_INSERTION) {1}
+set ::env(SCLPATH) {/localtmp/asic/gf180/pdk//gf180mcuC/gf180mcu_fd_sc_mcu7t5v0}
+set ::env(SPEF_EXTRACTOR) {openrcx}
+set ::env(START_TIME) {2022.12.05_15.22.01}
+set ::env(STA_REPORT_POWER) {1}
+set ::env(STA_WRITE_LIB) {1}
+set ::env(STD_CELL_GROUND_PINS) {VSS}
+set ::env(STD_CELL_LIBRARY) {gf180mcu_fd_sc_mcu7t5v0}
+set ::env(STD_CELL_LIBRARY_CDL) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/cdl/gf180mcu_fd_sc_mcu7t5v0.cdl}
+set ::env(STD_CELL_LIBRARY_OPT) {gf180mcu_fd_sc_mcu7t5v0}
+set ::env(STD_CELL_POWER_PINS) {VDD}
+set ::env(SYNTH_ADDER_TYPE) {YOSYS}
+set ::env(SYNTH_BIN) {yosys}
+set ::env(SYNTH_BUFFERING) {1}
+set ::env(SYNTH_CAP_LOAD) {72.91}
+set ::env(SYNTH_CLK_DRIVING_CELL) {gf180mcu_fd_sc_mcu7t5v0__inv_4}
+set ::env(SYNTH_CLK_DRIVING_CELL_PIN) {ZN}
+set ::env(SYNTH_CLOCK_TRANSITION) {0.15}
+set ::env(SYNTH_CLOCK_UNCERTAINTY) {0.25}
+set ::env(SYNTH_DRIVING_CELL) {gf180mcu_fd_sc_mcu7t5v0__inv_1}
+set ::env(SYNTH_DRIVING_CELL_PIN) {ZN}
+set ::env(SYNTH_ELABORATE_ONLY) {0}
+set ::env(SYNTH_EXTRA_MAPPING_FILE) {}
+set ::env(SYNTH_FLAT_TOP) {0}
+set ::env(SYNTH_LATCH_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/latch_map.v}
+set ::env(SYNTH_MAX_FANOUT) {4}
+set ::env(SYNTH_MIN_BUF_PORT) {gf180mcu_fd_sc_mcu7t5v0__buf_1 I Z}
+set ::env(SYNTH_NO_FLAT) {0}
+set ::env(SYNTH_READ_BLACKBOX_LIB) {0}
+set ::env(SYNTH_SCRIPT) {/openlane/scripts/yosys/synth.tcl}
+set ::env(SYNTH_SHARE_RESOURCES) {1}
+set ::env(SYNTH_SIZING) {0}
+set ::env(SYNTH_STRATEGY) {AREA 0}
+set ::env(SYNTH_TIEHI_PORT) {gf180mcu_fd_sc_mcu7t5v0__tieh Z}
+set ::env(SYNTH_TIELO_PORT) {gf180mcu_fd_sc_mcu7t5v0__tiel ZN}
+set ::env(SYNTH_TIMING_DERATE) {0.05}
+set ::env(TAKE_LAYOUT_SCROT) {0}
+set ::env(TECH_LEF) {/localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef}
+set ::env(TERMINAL_OUTPUT) {/dev/null}
+set ::env(TMP_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp}
+set ::env(TOP_MARGIN_MULT) {4}
+set ::env(TRACKS_INFO_FILE) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info}
+set ::env(TRISTATE_BUFFER_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tribuff_map.v}
+set ::env(USE_ARC_ANTENNA_CHECK) {1}
+set ::env(USE_GPIO_PADS) {0}
+set ::env(VDD_NETS) {vdd}
+set ::env(VDD_PIN) {VDD}
+set ::env(VERILOG_FILES) { /home/xb4syf/ASIC/gf180-demo/caravel/verilog/rtl/defines.v /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/../../verilog/rtl/plant_example.v}
+set ::env(WIRE_RC_LAYER) {Metal2}
+set ::env(YOSYS_REWRITE_VERILOG) {0}
+set ::env(cts_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/cts}
+set ::env(cts_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/cts}
+set ::env(cts_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/cts}
+set ::env(cts_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/cts}
+set ::env(eco_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/eco}
+set ::env(eco_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/eco}
+set ::env(eco_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/eco}
+set ::env(eco_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/eco}
+set ::env(floorplan_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/floorplan}
+set ::env(floorplan_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/floorplan}
+set ::env(floorplan_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/floorplan}
+set ::env(floorplan_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/floorplan}
+set ::env(placement_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/placement}
+set ::env(placement_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/placement}
+set ::env(placement_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/placement}
+set ::env(placement_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/placement}
+set ::env(routing_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing}
+set ::env(routing_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/routing}
+set ::env(routing_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing}
+set ::env(routing_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing}
+set ::env(signoff_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff}
+set ::env(signoff_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff}
+set ::env(signoff_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff}
+set ::env(signoff_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/signoff}
+set ::env(synthesis_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/synthesis}
+set ::env(synthesis_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/synthesis}
+set ::env(synthesis_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/synthesis}
+set ::env(synthesis_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis}
+set ::env(SYNTH_MAX_TRAN) {3.0}
+set ::env(CURRENT_INDEX) 29
+set ::env(CURRENT_DEF) /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.def
+set ::env(CURRENT_GUIDE) /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/16-global.guide
+set ::env(CURRENT_NETLIST) /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/signoff/24-plant_example.nl.v
+set ::env(CURRENT_POWERED_NETLIST) {0}
+set ::env(CURRENT_ODB) /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.odb
+set ::env(PDK_ROOT) {/localtmp/asic/gf180/pdk/}
+set ::env(ANTENNA_CHECK_CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/signoff/24-plant_example.p.def}
+set ::env(ANTENNA_VIOLATOR_LIST) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff/29-antenna_violators.rpt}
+set ::env(BASE_SDC_FILE) {/openlane/scripts/base.sdc}
+set ::env(BASIC_PREP_COMPLETE) {1}
+set ::env(BOTTOM_MARGIN_MULT) {4}
+set ::env(CARAVEL_ROOT) {/home/xb4syf/ASIC/gf180-demo/caravel}
+set ::env(CARRY_SELECT_ADDER_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/csa_map.v}
+set ::env(CELLS_LEF) {/localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/lef/gf180mcu_fd_sc_mcu7t5v0.lef}
+set ::env(CELL_PAD_EXCLUDE) {gf180mcu_fd_sc_mcu7t5v0__filltie_* gf180mcu_fd_sc_mcu7t5v0__filldecap_* gf180mcu_fd_sc_mcu7t5v0__fill_* gf180mcu_fd_sc_mcu7t5v0__endcap_*}
+set ::env(CHECK_ASSIGN_STATEMENTS) {0}
+set ::env(CHECK_UNMAPPED_CELLS) {1}
+set ::env(CLOCK_BUFFER_FANOUT) {16}
+set ::env(CLOCK_NET) {wb_clk_i}
+set ::env(CLOCK_PERIOD) {30.0}
+set ::env(CLOCK_PORT) {wb_clk_i}
+set ::env(CLOCK_TREE_SYNTH) {1}
+set ::env(CLOCK_WIRE_RC_LAYER) {Metal4}
+set ::env(CONFIGS) {general.tcl checkers.tcl synthesis.tcl floorplan.tcl cts.tcl placement.tcl routing.tcl extraction.tcl}
+set ::env(CORE_AREA) {6.72 15.68 893.2 584.08}
+set ::env(CORE_HEIGHT) {568.4}
+set ::env(CORE_WIDTH) {886.48}
+set ::env(CTS_CLK_BUFFER_LIST) {gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 gf180mcu_fd_sc_mcu7t5v0__clkbuf_8}
+set ::env(CTS_CLK_MAX_WIRE_LENGTH) {0}
+set ::env(CTS_CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/placement/plant_example.def}
+set ::env(CTS_DISABLE_POST_PROCESSING) {0}
+set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) {0}
+set ::env(CTS_MAX_CAP) {0.5}
+set ::env(CTS_REPORT_TIMING) {1}
+set ::env(CTS_ROOT_BUFFER) {gf180mcu_fd_sc_mcu7t5v0__clkbuf_16}
+set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) {50}
+set ::env(CTS_SINK_CLUSTERING_SIZE) {25}
+set ::env(CTS_TARGET_SKEW) {200}
+set ::env(CTS_TOLERANCE) {100}
+set ::env(CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/signoff/24-plant_example.p.def}
+set ::env(CURRENT_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing}
+set ::env(CURRENT_GDS) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/plant_example.gds}
+set ::env(CURRENT_GUIDE) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/16-global.guide}
+set ::env(CURRENT_INDEX) {29}
+set ::env(CURRENT_LIB) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/mca/process_corner_nom/plant_example.lib}
+set ::env(CURRENT_NETLIST) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/signoff/24-plant_example.nl.v}
+set ::env(CURRENT_ODB) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.odb}
+set ::env(CURRENT_POWERED_NETLIST) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/signoff/24-plant_example.pnl.v}
+set ::env(CURRENT_SDC) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/12-plant_example.sdc}
+set ::env(CURRENT_SDF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/mca/process_corner_nom/plant_example.sdf}
+set ::env(CURRENT_SPEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/mca/process_corner_nom/plant_example.spef}
+set ::env(CURRENT_STEP) {}
+set ::env(DATA_WIRE_RC_LAYER) {Metal2}
+set ::env(DECAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__fillcap_*}
+set ::env(DEFAULT_MAX_TRAN) {3}
+set ::env(DEF_UNITS_PER_MICRON) {2000}
+set ::env(DESIGN_CONFIG) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/config.tcl}
+set ::env(DESIGN_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example}
+set ::env(DESIGN_IS_CORE) {0}
+set ::env(DESIGN_NAME) {plant_example}
+set ::env(DETAILED_ROUTER) {tritonroute}
+set ::env(DIE_AREA) {0.0 0.0 900.0 600.0}
+set ::env(DIODE_CELL) {gf180mcu_fd_sc_mcu7t5v0__antenna}
+set ::env(DIODE_CELL_PIN) {I}
+set ::env(DIODE_INSERTION_CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.def}
+set ::env(DIODE_INSERTION_STRATEGY) {4}
+set ::env(DIODE_PADDING) {2}
+set ::env(DONT_USE_CELLS) {gf180mcu_fd_sc_mcu7t5v0__mux2_1 gf180mcu_fd_sc_mcu7t5v0__oai33_2 }
+set ::env(DPL_CELL_PADDING) {2}
+set ::env(DRC_CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/signoff/24-plant_example.p.def}
+set ::env(DRC_EXCLUDE_CELL_LIST) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
+set ::env(DRC_EXCLUDE_CELL_LIST_OPT) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
+set ::env(DRT_MIN_LAYER) {Metal1}
+set ::env(DRT_OPT_ITERS) {64}
+set ::env(ECO_ENABLE) {0}
+set ::env(ECO_FINISH) {0}
+set ::env(ECO_ITER) {0}
+set ::env(ECO_SKIP_PIN) {1}
+set ::env(EXT_NETLIST) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/plant_example.spice}
+set ::env(FILL_CELL) {gf180mcu_fd_sc_mcu7t5v0__fill_*}
+set ::env(FP_ASPECT_RATIO) {1}
+set ::env(FP_CORE_UTIL) {40}
+set ::env(FP_ENDCAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__endcap}
+set ::env(FP_IO_HEXTEND) {-1}
+set ::env(FP_IO_HLAYER) {Metal3}
+set ::env(FP_IO_HLENGTH) {4}
+set ::env(FP_IO_HTHICKNESS_MULT) {2}
+set ::env(FP_IO_MIN_DISTANCE) {3}
+set ::env(FP_IO_MODE) {1}
+set ::env(FP_IO_UNMATCHED_ERROR) {1}
+set ::env(FP_IO_VEXTEND) {-1}
+set ::env(FP_IO_VLAYER) {Metal2}
+set ::env(FP_IO_VLENGTH) {4}
+set ::env(FP_IO_VTHICKNESS_MULT) {2}
+set ::env(FP_PDN_AUTO_ADJUST) {1}
+set ::env(FP_PDN_CHECK_NODES) {1}
+set ::env(FP_PDN_CORE_RING) {0}
+set ::env(FP_PDN_CORE_RING_HOFFSET) {6}
+set ::env(FP_PDN_CORE_RING_HSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_HWIDTH) {1.6}
+set ::env(FP_PDN_CORE_RING_VOFFSET) {6}
+set ::env(FP_PDN_CORE_RING_VSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_VWIDTH) {1.6}
+set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) {1}
+set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
+set ::env(FP_PDN_ENABLE_RAILS) {1}
+set ::env(FP_PDN_HOFFSET) {16.65}
+set ::env(FP_PDN_HORIZONTAL_HALO) {10}
+set ::env(FP_PDN_HPITCH) {153.18}
+set ::env(FP_PDN_HSPACING) {1.7}
+set ::env(FP_PDN_HWIDTH) {1.6}
+set ::env(FP_PDN_IRDROP) {1}
+set ::env(FP_PDN_LOWER_LAYER) {Metal4}
+set ::env(FP_PDN_RAILS_LAYER) {Metal1}
+set ::env(FP_PDN_RAIL_OFFSET) {0}
+set ::env(FP_PDN_RAIL_WIDTH) {0.6}
+set ::env(FP_PDN_SKIPTRIM) {0}
+set ::env(FP_PDN_UPPER_LAYER) {Metal5}
+set ::env(FP_PDN_VERTICAL_HALO) {10}
+set ::env(FP_PDN_VOFFSET) {16.32}
+set ::env(FP_PDN_VPITCH) {153.6}
+set ::env(FP_PDN_VSPACING) {1.7}
+set ::env(FP_PDN_VWIDTH) {1.6}
+set ::env(FP_PIN_ORDER_CFG) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/pin_order.cfg}
+set ::env(FP_SIZING) {absolute}
+set ::env(FP_TAPCELL_DIST) {20}
+set ::env(FP_TAP_HORIZONTAL_HALO) {10}
+set ::env(FP_TAP_VERTICAL_HALO) {10}
+set ::env(FP_WELLTAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__filltie}
+set ::env(FULL_ADDER_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/fa_map.v}
+set ::env(GDS_FILES) {/localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/gds/gf180mcu_fd_sc_mcu7t5v0.gds}
+set ::env(GENERATE_FINAL_SUMMARY_REPORT) {1}
+set ::env(GLB_CFG_FILE) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/config.tcl}
+set ::env(GLB_OPTIMIZE_MIRRORING) {1}
+set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) {0}
+set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
+set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) {0.05}
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {10}
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {10}
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {0}
+set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
+set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) {0.025}
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(GLOBAL_ROUTER) {fastroute}
+set ::env(GND_NET) {vss}
+set ::env(GND_NETS) {vss}
+set ::env(GND_PIN) {vss}
+set ::env(GPIO_PADS_LEF) { /localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_io/lef/GF018green_ipio_5p0c_75_5lm.lef
+}
+set ::env(GPIO_PADS_VERILOG) { /localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_io/verilog/GF018green_ipio_5p0c_75_5lm.v
+}
+set ::env(GPL_CELL_PADDING) {0}
+set ::env(GRT_ADJUSTMENT) {0.3}
+set ::env(GRT_ALLOW_CONGESTION) {0}
+set ::env(GRT_ANT_ITERS) {3}
+set ::env(GRT_ESTIMATE_PARASITICS) {1}
+set ::env(GRT_LAYER_ADJUSTMENTS) {0,0,0,0,0}
+set ::env(GRT_MACRO_EXTENSION) {0}
+set ::env(GRT_MAX_DIODE_INS_ITERS) {1}
+set ::env(GRT_OVERFLOW_ITERS) {50}
+set ::env(HOME) {/}
+set ::env(HOSTNAME) {784831c5efa2}
+set ::env(IO_PCT) {0.2}
+set ::env(KLAYOUT_DRC_KLAYOUT_GDS) {0}
+set ::env(KLAYOUT_DRC_TECH_SCRIPT) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/klayout/gf180mcuC_mr.drc}
+set ::env(KLAYOUT_PROPERTIES) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/klayout/gf180mcuC.lyp}
+set ::env(KLAYOUT_TECH) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/klayout/gf180mcuC.lyt}
+set ::env(KLAYOUT_XOR_GDS) {1}
+set ::env(KLAYOUT_XOR_XML) {1}
+set ::env(LANG) {en_US.UTF-8}
+set ::env(LAST_TIMING_REPORT_TAG) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff/22-rcx_sta}
+set ::env(LC_ALL) {en_US.UTF-8}
+set ::env(LC_CTYPE) {en_US.UTF-8}
+set ::env(LD_LIBRARY_PATH) {/build//lib:/build//lib/Linux-x86_64:}
+set ::env(LEC_ENABLE) {0}
+set ::env(LEFT_MARGIN_MULT) {12}
+set ::env(LIB_CTS) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/cts/cts.lib}
+set ::env(LIB_FASTEST) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ff_n40C_5v50.lib}
+set ::env(LIB_SLOWEST) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ss_125C_4v50.lib}
+set ::env(LIB_SYNTH) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/trimmed.lib}
+set ::env(LIB_SYNTH_COMPLETE) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(LIB_SYNTH_COMPLETE_NO_PG) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/1-gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.no_pg.lib}
+set ::env(LIB_SYNTH_MERGED) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/merged.lib}
+set ::env(LIB_SYNTH_NO_PG) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/1-trimmed.no_pg.lib}
+set ::env(LIB_TYPICAL) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(LOGS_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs}
+set ::env(LVS_CONNECT_BY_LABEL) {0}
+set ::env(LVS_CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.def}
+set ::env(LVS_INSERT_POWER_PINS) {1}
+set ::env(MACRO_BLOCKAGES_LAYER) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(MAGIC_CONVERT_DRC_TO_RDB) {1}
+set ::env(MAGIC_DEF_LABELS) {1}
+set ::env(MAGIC_DEF_NO_BLOCKAGES) {1}
+set ::env(MAGIC_DISABLE_HIER_GDS) {1}
+set ::env(MAGIC_DRC_USE_GDS) {1}
+set ::env(MAGIC_EXT_USE_GDS) {0}
+set ::env(MAGIC_GDS) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/plant_example.magic.gds}
+set ::env(MAGIC_GENERATE_GDS) {1}
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_GENERATE_MAGLEF) {1}
+set ::env(MAGIC_INCLUDE_GDS_POINTERS) {0}
+set ::env(MAGIC_MAGICRC) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc}
+set ::env(MAGIC_PAD) {0}
+set ::env(MAGIC_TECH_FILE) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/magic/gf180mcuC.tech}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+set ::env(MAGIC_ZEROIZE_ORIGIN) {0}
+set ::env(MAGTYPE) {maglef}
+set ::env(MANPATH) {/build//share/man:}
+set ::env(MAX_METAL_LAYER) {5}
+set ::env(MCW_ROOT) {/home/xb4syf/ASIC/gf180-demo/mgmt_core_wrapper}
+set ::env(MC_SDF_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/mca/sdf}
+set ::env(MC_SPEF_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/mca/spef}
+set ::env(MERGED_LEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/merged.nom.lef}
+set ::env(METAL_LAYER_NAMES) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(MISMATCHES_OK) {1}
+set ::env(NETGEN_SETUP_FILE) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/netgen/gf180mcuC_setup.tcl}
+set ::env(NO_SYNTH_CELL_LIST) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells}
+set ::env(OPENLANE_ROOT) {/openlane}
+set ::env(OPENLANE_RUN_TAG) {22_12_05_10_22}
+set ::env(OPENLANE_VERBOSE) {0}
+set ::env(OPENLANE_VERSION) {235fa7a4a2872e779588919c58fc4fa32568e075}
+set ::env(OPENROAD) {/build/}
+set ::env(OPENROAD_BIN) {openroad}
+set ::env(PARSITICS_CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.def}
+set ::env(PATH) {/openlane:/openlane/scripts:/build//bin:/build//bin/Linux-x86_64:/build//pdn/scripts:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin}
+set ::env(PDK) {gf180mcuC}
+set ::env(PDKPATH) {/localtmp/asic/gf180/pdk//gf180mcuC}
+set ::env(PDK_ROOT) {/localtmp/asic/gf180/pdk/}
+set ::env(PDN_CFG) {/openlane/scripts/openroad/common/pdn_cfg.tcl}
+set ::env(PLACEMENT_CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/floorplan/6-pdn.def}
+set ::env(PLACE_SITE) {GF018hv5v_mcu_sc7}
+set ::env(PLACE_SITE_HEIGHT) {3.92}
+set ::env(PLACE_SITE_WIDTH) {0.56}
+set ::env(PL_BASIC_PLACEMENT) {0}
+set ::env(PL_ESTIMATE_PARASITICS) {1}
+set ::env(PL_INIT_COEFF) {0.00002}
+set ::env(PL_IO_ITER) {5}
+set ::env(PL_LIB) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(PL_MACRO_CHANNEL) {0 0}
+set ::env(PL_MACRO_HALO) {0 0}
+set ::env(PL_MAX_DISPLACEMENT_X) {500}
+set ::env(PL_MAX_DISPLACEMENT_Y) {100}
+set ::env(PL_OPTIMIZE_MIRRORING) {1}
+set ::env(PL_RANDOM_GLB_PLACEMENT) {0}
+set ::env(PL_RANDOM_INITIAL_PLACEMENT) {0}
+set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) {0}
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {1}
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {1}
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {1}
+set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) {0.1}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {20}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {20}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {0}
+set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) {1}
+set ::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
+set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) {0.05}
+set ::env(PL_RESIZER_TIE_SEPERATION) {0}
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(PL_ROUTABILITY_DRIVEN) {1}
+set ::env(PL_SKIP_INITIAL_PLACEMENT) {0}
+set ::env(PL_TARGET_DENSITY) {0.45}
+set ::env(PL_TIME_DRIVEN) {1}
+set ::env(PRIMARY_SIGNOFF_TOOL) {magic}
+set ::env(PROCESS) {180}
+set ::env(PWD) {/openlane}
+set ::env(QUIT_ON_HOLD_VIOLATIONS) {1}
+set ::env(QUIT_ON_ILLEGAL_OVERLAPS) {1}
+set ::env(QUIT_ON_LONG_WIRE) {0}
+set ::env(QUIT_ON_LVS_ERROR) {1}
+set ::env(QUIT_ON_MAGIC_DRC) {1}
+set ::env(QUIT_ON_SETUP_VIOLATIONS) {1}
+set ::env(QUIT_ON_TIMING_VIOLATIONS) {1}
+set ::env(QUIT_ON_TR_DRC) {1}
+set ::env(RCX_CC_MODEL) {10}
+set ::env(RCX_CONTEXT_DEPTH) {5}
+set ::env(RCX_CORNER_COUNT) {1}
+set ::env(RCX_COUPLING_THRESHOLD) {0.1}
+set ::env(RCX_MAX_RESISTANCE) {50}
+set ::env(RCX_MERGE_VIA_WIRE_RES) {1}
+set ::env(RCX_RULES) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.nom}
+set ::env(RCX_RULES_MAX) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.max}
+set ::env(RCX_RULES_MIN) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.min}
+set ::env(RCX_SDC_FILE) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/12-plant_example.sdc}
+set ::env(REPORTS_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports}
+set ::env(RESULTS_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results}
+set ::env(RIGHT_MARGIN_MULT) {12}
+set ::env(RIPPLE_CARRY_ADDER_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/rca_map.v}
+set ::env(ROUTING_CORES) {2}
+set ::env(ROUTING_CURRENT_DEF) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/cts/11-plant_example.resized.def}
+set ::env(RSZ_DONT_TOUCH_RX) {\$^}
+set ::env(RSZ_LIB) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/resizer_gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib}
+set ::env(RSZ_USE_OLD_REMOVER) {0}
+set ::env(RT_MAX_LAYER) {Metal4}
+set ::env(RT_MIN_LAYER) {Metal2}
+set ::env(RUN_CVC) {1}
+set ::env(RUN_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22}
+set ::env(RUN_DRT) {1}
+set ::env(RUN_FILL_INSERTION) {1}
+set ::env(RUN_IRDROP_REPORT) {0}
+set ::env(RUN_KLAYOUT) {0}
+set ::env(RUN_KLAYOUT_DRC) {0}
+set ::env(RUN_KLAYOUT_XOR) {0}
+set ::env(RUN_LVS) {1}
+set ::env(RUN_MAGIC) {1}
+set ::env(RUN_MAGIC_DRC) {1}
+set ::env(RUN_SPEF_EXTRACTION) {1}
+set ::env(RUN_STANDALONE) {1}
+set ::env(RUN_TAG) {22_12_05_10_22}
+set ::env(RUN_TAP_DECAP_INSERTION) {1}
+set ::env(SCLPATH) {/localtmp/asic/gf180/pdk//gf180mcuC/gf180mcu_fd_sc_mcu7t5v0}
+set ::env(SCRIPTS_DIR) {/openlane/scripts}
+set ::env(SHLVL) {1}
+set ::env(SPEF_EXTRACTOR) {openrcx}
+set ::env(START_TIME) {2022.12.05_15.22.01}
+set ::env(STA_PRE_CTS) {0}
+set ::env(STA_REPORT_POWER) {1}
+set ::env(STA_WRITE_LIB) {1}
+set ::env(STD_CELL_GROUND_PINS) {VSS}
+set ::env(STD_CELL_LIBRARY) {gf180mcu_fd_sc_mcu7t5v0}
+set ::env(STD_CELL_LIBRARY_CDL) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/cdl/gf180mcu_fd_sc_mcu7t5v0.cdl}
+set ::env(STD_CELL_LIBRARY_OPT) {gf180mcu_fd_sc_mcu7t5v0}
+set ::env(STD_CELL_POWER_PINS) {VDD}
+set ::env(SYNTH_ADDER_TYPE) {YOSYS}
+set ::env(SYNTH_BIN) {yosys}
+set ::env(SYNTH_BUFFERING) {1}
+set ::env(SYNTH_CAP_LOAD) {72.91}
+set ::env(SYNTH_CLK_DRIVING_CELL) {gf180mcu_fd_sc_mcu7t5v0__inv_4}
+set ::env(SYNTH_CLK_DRIVING_CELL_PIN) {ZN}
+set ::env(SYNTH_CLOCK_TRANSITION) {0.15}
+set ::env(SYNTH_CLOCK_UNCERTAINTY) {0.25}
+set ::env(SYNTH_DRIVING_CELL) {gf180mcu_fd_sc_mcu7t5v0__inv_1}
+set ::env(SYNTH_DRIVING_CELL_PIN) {ZN}
+set ::env(SYNTH_ELABORATE_ONLY) {0}
+set ::env(SYNTH_EXTRA_MAPPING_FILE) {}
+set ::env(SYNTH_FLAT_TOP) {0}
+set ::env(SYNTH_LATCH_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/latch_map.v}
+set ::env(SYNTH_MAX_FANOUT) {4}
+set ::env(SYNTH_MAX_TRAN) {3.0}
+set ::env(SYNTH_MIN_BUF_PORT) {gf180mcu_fd_sc_mcu7t5v0__buf_1 I Z}
+set ::env(SYNTH_NO_FLAT) {0}
+set ::env(SYNTH_OPT) {0}
+set ::env(SYNTH_READ_BLACKBOX_LIB) {0}
+set ::env(SYNTH_SCRIPT) {/openlane/scripts/yosys/synth.tcl}
+set ::env(SYNTH_SHARE_RESOURCES) {1}
+set ::env(SYNTH_SIZING) {0}
+set ::env(SYNTH_STRATEGY) {AREA 0}
+set ::env(SYNTH_TIEHI_PORT) {gf180mcu_fd_sc_mcu7t5v0__tieh Z}
+set ::env(SYNTH_TIELO_PORT) {gf180mcu_fd_sc_mcu7t5v0__tiel ZN}
+set ::env(SYNTH_TIMING_DERATE) {0.05}
+set ::env(TAKE_LAYOUT_SCROT) {0}
+set ::env(TECH_LEF) {/localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef}
+set ::env(TECH_METAL_LAYERS) {Metal1 Metal2 Metal3 Metal4 Metal5}
+set ::env(TERM) {xterm}
+set ::env(TERMINAL_OUTPUT) {/dev/null}
+set ::env(TMP_DIR) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp}
+set ::env(TOP_MARGIN_MULT) {4}
+set ::env(TRACKS_INFO_FILE) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info}
+set ::env(TRACKS_INFO_FILE_PROCESSED) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/config.tracks}
+set ::env(TRISTATE_BUFFER_MAP) {/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tribuff_map.v}
+set ::env(USE_ARC_ANTENNA_CHECK) {1}
+set ::env(USE_GPIO_PADS) {0}
+set ::env(VCHECK_OUTPUT) {}
+set ::env(VDD_NET) {vdd}
+set ::env(VDD_NETS) {vdd}
+set ::env(VDD_PIN) {vdd}
+set ::env(VERILOG_FILES) { /home/xb4syf/ASIC/gf180-demo/caravel/verilog/rtl/defines.v /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/../../verilog/rtl/plant_example.v}
+set ::env(WIRE_RC_LAYER) {Metal2}
+set ::env(YOSYS_REWRITE_VERILOG) {0}
+set ::env(_) {/openlane/flow.tcl}
+set ::env(cts_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/cts}
+set ::env(cts_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/cts}
+set ::env(cts_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/cts}
+set ::env(cts_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/cts}
+set ::env(drc_prefix) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff/drc}
+set ::env(eco_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/eco}
+set ::env(eco_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/eco}
+set ::env(eco_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/eco}
+set ::env(eco_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/eco}
+set ::env(floorplan_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/floorplan}
+set ::env(floorplan_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/floorplan}
+set ::env(floorplan_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/floorplan}
+set ::env(floorplan_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/floorplan}
+set ::env(fp_report_prefix) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/floorplan/3-initial_fp}
+set ::env(placement_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/placement}
+set ::env(placement_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/placement}
+set ::env(placement_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/placement}
+set ::env(placement_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/placement}
+set ::env(routing_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing}
+set ::env(routing_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/routing}
+set ::env(routing_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing}
+set ::env(routing_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing}
+set ::env(signoff_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff}
+set ::env(signoff_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff}
+set ::env(signoff_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff}
+set ::env(signoff_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/signoff}
+set ::env(synth_report_prefix) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/synthesis/1-synthesis}
+set ::env(synthesis_logs) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/synthesis}
+set ::env(synthesis_reports) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/synthesis}
+set ::env(synthesis_results) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/synthesis}
+set ::env(synthesis_tmpfiles) {/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis}
+set ::env(timer_end) {1670253875}
+set ::env(timer_routed) {1670253804}
+set ::env(timer_start) {1670253720}
diff --git a/openlane/user_proj_example/runs/user_proj_example/config_in.tcl b/openlane/user_proj_example/runs/user_proj_example/config_in.tcl
new file mode 100644
index 0000000..441c77c
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/config_in.tcl
@@ -0,0 +1,56 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set ::env(PDK) "gf180mcuC"
+set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
+
+set ::env(DESIGN_NAME) plant_example
+
+set ::env(VERILOG_FILES) "\
+ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/plant_example.v"
+
+set ::env(DESIGN_IS_CORE) 0
+
+set ::env(CLOCK_PORT) "wb_clk_i"
+# set ::env(CLOCK_NET) "counter.clk"
+set ::env(CLOCK_PERIOD) "30.0"
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 900 600"
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(PL_BASIC_PLACEMENT) 0
+set ::env(PL_TARGET_DENSITY) 0.45
+
+set ::env(FP_CORE_UTIL) 40
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+# Maximum layer used for routing is metal 4.
+# This is because this macro will be inserted in a top level (user_project_wrapper)
+# where the PDN is planned on metal 5. So, to avoid having shorts between routes
+# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4.
+#
+set ::env(RT_MAX_LAYER) {Metal4}
+
+# You can draw more power domains if you need to
+set ::env(VDD_NETS) [list {vdd}]
+set ::env(GND_NETS) [list {vss}]
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+# If you're going to use multiple power domains, then disable cvc run.
+set ::env(RUN_CVC) 1
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/cts/10-cts.log b/openlane/user_proj_example/runs/user_proj_example/logs/cts/10-cts.log
new file mode 100644
index 0000000..dc4ae9e
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/cts/10-cts.log
@@ -0,0 +1,795 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO]: Setting RC values...
+[INFO]: Configuring cts characterization...
+[INFO]: Performing clock tree synthesis...
+[INFO]: Looking for the following net(s): wb_clk_i
+[INFO]: Running Clock Tree Synthesis...
+[INFO CTS-0049] Characterization buffer is: gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.
+[INFO CTS-0038] Number of created patterns = 50000.
+[INFO CTS-0038] Number of created patterns = 100000.
+[INFO CTS-0039] Number of created patterns = 137808.
+[INFO CTS-0084] Compiling LUT.
+Min. len Max. len Min. cap Max. cap Min. slew Max. slew
+2 8 1 34 1 79
+[WARNING CTS-0043] 4752 wires are pure wire and no slew degradation.
+TritonCTS forced slew degradation on these wires.
+[INFO CTS-0046] Number of wire segments: 137808.
+[INFO CTS-0047] Number of keys in characterization LUT: 1810.
+[INFO CTS-0048] Actual min input cap: 1.
+[INFO CTS-0007] Net "wb_clk_i" found for clock "wb_clk_i".
+[INFO CTS-0010] Clock net "wb_clk_i" has 6 sinks.
+[INFO CTS-0008] TritonCTS found 1 clock nets.
+[INFO CTS-0097] Characterization used 2 buffer(s) types.
+[INFO CTS-0027] Generating H-Tree topology for net wb_clk_i.
+[INFO CTS-0028] Total number of sinks: 6.
+[INFO CTS-0029] Sinks will be clustered in groups of up to 25 and with maximum cluster diameter of 50.0 um.
+[INFO CTS-0030] Number of static layers: 0.
+[INFO CTS-0020] Wire segment unit: 38000 dbu (19 um).
+[INFO CTS-0023] Original sink region: [(129920, 35280), (137760, 74480)].
+[INFO CTS-0024] Normalized sink region: [(3.41895, 0.928421), (3.62526, 1.96)].
+[INFO CTS-0025] Width: 0.2063.
+[INFO CTS-0026] Height: 1.0316.
+[WARNING CTS-0045] Creating fake entries in the LUT.
+ Level 1
+ Direction: Vertical
+ Sinks per sub-region: 3
+ Sub-region size: 0.2063 X 0.5158
+[INFO CTS-0034] Segment length (rounded): 1.
+ Key: 137808 inSlew: 1 inCap: 1 outSlew: 2 load: 1 length: 1 delay: 1
+[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
+[INFO CTS-0035] Number of sinks covered: 6.
+[INFO CTS-0036] Average source sink dist: 45893.33 dbu.
+[INFO CTS-0037] Number of outlier sinks: 0.
+[INFO CTS-0018] Created 3 clock buffers.
+[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
+[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
+[INFO CTS-0015] Created 3 clock nets.
+[INFO CTS-0016] Fanout distribution for the current clock = 3:2..
+[INFO CTS-0017] Max level of the clock tree: 1.
+[INFO CTS-0098] Clock net "wb_clk_i"
+[INFO CTS-0099] Sinks 6
+[INFO CTS-0100] Leaf buffers 0
+[INFO CTS-0101] Average sink wire length 100.40 um
+[INFO CTS-0102] Path depth 2 - 2
+[INFO]: Repairing long wires on clock nets...
+[INFO RSZ-0058] Using max wire length 18670um.
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/cts/plant_example.odb...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/cts/plant_example.def...
+Writing timing constraints to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/cts/plant_example.sdc...
+[INFO]: Legalizing...
+Placement Analysis
+---------------------------------
+total displacement 79.4 u
+average displacement 0.0 u
+max displacement 19.7 u
+original HPWL 10105.2 u
+legalized HPWL 10240.9 u
+delta HPWL 1 %
+
+[INFO DPL-0020] Mirrored 111 instances
+[INFO DPL-0021] HPWL before 10240.9 u
+[INFO DPL-0022] HPWL after 10094.7 u
+[INFO DPL-0023] HPWL delta -1.4 %
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/cts/plant_example.odb...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/cts/plant_example.def...
+Writing timing constraints to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/cts/plant_example.sdc...
+cts_report
+[INFO CTS-0003] Total number of Clock Roots: 1.
+[INFO CTS-0004] Total number of Buffers Inserted: 3.
+[INFO CTS-0005] Total number of Clock Subnets: 3.
+[INFO CTS-0006] Total number of Sinks: 6.
+cts_report_end
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.71 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 1.45 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.15 0.12 1.57 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp3555 (net)
+ 0.15 0.00 1.57 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.57 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.07 0.82 library hold time
+ 0.82 data required time
+-----------------------------------------------------------------------------
+ 0.82 data required time
+ -1.57 data arrival time
+-----------------------------------------------------------------------------
+ 0.75 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.31 0.76 1.25 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.31 0.00 1.25 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.24 0.20 1.45 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.01 _033_ (net)
+ 0.24 0.00 1.45 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.16 0.12 1.58 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _041_ (net)
+ 0.16 0.00 1.58 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.13 1.71 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _045_ (net)
+ 0.16 0.00 1.71 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.14 0.11 1.83 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2410 (net)
+ 0.14 0.00 1.83 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.83 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.07 0.82 library hold time
+ 0.82 data required time
+-----------------------------------------------------------------------------
+ 0.82 data required time
+ -1.83 data arrival time
+-----------------------------------------------------------------------------
+ 1.01 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.71 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 1.45 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.19 0.18 1.64 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 2 0.01 _048_ (net)
+ 0.19 0.00 1.64 v _121_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.25 1.89 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 1.89 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.23 2.12 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 2.12 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.12 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.06 0.81 library hold time
+ 0.81 data required time
+-----------------------------------------------------------------------------
+ 0.81 data required time
+ -2.12 data arrival time
+-----------------------------------------------------------------------------
+ 1.31 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.71 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 1.45 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.23 1.68 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.68 v _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.12 0.29 1.98 v _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _018_ (net)
+ 0.12 0.00 1.98 v _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.26 0.17 2.15 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.26 0.00 2.15 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.15 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.04 0.78 library hold time
+ 0.78 data required time
+-----------------------------------------------------------------------------
+ 0.78 data required time
+ -2.15 data arrival time
+-----------------------------------------------------------------------------
+ 1.37 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.71 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 1.45 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.23 1.68 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.68 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.12 0.34 2.03 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.12 0.00 2.03 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.12 0.20 2.22 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.12 0.00 2.22 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.22 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.03 0.77 clock reconvergence pessimism
+ 0.08 0.84 library hold time
+ 0.84 data required time
+-----------------------------------------------------------------------------
+ 0.84 data required time
+ -2.22 data arrival time
+-----------------------------------------------------------------------------
+ 1.38 slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.98 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.98 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.28 0.73 8.52 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.28 0.00 8.52 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.76 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.76 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.26 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.26 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.13 0.23 9.49 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.13 0.00 9.49 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.49 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.22 30.02 library setup time
+ 30.02 data required time
+-----------------------------------------------------------------------------
+ 30.02 data required time
+ -9.49 data arrival time
+-----------------------------------------------------------------------------
+ 20.53 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.49 0.98 1.53 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.49 0.00 1.53 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.35 0.31 1.84 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.35 0.00 1.84 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.62 0.46 2.29 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.62 0.00 2.29 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.18 2.48 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 2.48 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.29 0.25 2.73 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 net11 (net)
+ 0.29 0.00 2.73 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.46 3.19 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[1] (net)
+ 0.33 0.00 3.19 ^ io_oeb[1] (out)
+ 3.19 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -3.19 data arrival time
+-----------------------------------------------------------------------------
+ 20.56 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.49 0.98 1.53 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.49 0.00 1.53 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.35 0.31 1.84 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.35 0.00 1.84 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.62 0.46 2.29 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.62 0.00 2.29 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.18 2.48 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 2.48 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.23 2.71 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 net10 (net)
+ 0.27 0.00 2.71 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.46 3.17 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[0] (net)
+ 0.33 0.00 3.17 ^ io_oeb[0] (out)
+ 3.17 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -3.17 data arrival time
+-----------------------------------------------------------------------------
+ 20.58 slack (MET)
+
+
+Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.28 0.85 1.40 ^ _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_water_synth_0 (net)
+ 0.28 0.00 1.40 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.29 0.25 1.65 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 3 0.01 _000_ (net)
+ 0.29 0.00 1.65 v _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.25 0.54 2.19 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 3 0.01 _001_ (net)
+ 0.25 0.00 2.19 v _118_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.22 0.20 2.39 ^ _118_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 1 0.01 net12 (net)
+ 0.22 0.00 2.39 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.45 2.83 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_out[0] (net)
+ 0.33 0.00 2.84 ^ io_out[0] (out)
+ 2.84 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.84 data arrival time
+-----------------------------------------------------------------------------
+ 20.91 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ wbs_we_i (in)
+ 1 0.00 wbs_we_i (net)
+ 0.10 0.00 6.03 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.40 0.38 6.42 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 net9 (net)
+ 0.40 0.00 6.42 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.26 0.23 6.65 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.26 0.00 6.65 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.32 0.47 7.12 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.03 _004_ (net)
+ 0.32 0.00 7.12 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.30 0.58 7.70 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.30 0.00 7.71 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.42 0.33 8.03 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.42 0.00 8.03 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.17 0.12 8.15 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.17 0.00 8.15 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.28 8.43 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 8.43 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.26 8.69 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 8.69 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.27 0.21 8.90 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 fsm_plant_opt.tmp3553 (net)
+ 0.27 0.00 8.90 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.90 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.24 30.00 library setup time
+ 30.00 data required time
+-----------------------------------------------------------------------------
+ 30.00 data required time
+ -8.90 data arrival time
+-----------------------------------------------------------------------------
+ 21.10 slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.98 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.98 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.28 0.73 8.52 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.28 0.00 8.52 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.76 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.76 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.26 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.26 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.13 0.23 9.49 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.13 0.00 9.49 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.49 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.22 30.02 library setup time
+ 30.02 data required time
+-----------------------------------------------------------------------------
+ 30.02 data required time
+ -9.49 data arrival time
+-----------------------------------------------------------------------------
+ 20.53 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 20.53
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 0.75
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_129_/CLK ^
+ 0.55
+_126_/CLK ^
+ 0.50 -0.03 0.02
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 1.08e-04 6.56e-06 1.22e-09 1.14e-04 19.6%
+Combinational 3.76e-04 9.18e-05 1.91e-07 4.68e-04 80.4%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 4.84e-04 9.83e-05 1.92e-07 5.82e-04 100.0%
+ 83.1% 16.9% 0.0%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 18295 u^2 4% utilization.
+area_report_end
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/cts/plant_example.odb...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/cts/plant_example.def...
+Writing timing constraints to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/cts/plant_example.sdc...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/cts/11-resizer.log b/openlane/user_proj_example/runs/user_proj_example/logs/cts/11-resizer.log
new file mode 100644
index 0000000..4dde72d
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/cts/11-resizer.log
@@ -0,0 +1,736 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO]: Setting RC values...
+[INFO RSZ-0033] No hold violations found.
+Placement Analysis
+---------------------------------
+total displacement 0.0 u
+average displacement 0.0 u
+max displacement 0.0 u
+original HPWL 10094.7 u
+legalized HPWL 10240.9 u
+delta HPWL 1 %
+
+[INFO DPL-0020] Mirrored 111 instances
+[INFO DPL-0021] HPWL before 10240.9 u
+[INFO DPL-0022] HPWL after 10094.7 u
+[INFO DPL-0023] HPWL delta -1.4 %
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/cts/11-plant_example.resized.odb...
+Writing netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/cts/11-plant_example.resized.nl.v...
+Writing powered netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/cts/11-plant_example.resized.pnl.v...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/cts/11-plant_example.resized.def...
+Writing timing constraints to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/cts/11-plant_example.resized.sdc...
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.71 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 1.45 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.15 0.12 1.57 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp3555 (net)
+ 0.15 0.00 1.57 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.57 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.07 0.82 library hold time
+ 0.82 data required time
+-----------------------------------------------------------------------------
+ 0.82 data required time
+ -1.57 data arrival time
+-----------------------------------------------------------------------------
+ 0.75 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.31 0.76 1.25 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.31 0.00 1.25 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.24 0.20 1.45 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.01 _033_ (net)
+ 0.24 0.00 1.45 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.16 0.12 1.58 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _041_ (net)
+ 0.16 0.00 1.58 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.13 1.71 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _045_ (net)
+ 0.16 0.00 1.71 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.14 0.11 1.83 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2410 (net)
+ 0.14 0.00 1.83 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.83 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.07 0.82 library hold time
+ 0.82 data required time
+-----------------------------------------------------------------------------
+ 0.82 data required time
+ -1.83 data arrival time
+-----------------------------------------------------------------------------
+ 1.01 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.71 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 1.45 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.19 0.18 1.64 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 2 0.01 _048_ (net)
+ 0.19 0.00 1.64 v _121_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.25 1.89 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 1.89 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.23 2.12 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 2.12 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.12 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.06 0.81 library hold time
+ 0.81 data required time
+-----------------------------------------------------------------------------
+ 0.81 data required time
+ -2.12 data arrival time
+-----------------------------------------------------------------------------
+ 1.31 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.71 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 1.45 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.23 1.68 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.68 v _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.12 0.29 1.98 v _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _018_ (net)
+ 0.12 0.00 1.98 v _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.26 0.17 2.15 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.26 0.00 2.15 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.15 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.04 0.78 library hold time
+ 0.78 data required time
+-----------------------------------------------------------------------------
+ 0.78 data required time
+ -2.15 data arrival time
+-----------------------------------------------------------------------------
+ 1.37 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.71 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 1.45 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.23 1.68 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.68 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.12 0.34 2.03 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.12 0.00 2.03 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.12 0.20 2.22 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.12 0.00 2.22 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.22 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.03 0.77 clock reconvergence pessimism
+ 0.08 0.84 library hold time
+ 0.84 data required time
+-----------------------------------------------------------------------------
+ 0.84 data required time
+ -2.22 data arrival time
+-----------------------------------------------------------------------------
+ 1.38 slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.98 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.98 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.28 0.73 8.52 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.28 0.00 8.52 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.76 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.76 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.26 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.26 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.13 0.23 9.49 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.13 0.00 9.49 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.49 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.22 30.02 library setup time
+ 30.02 data required time
+-----------------------------------------------------------------------------
+ 30.02 data required time
+ -9.49 data arrival time
+-----------------------------------------------------------------------------
+ 20.53 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.49 0.98 1.53 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.49 0.00 1.53 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.35 0.31 1.84 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.35 0.00 1.84 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.62 0.46 2.29 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.62 0.00 2.29 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.18 2.48 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 2.48 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.29 0.25 2.73 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 net11 (net)
+ 0.29 0.00 2.73 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.46 3.19 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[1] (net)
+ 0.33 0.00 3.19 ^ io_oeb[1] (out)
+ 3.19 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -3.19 data arrival time
+-----------------------------------------------------------------------------
+ 20.56 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.49 0.98 1.53 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.49 0.00 1.53 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.35 0.31 1.84 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.35 0.00 1.84 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.62 0.46 2.29 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.62 0.00 2.29 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.18 2.48 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 2.48 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.23 2.71 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 net10 (net)
+ 0.27 0.00 2.71 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.46 3.17 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[0] (net)
+ 0.33 0.00 3.17 ^ io_oeb[0] (out)
+ 3.17 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -3.17 data arrival time
+-----------------------------------------------------------------------------
+ 20.58 slack (MET)
+
+
+Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.28 0.85 1.40 ^ _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_water_synth_0 (net)
+ 0.28 0.00 1.40 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.29 0.25 1.65 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 3 0.01 _000_ (net)
+ 0.29 0.00 1.65 v _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.25 0.54 2.19 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 3 0.01 _001_ (net)
+ 0.25 0.00 2.19 v _118_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.22 0.20 2.39 ^ _118_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 1 0.01 net12 (net)
+ 0.22 0.00 2.39 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.45 2.83 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_out[0] (net)
+ 0.33 0.00 2.84 ^ io_out[0] (out)
+ 2.84 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.84 data arrival time
+-----------------------------------------------------------------------------
+ 20.91 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ wbs_we_i (in)
+ 1 0.00 wbs_we_i (net)
+ 0.10 0.00 6.03 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.40 0.38 6.42 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 net9 (net)
+ 0.40 0.00 6.42 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.26 0.23 6.65 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.26 0.00 6.65 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.32 0.47 7.12 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.03 _004_ (net)
+ 0.32 0.00 7.12 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.30 0.58 7.70 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.30 0.00 7.71 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.42 0.33 8.03 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.42 0.00 8.03 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.17 0.12 8.15 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.17 0.00 8.15 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.28 8.43 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 8.43 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.26 8.69 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 8.69 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.27 0.21 8.90 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 fsm_plant_opt.tmp3553 (net)
+ 0.27 0.00 8.90 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.90 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.24 30.00 library setup time
+ 30.00 data required time
+-----------------------------------------------------------------------------
+ 30.00 data required time
+ -8.90 data arrival time
+-----------------------------------------------------------------------------
+ 21.10 slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.98 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.98 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.28 0.73 8.52 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.28 0.00 8.52 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.76 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.76 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.26 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.26 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.13 0.23 9.49 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.13 0.00 9.49 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.49 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.22 30.02 library setup time
+ 30.02 data required time
+-----------------------------------------------------------------------------
+ 30.02 data required time
+ -9.49 data arrival time
+-----------------------------------------------------------------------------
+ 20.53 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 20.53
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 0.75
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_129_/CLK ^
+ 0.55
+_126_/CLK ^
+ 0.50 -0.03 0.02
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 1.08e-04 6.56e-06 1.22e-09 1.14e-04 19.6%
+Combinational 3.76e-04 9.18e-05 1.91e-07 4.68e-04 80.4%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 4.84e-04 9.83e-05 1.92e-07 5.82e-04 100.0%
+ 83.1% 16.9% 0.0%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 18295 u^2 4% utilization.
+area_report_end
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/cts/11-plant_example.resized.odb...
+Writing netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/cts/11-plant_example.resized.nl.v...
+Writing powered netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/cts/11-plant_example.resized.pnl.v...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/cts/11-plant_example.resized.def...
+Writing timing constraints to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/cts/11-plant_example.resized.sdc...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/floorplan/3-initial_fp.log b/openlane/user_proj_example/runs/user_proj_example/logs/floorplan/3-initial_fp.log
new file mode 100644
index 0000000..a25a0bb
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/floorplan/3-initial_fp.log
@@ -0,0 +1,16 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO ODB-0222] Reading LEF file: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/merged.nom.lef
+[INFO ODB-0223] Created 13 technology layers
+[INFO ODB-0224] Created 60 technology vias
+[INFO ODB-0225] Created 229 library cells
+[INFO ODB-0226] Finished LEF file: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/merged.nom.lef
+Reading netlist...
+[INFO IFP-0001] Added 145 rows of 1583 sites.
+[INFO IFP-0030] Inserted 0 tiecells using gf180mcu_fd_sc_mcu7t5v0__tiel/ZN.
+[INFO IFP-0030] Inserted 0 tiecells using gf180mcu_fd_sc_mcu7t5v0__tieh/Z.
+[INFO] Extracting DIE_AREA and CORE_AREA from the floorplan
+[INFO] Floorplanned on a die area of 0.0 0.0 900.0 600.0 (microns). Saving to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/floorplan/3-initial_fp_die_area.rpt.
+[INFO] Floorplanned on a core area of 6.72 15.68 893.2 584.08 (microns). Saving to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/floorplan/3-initial_fp_core_area.rpt.
+[WARNING] Did not save OpenROAD database!
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/floorplan/4-place_io.log b/openlane/user_proj_example/runs/user_proj_example/logs/floorplan/4-place_io.log
new file mode 100644
index 0000000..be0b5a8
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/floorplan/4-place_io.log
@@ -0,0 +1,33 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Top-level design name: plant_example
+Block boundaries: 0 0 1800000 1200000
+Horizontal Tracks Origin: 560, Count: 1071, Step: 1120
+Vertical Tracks Origin: 560, Count: 1607, Step: 1120
+Placement details for the #N side
+Virtual pin count: 0
+Actual pin count: 114
+Total pin count: 114
+Tracks count: 1607
+Tracks per pin: 14
+Used tracks count: 1583
+Unused track count: 24
+Starting track index: 12
+Placement Map:
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+Indices of used tracks: [12, 26, 40, 54, 68, 82, 96, 110, 124, 138, 152, 166, 180, 194, 208, 222, 236, 250, 264, 278, 292, 306, 320, 334, 348, 362, 376, 390, 404, 418, 432, 446, 460, 474, 488, 502, 516, 530, 544, 558, 572, 586, 600, 614, 628, 642, 656, 670, 684, 698, 712, 726, 740, 754, 768, 782, 796, 810, 824, 838, 852, 866, 880, 894, 908, 922, 936, 950, 964, 978, 992, 1006, 1020, 1034, 1048, 1062, 1076, 1090, 1104, 1118, 1132, 1146, 1160, 1174, 1188, 1202, 1216, 1230, 1244, 1258, 1272, 1286, 1300, 1314, 1328, 1342, 1356, 1370, 1384, 1398, 1412, 1426, 1440, 1454, 1468, 1482, 1496, 1510, 1524, 1538, 1552, 1566, 1580, 1594]
+---
+Placement details for the #S side
+Virtual pin count: 0
+Actual pin count: 7
+Total pin count: 7
+Tracks count: 1607
+Tracks per pin: 229
+Used tracks count: 1375
+Unused track count: 232
+Starting track index: 116
+Placement Map:
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1362480, 1363600, 1364720, 1365840, 1366960, 1368080, 1369200, 1370320, 1371440, 1372560, 1373680, 1374800, 1375920, 1377040, 1378160, 1379280, 1380400, 1381520, 1382640, 1383760, 1384880, 1386000, 1387120, 1388240, 1389360, 1390480, 1391600, 1392720, 1393840, 1394960, 1396080, 1397200, 1398320, 1399440, 1400560, 1401680, 1402800, 1403920, 1405040, 1406160, 1407280, 1408400, 1409520, 1410640, 1411760, [91m1412880[0m, 1414000, 1415120, 1416240, 1417360, 1418480, 1419600, 1420720, 1421840, 1422960, 1424080, 1425200, 1426320, 1427440, 1428560, 1429680, 1430800, 1431920, 1433040, 1434160, 1435280, 1436400, 1437520, 1438640, 1439760, 1440880, 1442000, 1443120, 1444240, 1445360, 1446480, 1447600, 1448720, 1449840, 1450960, 1452080, 1453200, 1454320, 1455440, 1456560, 1457680, 1458800, 1459920, 1461040, 1462160, 1463280, 1464400, 1465520, 1466640, 1467760, 1468880, 1470000, 1471120, 1472240, 1473360, 1474480, 1475600, 1476720, 1477840, 1478960, 1480080, 1481200, 1482320, 1483440, 1484560, 1485680, 1486800, 1487920, 1489040, 1490160, 1491280, 1492400, 1493520, 1494640, 1495760, 1496880, 1498000, 1499120, 1500240, 1501360, 1502480, 1503600, 1504720, 1505840, 1506960, 1508080, 1509200, 1510320, 1511440, 1512560, 1513680, 1514800, 1515920, 1517040, 1518160, 1519280, 1520400, 1521520, 1522640, 1523760, 1524880, 1526000, 1527120, 1528240, 1529360, 1530480, 1531600, 1532720, 1533840, 1534960, 1536080, 1537200, 1538320, 1539440, 1540560, 1541680, 1542800, 1543920, 1545040, 1546160, 1547280, 1548400, 1549520, 1550640, 1551760, 1552880, 1554000, 1555120, 1556240, 1557360, 1558480, 1559600, 1560720, 1561840, 1562960, 1564080, 1565200, 1566320, 1567440, 1568560, 1569680, 1570800, 1571920, 1573040, 1574160, 1575280, 1576400, 1577520, 1578640, 1579760, 1580880, 1582000, 1583120, 1584240, 1585360, 1586480, 1587600, 1588720, 1589840, 1590960, 1592080, 1593200, 1594320, 1595440, 1596560, 1597680, 1598800, 1599920, 1601040, 1602160, 1603280, 1604400, 1605520, 1606640, 1607760, 1608880, 1610000, 1611120, 1612240, 1613360, 1614480, 1615600, 1616720, 1617840, 1618960, 1620080, 1621200, 1622320, 1623440, 1624560, 1625680, 1626800, 1627920, 1629040, 1630160, 1631280, 1632400, 1633520, 1634640, 1635760, 1636880, 1638000, 1639120, 1640240, 1641360, 1642480, 1643600, 1644720, 1645840, 1646960, 1648080, 1649200, 1650320, 1651440, 1652560, 1653680, 1654800, 1655920, 1657040, 1658160, 1659280, 1660400, 1661520, 1662640, 1663760, 1664880, 1666000, 1667120, 1668240, [91m1669360[0m, 1670480, 1671600, 1672720, 1673840, 1674960, 1676080, 1677200, 1678320, 1679440, 1680560, 1681680, 1682800, 1683920, 1685040, 1686160, 1687280, 1688400, 1689520, 1690640, 1691760, 1692880, 1694000, 1695120, 1696240, 1697360, 1698480, 1699600, 1700720, 1701840, 1702960, 1704080, 1705200, 1706320, 1707440, 1708560, 1709680, 1710800, 1711920, 1713040, 1714160, 1715280, 1716400, 1717520, 1718640, 1719760, 1720880, 1722000, 1723120, 1724240, 1725360, 1726480, 1727600, 1728720, 1729840, 1730960, 1732080, 1733200, 1734320, 1735440, 1736560, 1737680, 1738800, 1739920, 1741040, 1742160, 1743280, 1744400, 1745520, 1746640, 1747760, 1748880, 1750000, 1751120, 1752240, 1753360, 1754480, 1755600, 1756720, 1757840, 1758960, 1760080, 1761200, 1762320, 1763440, 1764560, 1765680, 1766800, 1767920, 1769040, 1770160, 1771280, 1772400, 1773520, 1774640, 1775760, 1776880, 1778000, 1779120, 1780240, 1781360, 1782480, 1783600, 1784720, 1785840, 1786960, 1788080, 1789200, 1790320, 1791440, 1792560, 1793680, 1794800, 1795920, 1797040, 1798160, 1799280, ]
+Indices of used tracks: [116, 345, 574, 803, 1032, 1261, 1490]
+---
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/floorplan/5-tap.log b/openlane/user_proj_example/runs/user_proj_example/logs/floorplan/5-tap.log
new file mode 100644
index 0000000..4639956
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/floorplan/5-tap.log
@@ -0,0 +1,7 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO TAP-0004] Inserted 290 endcaps.
+[INFO TAP-0005] Inserted 3236 tapcells.
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/floorplan/plant_example.odb...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/floorplan/plant_example.def...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/floorplan/6-pdn.log b/openlane/user_proj_example/runs/user_proj_example/logs/floorplan/6-pdn.log
new file mode 100644
index 0000000..26c992a
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/floorplan/6-pdn.log
@@ -0,0 +1,33 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO PDN-0001] Inserting grid: stdcell_grid
+[WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area.
+[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
+[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
+[WARNING PSM-0019] Voltage on net vdd is not explicitly set.
+[WARNING PSM-0022] Using voltage 0.000V for VDD network.
+[WARNING PSM-0065] VSRC location not specified, using default checkerboard pattern with one VDD every size bumps in x-direction and one in two bumps in the y-direction
+[INFO PSM-0076] Setting metal node density to be standard cell height times 5.
+[WARNING PSM-0030] VSRC location at (99.960um, 89.880um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (176.640um, 90.160um).
+[WARNING PSM-0030] VSRC location at (379.960um, 229.880um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (330.240um, 231.280um).
+[WARNING PSM-0030] VSRC location at (659.960um, 369.880um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (637.440um, 372.400um).
+[WARNING PSM-0030] VSRC location at (99.960um, 509.880um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (176.640um, 513.520um).
+[INFO PSM-0031] Number of PDN nodes on net vdd = 4830.
+[INFO PSM-0064] Number of voltage sources = 4.
+[INFO PSM-0040] All PDN stripes on net vdd are connected.
+[WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area.
+[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
+[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
+[WARNING PSM-0019] Voltage on net vss is not explicitly set.
+[WARNING PSM-0021] Using voltage 0.000V for ground network.
+[WARNING PSM-0065] VSRC location not specified, using default checkerboard pattern with one VDD every size bumps in x-direction and one in two bumps in the y-direction
+[INFO PSM-0076] Setting metal node density to be standard cell height times 5.
+[WARNING PSM-0030] VSRC location at (379.960um, 229.880um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (407.040um, 227.360um).
+[WARNING PSM-0030] VSRC location at (659.960um, 369.880um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (714.240um, 368.480um).
+[INFO PSM-0031] Number of PDN nodes on net vss = 4830.
+[INFO PSM-0064] Number of voltage sources = 4.
+[INFO PSM-0040] All PDN stripes on net vss are connected.
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/floorplan/6-pdn.odb...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/floorplan/6-pdn.def...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/placement/7-global.log b/openlane/user_proj_example/runs/user_proj_example/logs/placement/7-global.log
new file mode 100644
index 0000000..ebb48d3
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/placement/7-global.log
@@ -0,0 +1,708 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO]: Setting RC values...
+[INFO]: Setting signal min routing layer to: Metal2 and clock min routing layer to Metal2.
+[INFO]: Setting signal max routing layer to: Metal4 and clock max routing layer to Metal4.
+[INFO GPL-0002] DBU: 2000
+[INFO GPL-0003] SiteSize: 1120 7840
+[INFO GPL-0004] CoreAreaLxLy: 13440 31360
+[INFO GPL-0005] CoreAreaUxUy: 1786400 1168160
+[INFO GPL-0006] NumInstances: 3382
+[INFO GPL-0007] NumPlaceInstances: 146
+[INFO GPL-0008] NumFixedInstances: 3236
+[INFO GPL-0009] NumDummyInstances: 0
+[INFO GPL-0010] NumNets: 191
+[INFO GPL-0011] NumPins: 440
+[INFO GPL-0012] DieAreaLxLy: 0 0
+[INFO GPL-0013] DieAreaUxUy: 1800000 1200000
+[INFO GPL-0014] CoreAreaLxLy: 13440 31360
+[INFO GPL-0015] CoreAreaUxUy: 1786400 1168160
+[INFO GPL-0016] CoreArea: 2015500928000
+[INFO GPL-0017] NonPlaceInstsArea: 56829337600
+[INFO GPL-0018] PlaceInstsArea: 8280294400
+[INFO GPL-0019] Util(%): 0.42
+[INFO GPL-0020] StdInstsArea: 8280294400
+[INFO GPL-0021] MacroInstsArea: 0
+[InitialPlace] Iter: 1 CG residual: 0.00004492 HPWL: 171948160
+[InitialPlace] Iter: 2 CG residual: 0.00000007 HPWL: 18828598
+[InitialPlace] Iter: 3 CG residual: 0.00000010 HPWL: 18094725
+[InitialPlace] Iter: 4 CG residual: 0.00000008 HPWL: 16792716
+[InitialPlace] Iter: 5 CG residual: 0.00000006 HPWL: 16166592
+[INFO GPL-0031] FillerInit: NumGCells: 18367
+[INFO GPL-0032] FillerInit: NumGNets: 191
+[INFO GPL-0033] FillerInit: NumGPins: 440
+[INFO GPL-0023] TargetDensity: 0.45
+[INFO GPL-0024] AveragePlaceInstArea: 56714345
+[INFO GPL-0025] IdealBinArea: 126031880
+[INFO GPL-0026] IdealBinCnt: 15991
+[INFO GPL-0027] TotalBinArea: 2015500928000
+[INFO GPL-0028] BinCnt: 64 64
+[INFO GPL-0029] BinSize: 27703 17763
+[INFO GPL-0030] NumBins: 4096
+[NesterovSolve] Iter: 1 overflow: 0.443012 HPWL: 16065417
+[INFO GPL-0100] worst slack 2.07e-08
+[INFO GPL-0103] Weighted 84 nets.
+[NesterovSolve] Snapshot saved at iter = 0
+[NesterovSolve] Iter: 10 overflow: 0.354634 HPWL: 17664828
+[NesterovSolve] Iter: 20 overflow: 0.344428 HPWL: 20716303
+[NesterovSolve] Iter: 30 overflow: 0.325905 HPWL: 22549429
+[NesterovSolve] Iter: 40 overflow: 0.314579 HPWL: 24561399
+[NesterovSolve] Iter: 50 overflow: 0.309204 HPWL: 26517559
+[NesterovSolve] Iter: 60 overflow: 0.315056 HPWL: 26478900
+[NesterovSolve] Iter: 70 overflow: 0.306594 HPWL: 26309663
+[NesterovSolve] Iter: 80 overflow: 0.306286 HPWL: 26181186
+[NesterovSolve] Iter: 90 overflow: 0.293182 HPWL: 26034004
+[NesterovSolve] Iter: 100 overflow: 0.293483 HPWL: 25828946
+[NesterovSolve] Iter: 110 overflow: 0.289584 HPWL: 25609336
+[NesterovSolve] Iter: 120 overflow: 0.296372 HPWL: 25396208
+[NesterovSolve] Iter: 130 overflow: 0.308593 HPWL: 25197154
+[NesterovSolve] Iter: 140 overflow: 0.307521 HPWL: 25008216
+[NesterovSolve] Iter: 150 overflow: 0.296831 HPWL: 24836567
+[NesterovSolve] Iter: 160 overflow: 0.291939 HPWL: 24637780
+[NesterovSolve] Iter: 170 overflow: 0.296774 HPWL: 24387233
+[NesterovSolve] Iter: 180 overflow: 0.306911 HPWL: 24109242
+[NesterovSolve] Iter: 190 overflow: 0.289654 HPWL: 23880376
+[NesterovSolve] Iter: 200 overflow: 0.294889 HPWL: 23668111
+[NesterovSolve] Iter: 210 overflow: 0.297489 HPWL: 23433050
+[NesterovSolve] Iter: 220 overflow: 0.292626 HPWL: 23189726
+[NesterovSolve] Iter: 230 overflow: 0.293975 HPWL: 22951320
+[NesterovSolve] Iter: 240 overflow: 0.296887 HPWL: 22686336
+[NesterovSolve] Iter: 250 overflow: 0.289627 HPWL: 22411999
+[NesterovSolve] Iter: 260 overflow: 0.298275 HPWL: 22132671
+[NesterovSolve] Iter: 270 overflow: 0.297626 HPWL: 21831989
+[NesterovSolve] Iter: 280 overflow: 0.318725 HPWL: 21544996
+[NesterovSolve] Iter: 290 overflow: 0.301481 HPWL: 21305859
+[NesterovSolve] Iter: 300 overflow: 0.310825 HPWL: 21114133
+[NesterovSolve] Iter: 310 overflow: 0.337337 HPWL: 21003839
+[NesterovSolve] Iter: 320 overflow: 0.321479 HPWL: 20946445
+[NesterovSolve] Iter: 330 overflow: 0.284734 HPWL: 20891813
+[INFO GPL-0100] worst slack 2.06e-08
+[INFO GPL-0103] Weighted 85 nets.
+[NesterovSolve] Iter: 340 overflow: 0.277501 HPWL: 20781210
+[NesterovSolve] Iter: 350 overflow: 0.266736 HPWL: 20637821
+[NesterovSolve] Iter: 360 overflow: 0.273328 HPWL: 20520112
+[NesterovSolve] Iter: 370 overflow: 0.252196 HPWL: 20450739
+[NesterovSolve] Iter: 380 overflow: 0.249151 HPWL: 20342874
+[NesterovSolve] Iter: 390 overflow: 0.24011 HPWL: 20275732
+[NesterovSolve] Iter: 400 overflow: 0.205939 HPWL: 20398845
+[INFO GPL-0100] worst slack 2.06e-08
+[INFO GPL-0103] Weighted 85 nets.
+[INFO GPL-0075] Routability numCall: 1 inflationIterCnt: 1 bloatIterCnt: 0
+[INFO GPL-0036] TileLxLy: 0 0
+[INFO GPL-0037] TileSize: 16800 16800
+[INFO GPL-0038] TileCnt: 107 71
+[INFO GPL-0039] numRoutingLayers: 5
+[INFO GPL-0040] NumTiles: 7597
+[INFO GPL-0063] TotalRouteOverflowH2: 0.0
+[INFO GPL-0064] TotalRouteOverflowV2: 0.0
+[INFO GPL-0065] OverflowTileCnt2: 0
+[INFO GPL-0066] 0.5%RC: 0.7333333285649618
+[INFO GPL-0067] 1.0%RC: 0.6140939601315748
+[INFO GPL-0068] 2.0%RC: 0.5216450239672805
+[INFO GPL-0069] 5.0%RC: 0.4658259565055852
+[INFO GPL-0070] 0.5rcK: 1.0
+[INFO GPL-0071] 1.0rcK: 1.0
+[INFO GPL-0072] 2.0rcK: 0.0
+[INFO GPL-0073] 5.0rcK: 0.0
+[INFO GPL-0074] FinalRC: 0.6737136
+[NesterovSolve] Iter: 410 overflow: 0.149291 HPWL: 20612506
+[INFO GPL-0100] worst slack 2.06e-08
+[INFO GPL-0103] Weighted 84 nets.
+[NesterovSolve] Iter: 420 overflow: 0.128436 HPWL: 20608427
+[NesterovSolve] Iter: 430 overflow: 0.141193 HPWL: 20370520
+[NesterovSolve] Iter: 440 overflow: 0.137537 HPWL: 20309362
+[NesterovSolve] Iter: 450 overflow: 0.106591 HPWL: 20381060
+[NesterovSolve] Finished with Overflow: 0.099047
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/placement/7-global.odb...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/placement/7-global.def...
+[INFO]: Setting RC values...
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.20 0.70 0.70 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.20 0.00 0.70 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.47 0.34 1.04 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 4 0.02 _002_ (net)
+ 0.47 0.00 1.04 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.16 0.12 1.15 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp3555 (net)
+ 0.16 0.00 1.15 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.15 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.08 0.33 library hold time
+ 0.33 data required time
+-----------------------------------------------------------------------------
+ 0.33 data required time
+ -1.15 data arrival time
+-----------------------------------------------------------------------------
+ 0.83 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.20 0.69 0.69 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.20 0.00 0.70 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.22 0.17 0.87 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.01 _033_ (net)
+ 0.22 0.00 0.87 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.16 0.12 0.99 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _041_ (net)
+ 0.16 0.00 0.99 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.13 1.12 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _045_ (net)
+ 0.16 0.00 1.12 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.14 0.11 1.24 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2410 (net)
+ 0.14 0.00 1.24 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.24 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.09 0.34 library hold time
+ 0.34 data required time
+-----------------------------------------------------------------------------
+ 0.34 data required time
+ -1.24 data arrival time
+-----------------------------------------------------------------------------
+ 0.90 slack (MET)
+
+
+Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.27 0.78 0.78 ^ _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_temperature_synth_2 (net)
+ 0.27 0.00 0.78 ^ _070_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.28 0.24 1.02 v _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.28 0.00 1.02 v _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand4_1)
+ 0.20 0.22 1.24 ^ _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand4_1)
+ 1 0.00 _017_ (net)
+ 0.20 0.00 1.24 ^ _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.16 0.28 1.52 ^ _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _018_ (net)
+ 0.16 0.00 1.52 ^ _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.13 0.11 1.63 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.13 0.00 1.63 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.63 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.09 0.34 library hold time
+ 0.34 data required time
+-----------------------------------------------------------------------------
+ 0.34 data required time
+ -1.63 data arrival time
+-----------------------------------------------------------------------------
+ 1.29 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.20 0.70 0.70 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.20 0.00 0.70 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.47 0.34 1.04 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 4 0.02 _002_ (net)
+ 0.47 0.00 1.04 ^ _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.19 0.20 1.24 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 2 0.01 _048_ (net)
+ 0.19 0.00 1.24 v _121_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.10 0.24 1.48 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.10 0.00 1.48 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.15 0.26 1.74 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.15 0.00 1.74 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.74 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.08 0.33 library hold time
+ 0.33 data required time
+-----------------------------------------------------------------------------
+ 0.33 data required time
+ -1.74 data arrival time
+-----------------------------------------------------------------------------
+ 1.41 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.20 0.70 0.70 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.20 0.00 0.70 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.47 0.34 1.04 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 4 0.02 _002_ (net)
+ 0.47 0.00 1.04 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.24 1.28 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.28 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.11 0.34 1.62 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.11 0.00 1.62 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.11 0.23 1.85 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.11 0.00 1.85 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.85 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.09 0.34 library hold time
+ 0.34 data required time
+-----------------------------------------------------------------------------
+ 0.34 data required time
+ -1.85 data arrival time
+-----------------------------------------------------------------------------
+ 1.51 slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.39 0.22 6.22 ^ wbs_we_i (in)
+ 4 0.02 wbs_we_i (net)
+ 0.39 0.00 6.22 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.21 0.18 6.40 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.21 0.00 6.40 v _072_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 0.78 0.43 6.83 ^ _072_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 2 0.01 _014_ (net)
+ 0.78 0.00 6.83 ^ _073_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.34 0.40 7.23 ^ _073_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 _015_ (net)
+ 0.34 0.00 7.23 ^ _097_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.27 0.57 7.80 ^ _097_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _036_ (net)
+ 0.27 0.00 7.80 ^ _114_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.25 0.21 8.01 v _114_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 _052_ (net)
+ 0.25 0.00 8.01 v _115_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.21 8.23 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.23 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.17 0.49 8.72 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.17 0.00 8.72 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.14 0.23 8.95 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.14 0.00 8.95 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.95 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.21 29.54 library setup time
+ 29.54 data required time
+-----------------------------------------------------------------------------
+ 29.54 data required time
+ -8.95 data arrival time
+-----------------------------------------------------------------------------
+ 20.59 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.39 0.22 6.22 ^ wbs_we_i (in)
+ 4 0.02 wbs_we_i (net)
+ 0.39 0.00 6.22 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.21 0.18 6.40 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.21 0.00 6.40 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.21 0.37 6.77 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 _004_ (net)
+ 0.21 0.00 6.77 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.29 0.55 7.32 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.29 0.00 7.32 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.44 0.32 7.65 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.44 0.00 7.65 ^ _088_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.46 0.24 7.89 v _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _029_ (net)
+ 0.46 0.00 7.89 v _089_/S (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 0.13 0.42 8.31 v _089_/Z (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 1 0.00 _030_ (net)
+ 0.13 0.00 8.31 v _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.33 0.23 8.54 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.33 0.00 8.54 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.54 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.23 29.52 library setup time
+ 29.52 data required time
+-----------------------------------------------------------------------------
+ 29.52 data required time
+ -8.54 data arrival time
+-----------------------------------------------------------------------------
+ 20.98 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.39 0.22 6.22 ^ wbs_we_i (in)
+ 4 0.02 wbs_we_i (net)
+ 0.39 0.00 6.22 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.21 0.18 6.40 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.21 0.00 6.40 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.21 0.37 6.77 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 _004_ (net)
+ 0.21 0.00 6.77 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.29 0.55 7.32 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.29 0.00 7.32 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.44 0.32 7.65 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.44 0.00 7.65 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.17 0.12 7.76 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.17 0.00 7.76 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.10 0.28 8.04 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.10 0.00 8.04 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.15 0.29 8.33 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.15 0.00 8.33 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.25 0.20 8.53 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 fsm_plant_opt.tmp3553 (net)
+ 0.25 0.00 8.53 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.53 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.22 29.53 library setup time
+ 29.53 data required time
+-----------------------------------------------------------------------------
+ 29.53 data required time
+ -8.53 data arrival time
+-----------------------------------------------------------------------------
+ 21.00 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.30 0.88 0.88 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.30 0.00 0.88 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.31 0.27 1.14 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.31 0.00 1.14 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.61 0.44 1.59 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.61 0.00 1.59 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.28 0.19 1.78 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.28 0.00 1.78 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1.43 0.94 2.72 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.07 io_oeb[0] (net)
+ 1.43 0.01 2.73 ^ io_oeb[0] (out)
+ 2.73 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.73 data arrival time
+-----------------------------------------------------------------------------
+ 21.02 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.30 0.88 0.88 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.30 0.00 0.88 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.31 0.27 1.14 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.31 0.00 1.14 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.61 0.44 1.59 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.61 0.00 1.59 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.28 0.19 1.78 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.28 0.00 1.78 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__inv_1)
+ 1.36 0.91 2.69 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__inv_1)
+ 2 0.08 io_oeb[1] (net)
+ 1.36 0.01 2.70 ^ io_oeb[1] (out)
+ 2.70 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.70 data arrival time
+-----------------------------------------------------------------------------
+ 21.05 slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.39 0.22 6.22 ^ wbs_we_i (in)
+ 4 0.02 wbs_we_i (net)
+ 0.39 0.00 6.22 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.21 0.18 6.40 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.21 0.00 6.40 v _072_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 0.78 0.43 6.83 ^ _072_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 2 0.01 _014_ (net)
+ 0.78 0.00 6.83 ^ _073_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.34 0.40 7.23 ^ _073_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 _015_ (net)
+ 0.34 0.00 7.23 ^ _097_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.27 0.57 7.80 ^ _097_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _036_ (net)
+ 0.27 0.00 7.80 ^ _114_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.25 0.21 8.01 v _114_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 _052_ (net)
+ 0.25 0.00 8.01 v _115_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.21 8.23 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.23 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.17 0.49 8.72 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.17 0.00 8.72 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.14 0.23 8.95 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.14 0.00 8.95 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.95 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.21 29.54 library setup time
+ 29.54 data required time
+-----------------------------------------------------------------------------
+ 29.54 data required time
+ -8.95 data arrival time
+-----------------------------------------------------------------------------
+ 20.59 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 20.59
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 0.83
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_125_/CLK ^
+ 0.05
+_125_/CLK ^
+ 0.05 0.00 0.00
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 1.09e-04 4.77e-06 1.22e-09 1.13e-04 68.5%
+Combinational 2.30e-05 2.89e-05 1.87e-07 5.21e-05 31.5%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 1.32e-04 3.36e-05 1.88e-07 1.65e-04 100.0%
+ 79.5% 20.3% 0.1%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 17551 u^2 3% utilization.
+area_report_end
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/placement/7-global.odb...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/placement/7-global.def...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/placement/8-resizer.log b/openlane/user_proj_example/runs/user_proj_example/logs/placement/8-resizer.log
new file mode 100644
index 0000000..ce81104
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/placement/8-resizer.log
@@ -0,0 +1,639 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO]: Setting RC values...
+[INFO RSZ-0027] Inserted 9 input buffers.
+[INFO RSZ-0028] Inserted 3 output buffers.
+[INFO RSZ-0058] Using max wire length 18670um.
+[INFO RSZ-0039] Resized 22 instances.
+[INFO RSZ-0042] Inserted 73 tie gf180mcu_fd_sc_mcu7t5v0__tiel instances.
+Placement Analysis
+---------------------------------
+total displacement 324.9 u
+average displacement 0.1 u
+max displacement 12.9 u
+original HPWL 9962.4 u
+legalized HPWL 10116.3 u
+delta HPWL 2 %
+
+[INFO DPL-0020] Mirrored 109 instances
+[INFO DPL-0021] HPWL before 10116.3 u
+[INFO DPL-0022] HPWL after 9993.9 u
+[INFO DPL-0023] HPWL delta -1.2 %
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/placement/8-resizer.odb...
+Writing netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/placement/8-resizer.nl.v...
+Writing powered netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/placement/8-resizer.pnl.v...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/placement/8-resizer.def...
+Writing timing constraints to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/placement/8-resizer.sdc...
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.73 0.73 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 0.73 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 0.97 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 0.97 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.15 0.12 1.09 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp3555 (net)
+ 0.15 0.00 1.09 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.09 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.08 0.33 library hold time
+ 0.33 data required time
+-----------------------------------------------------------------------------
+ 0.33 data required time
+ -1.09 data arrival time
+-----------------------------------------------------------------------------
+ 0.76 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.31 0.77 0.77 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.31 0.00 0.77 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.24 0.20 0.97 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.01 _033_ (net)
+ 0.24 0.00 0.97 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.16 0.12 1.10 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _041_ (net)
+ 0.16 0.00 1.10 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.13 1.23 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _045_ (net)
+ 0.16 0.00 1.23 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.14 0.11 1.35 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2410 (net)
+ 0.14 0.00 1.35 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.35 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.09 0.34 library hold time
+ 0.34 data required time
+-----------------------------------------------------------------------------
+ 0.34 data required time
+ -1.35 data arrival time
+-----------------------------------------------------------------------------
+ 1.01 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.73 0.73 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 0.73 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 0.97 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 0.97 ^ _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.19 0.18 1.16 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 2 0.01 _048_ (net)
+ 0.19 0.00 1.16 v _121_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.25 1.40 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 1.40 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.23 1.64 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 1.64 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.64 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.07 0.32 library hold time
+ 0.32 data required time
+-----------------------------------------------------------------------------
+ 0.32 data required time
+ -1.64 data arrival time
+-----------------------------------------------------------------------------
+ 1.31 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.73 0.73 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 0.73 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 0.97 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 0.97 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.23 1.20 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.20 v _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.12 0.29 1.49 v _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _018_ (net)
+ 0.12 0.00 1.49 v _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.26 0.17 1.67 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.26 0.00 1.67 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.67 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.05 0.30 library hold time
+ 0.30 data required time
+-----------------------------------------------------------------------------
+ 0.30 data required time
+ -1.67 data arrival time
+-----------------------------------------------------------------------------
+ 1.37 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.73 0.73 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 0.73 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.24 0.97 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 0.97 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.23 1.20 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.20 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.12 0.34 1.55 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.12 0.00 1.55 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.12 0.20 1.74 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.12 0.00 1.74 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.74 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.09 0.34 library hold time
+ 0.34 data required time
+-----------------------------------------------------------------------------
+ 0.34 data required time
+ -1.74 data arrival time
+-----------------------------------------------------------------------------
+ 1.40 slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.98 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.98 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.28 0.73 8.52 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.28 0.00 8.52 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.76 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.76 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.26 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.26 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.13 0.23 9.49 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.13 0.00 9.49 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.49 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.21 29.54 library setup time
+ 29.54 data required time
+-----------------------------------------------------------------------------
+ 29.54 data required time
+ -9.49 data arrival time
+-----------------------------------------------------------------------------
+ 20.05 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ wbs_we_i (in)
+ 1 0.00 wbs_we_i (net)
+ 0.10 0.00 6.03 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.40 0.38 6.42 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 net9 (net)
+ 0.40 0.00 6.42 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.26 0.23 6.65 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.26 0.00 6.65 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.32 0.47 7.12 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.03 _004_ (net)
+ 0.32 0.00 7.12 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.30 0.58 7.70 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.30 0.00 7.71 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.42 0.33 8.03 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.42 0.00 8.03 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.17 0.12 8.15 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.17 0.00 8.15 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.28 8.43 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 8.43 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.26 8.69 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 8.69 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.26 0.21 8.90 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 fsm_plant_opt.tmp3553 (net)
+ 0.26 0.00 8.90 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.90 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.22 29.53 library setup time
+ 29.53 data required time
+-----------------------------------------------------------------------------
+ 29.53 data required time
+ -8.90 data arrival time
+-----------------------------------------------------------------------------
+ 20.62 slack (MET)
+
+
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.98 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.98 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.28 0.73 8.52 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.28 0.00 8.52 v _106_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.21 0.21 8.73 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _045_ (net)
+ 0.21 0.00 8.73 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.23 0.13 8.86 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2410 (net)
+ 0.23 0.00 8.86 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.86 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.26 29.49 library setup time
+ 29.49 data required time
+-----------------------------------------------------------------------------
+ 29.49 data required time
+ -8.86 data arrival time
+-----------------------------------------------------------------------------
+ 20.63 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ wbs_we_i (in)
+ 1 0.00 wbs_we_i (net)
+ 0.10 0.00 6.03 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.40 0.38 6.42 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 net9 (net)
+ 0.40 0.00 6.42 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.26 0.23 6.65 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.26 0.00 6.65 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.32 0.47 7.12 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.03 _004_ (net)
+ 0.32 0.00 7.12 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.30 0.58 7.70 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.30 0.00 7.71 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.42 0.33 8.03 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.42 0.00 8.03 ^ _088_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.30 0.24 8.27 v _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _029_ (net)
+ 0.30 0.00 8.27 v _089_/S (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 0.11 0.44 8.71 ^ _089_/Z (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 1 0.00 _030_ (net)
+ 0.11 0.00 8.71 ^ _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.31 0.12 8.83 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.31 0.00 8.83 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.83 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.28 29.47 library setup time
+ 29.47 data required time
+-----------------------------------------------------------------------------
+ 29.47 data required time
+ -8.83 data arrival time
+-----------------------------------------------------------------------------
+ 20.64 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ wbs_we_i (in)
+ 1 0.00 wbs_we_i (net)
+ 0.10 0.00 6.03 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.40 0.38 6.42 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 net9 (net)
+ 0.40 0.00 6.42 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.26 0.23 6.65 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.26 0.00 6.65 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.32 0.47 7.12 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.03 _004_ (net)
+ 0.32 0.00 7.12 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.30 0.58 7.70 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.30 0.00 7.71 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.42 0.33 8.03 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.42 0.00 8.03 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.17 0.12 8.15 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.17 0.00 8.15 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.28 8.43 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 8.43 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.26 8.69 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 8.69 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.69 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.24 29.51 library setup time
+ 29.51 data required time
+-----------------------------------------------------------------------------
+ 29.51 data required time
+ -8.69 data arrival time
+-----------------------------------------------------------------------------
+ 20.82 slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.98 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.98 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.28 0.73 8.52 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.28 0.00 8.52 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.76 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.76 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.26 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.26 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.13 0.23 9.49 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.13 0.00 9.49 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.49 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.21 29.54 library setup time
+ 29.54 data required time
+-----------------------------------------------------------------------------
+ 29.54 data required time
+ -9.49 data arrival time
+-----------------------------------------------------------------------------
+ 20.05 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 20.05
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 0.76
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_125_/CLK ^
+ 0.05
+_125_/CLK ^
+ 0.05 0.00 0.00
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 1.09e-04 6.56e-06 1.22e-09 1.15e-04 60.4%
+Combinational 3.82e-05 3.72e-05 1.89e-07 7.56e-05 39.6%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 1.47e-04 4.38e-05 1.90e-07 1.91e-04 100.0%
+ 76.9% 23.0% 0.1%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 17966 u^2 4% utilization.
+area_report_end
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/placement/8-resizer.odb...
+Writing netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/placement/8-resizer.nl.v...
+Writing powered netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/placement/8-resizer.pnl.v...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/placement/8-resizer.def...
+Writing timing constraints to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/placement/8-resizer.sdc...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/placement/9-detailed.log b/openlane/user_proj_example/runs/user_proj_example/logs/placement/9-detailed.log
new file mode 100644
index 0000000..796d269
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/placement/9-detailed.log
@@ -0,0 +1,21 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Placement Analysis
+---------------------------------
+total displacement 0.0 u
+average displacement 0.0 u
+max displacement 0.0 u
+original HPWL 9993.9 u
+legalized HPWL 10116.3 u
+delta HPWL 1 %
+
+[INFO DPL-0020] Mirrored 109 instances
+[INFO DPL-0021] HPWL before 10116.3 u
+[INFO DPL-0022] HPWL after 9993.9 u
+[INFO DPL-0023] HPWL delta -1.2 %
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/placement/plant_example.odb...
+Writing netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/placement/plant_example.nl.v...
+Writing powered netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/placement/plant_example.pnl.v...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/placement/plant_example.def...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/routing/12-resizer.log b/openlane/user_proj_example/runs/user_proj_example/logs/routing/12-resizer.log
new file mode 100644
index 0000000..4ed6cd3
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/routing/12-resizer.log
@@ -0,0 +1,782 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO]: Setting signal min routing layer to: Metal2 and clock min routing layer to Metal2.
+[INFO]: Setting signal max routing layer to: Metal4 and clock max routing layer to Metal4.
+-congestion_iterations 50 -verbose
+[INFO GRT-0020] Min routing layer: Metal2
+[INFO GRT-0021] Max routing layer: Metal4
+[INFO GRT-0022] Global adjustment: 30%
+[INFO GRT-0023] Grid origin: (0, 0)
+[INFO GRT-0043] No OR_DEFAULT vias defined.
+[INFO GRT-0088] Layer Metal1 Track-Pitch = 0.5600 line-2-Via Pitch: 0.5450
+[INFO GRT-0088] Layer Metal2 Track-Pitch = 0.5600 line-2-Via Pitch: 0.5800
+[INFO GRT-0088] Layer Metal3 Track-Pitch = 0.5600 line-2-Via Pitch: 0.5800
+[INFO GRT-0088] Layer Metal4 Track-Pitch = 0.5600 line-2-Via Pitch: 0.5800
+[INFO GRT-0019] Found 4 clock nets.
+[INFO GRT-0001] Minimum degree: 2
+[INFO GRT-0002] Maximum degree: 5
+[INFO GRT-0003] Macros: 0
+[INFO GRT-0004] Blockages: 0
+
+[INFO GRT-0053] Routing resources analysis:
+ Routing Original Derated Resource
+Layer Direction Resources Resources Reduction (%)
+---------------------------------------------------------------
+Metal1 Horizontal 0 0 0.00%
+Metal2 Vertical 106358 67970 36.09%
+Metal3 Horizontal 106358 69006 35.12%
+Metal4 Vertical 106358 67290 36.73%
+---------------------------------------------------------------
+
+[INFO GRT-0197] Via related to pin nodes: 534
+[INFO GRT-0198] Via related Steiner nodes: 5
+[INFO GRT-0199] Via filling finished.
+[INFO GRT-0111] Final number of vias: 602
+[INFO GRT-0112] Final usage 3D: 2916
+
+[INFO GRT-0096] Final congestion report:
+Layer Resource Demand Usage (%) Max H / Max V / Total Overflow
+---------------------------------------------------------------------------------------
+Metal1 0 0 0.00% 0 / 0 / 0
+Metal2 67970 729 1.07% 0 / 0 / 0
+Metal3 69006 381 0.55% 0 / 0 / 0
+Metal4 67290 0 0.00% 0 / 0 / 0
+---------------------------------------------------------------------------------------
+Total 204266 1110 0.54% 0 / 0 / 0
+
+[INFO GRT-0018] Total wirelength: 13935 um
+[INFO GRT-0014] Routed nets: 171
+[INFO]: Setting RC values...
+[INFO RSZ-0033] No hold violations found.
+Placement Analysis
+---------------------------------
+total displacement 0.0 u
+average displacement 0.0 u
+max displacement 0.0 u
+original HPWL 10094.7 u
+legalized HPWL 10240.9 u
+delta HPWL 1 %
+
+[INFO DPL-0020] Mirrored 111 instances
+[INFO DPL-0021] HPWL before 10240.9 u
+[INFO DPL-0022] HPWL after 10094.7 u
+[INFO DPL-0023] HPWL delta -1.4 %
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/12-plant_example.odb...
+Writing netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/12-plant_example.nl.v...
+Writing powered netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/12-plant_example.pnl.v...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/12-plant_example.def...
+Writing timing constraints to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/12-plant_example.sdc...
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.72 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.25 1.46 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.15 0.12 1.58 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp3555 (net)
+ 0.15 0.00 1.58 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.58 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.07 0.82 library hold time
+ 0.82 data required time
+-----------------------------------------------------------------------------
+ 0.82 data required time
+ -1.58 data arrival time
+-----------------------------------------------------------------------------
+ 0.76 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.31 0.76 1.25 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.31 0.00 1.25 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.24 0.20 1.46 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.01 _033_ (net)
+ 0.24 0.00 1.46 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.16 0.13 1.58 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _041_ (net)
+ 0.16 0.00 1.58 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.13 1.72 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _045_ (net)
+ 0.16 0.00 1.72 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.14 0.12 1.83 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 fsm_plant_opt.tmp2410 (net)
+ 0.14 0.00 1.83 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.83 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.07 0.82 library hold time
+ 0.82 data required time
+-----------------------------------------------------------------------------
+ 0.82 data required time
+ -1.83 data arrival time
+-----------------------------------------------------------------------------
+ 1.01 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.72 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.25 1.46 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.20 0.19 1.65 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 2 0.01 _048_ (net)
+ 0.20 0.00 1.65 v _121_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.25 1.90 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 1.90 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.23 2.13 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 2.13 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.13 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.06 0.81 library hold time
+ 0.81 data required time
+-----------------------------------------------------------------------------
+ 0.81 data required time
+ -2.13 data arrival time
+-----------------------------------------------------------------------------
+ 1.32 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.72 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.25 1.46 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.23 1.69 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.69 v _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.12 0.29 1.98 v _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _018_ (net)
+ 0.12 0.00 1.98 v _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.26 0.17 2.15 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.26 0.00 2.15 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.15 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.04 0.78 library hold time
+ 0.78 data required time
+-----------------------------------------------------------------------------
+ 0.78 data required time
+ -2.15 data arrival time
+-----------------------------------------------------------------------------
+ 1.37 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.05 0.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.72 1.21 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.25 0.00 1.21 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.28 0.25 1.46 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.28 0.00 1.46 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.32 0.23 1.69 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.32 0.00 1.69 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.12 0.34 2.03 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.12 0.00 2.03 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.12 0.20 2.23 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.12 0.00 2.23 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.23 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.03 0.77 clock reconvergence pessimism
+ 0.08 0.84 library hold time
+ 0.84 data required time
+-----------------------------------------------------------------------------
+ 0.84 data required time
+ -2.23 data arrival time
+-----------------------------------------------------------------------------
+ 1.39 slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.99 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.99 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.29 0.73 8.53 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.29 0.00 8.53 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.77 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.77 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.27 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.27 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.13 0.23 9.50 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.13 0.00 9.50 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.50 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.22 30.02 library setup time
+ 30.02 data required time
+-----------------------------------------------------------------------------
+ 30.02 data required time
+ -9.50 data arrival time
+-----------------------------------------------------------------------------
+ 20.52 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.49 0.98 1.53 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.49 0.00 1.53 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.36 0.31 1.84 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.36 0.00 1.84 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.62 0.46 2.30 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.62 0.00 2.30 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.18 2.49 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 2.49 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.29 0.25 2.74 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 net11 (net)
+ 0.29 0.00 2.74 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.46 3.20 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[1] (net)
+ 0.33 0.00 3.20 ^ io_oeb[1] (out)
+ 3.20 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -3.20 data arrival time
+-----------------------------------------------------------------------------
+ 20.55 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.49 0.98 1.53 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.49 0.00 1.53 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.36 0.31 1.84 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.36 0.00 1.84 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.62 0.46 2.30 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.62 0.00 2.30 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.18 2.49 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 2.49 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.23 2.72 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 net10 (net)
+ 0.27 0.00 2.72 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.46 3.18 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[0] (net)
+ 0.33 0.00 3.18 ^ io_oeb[0] (out)
+ 3.18 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -3.18 data arrival time
+-----------------------------------------------------------------------------
+ 20.57 slack (MET)
+
+
+Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.29 0.86 1.40 ^ _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_water_synth_0 (net)
+ 0.29 0.00 1.40 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.28 0.25 1.66 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 3 0.01 _000_ (net)
+ 0.28 0.00 1.66 v _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.25 0.53 2.19 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 3 0.01 _001_ (net)
+ 0.25 0.00 2.19 v _118_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.22 0.20 2.39 ^ _118_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 1 0.01 net12 (net)
+ 0.22 0.00 2.39 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.45 2.84 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_out[0] (net)
+ 0.33 0.00 2.84 ^ io_out[0] (out)
+ 2.84 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.84 data arrival time
+-----------------------------------------------------------------------------
+ 20.91 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ wbs_we_i (in)
+ 1 0.00 wbs_we_i (net)
+ 0.10 0.00 6.03 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.40 0.39 6.42 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 net9 (net)
+ 0.40 0.00 6.42 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.26 0.23 6.65 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.26 0.00 6.66 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.32 0.47 7.13 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.03 _004_ (net)
+ 0.32 0.00 7.13 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.29 0.59 7.71 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.29 0.00 7.71 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.42 0.32 8.04 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.42 0.00 8.04 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.17 0.12 8.16 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.17 0.00 8.16 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.29 8.44 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 8.44 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.18 0.26 8.70 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.18 0.00 8.70 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.27 0.21 8.92 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 fsm_plant_opt.tmp3553 (net)
+ 0.27 0.00 8.92 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.92 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.24 30.01 library setup time
+ 30.01 data required time
+-----------------------------------------------------------------------------
+ 30.01 data required time
+ -8.92 data arrival time
+-----------------------------------------------------------------------------
+ 21.09 slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.10 0.03 6.03 ^ io_in[1] (in)
+ 1 0.00 io_in[1] (net)
+ 0.10 0.00 6.03 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.95 6.99 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 6.99 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.32 0.60 7.59 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _034_ (net)
+ 0.32 0.00 7.59 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.20 7.79 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 3 0.01 _043_ (net)
+ 0.32 0.00 7.79 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.29 0.73 8.53 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.29 0.00 8.53 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.77 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.77 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.27 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.27 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.13 0.23 9.50 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.13 0.00 9.50 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.50 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.05 30.05 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.13 0.00 30.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.23 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.22 30.02 library setup time
+ 30.02 data required time
+-----------------------------------------------------------------------------
+ 30.02 data required time
+ -9.50 data arrival time
+-----------------------------------------------------------------------------
+ 20.52 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 20.52
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 0.76
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_128_/CLK ^
+ 0.55
+_125_/CLK ^
+ 0.50 -0.03 0.02
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 1.08e-04 6.62e-06 1.22e-09 1.14e-04 19.6%
+Combinational 3.76e-04 9.26e-05 1.91e-07 4.69e-04 80.4%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 4.84e-04 9.92e-05 1.92e-07 5.83e-04 100.0%
+ 82.9% 17.0% 0.0%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 18295 u^2 4% utilization.
+area_report_end
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/12-plant_example.odb...
+Writing netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/12-plant_example.nl.v...
+Writing powered netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/12-plant_example.pnl.v...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/12-plant_example.def...
+Writing timing constraints to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/12-plant_example.sdc...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/routing/13-diodes.log b/openlane/user_proj_example/runs/user_proj_example/logs/routing/13-diodes.log
new file mode 100644
index 0000000..6c7a350
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/routing/13-diodes.log
@@ -0,0 +1,5 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Design name: plant_example
+Inserted 65 diodes.
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/routing/14-diode_legalization.log b/openlane/user_proj_example/runs/user_proj_example/logs/routing/14-diode_legalization.log
new file mode 100644
index 0000000..384c1e1
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/routing/14-diode_legalization.log
@@ -0,0 +1,21 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Placement Analysis
+---------------------------------
+total displacement 332.1 u
+average displacement 0.1 u
+max displacement 14.0 u
+original HPWL 10142.6 u
+legalized HPWL 10356.3 u
+delta HPWL 2 %
+
+[INFO DPL-0020] Mirrored 143 instances
+[INFO DPL-0021] HPWL before 10356.3 u
+[INFO DPL-0022] HPWL after 10196.8 u
+[INFO DPL-0023] HPWL delta -1.5 %
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/diodes.odb...
+Writing netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/diodes.nl.v...
+Writing powered netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/diodes.pnl.v...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/diodes.def...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/routing/15-fill.log b/openlane/user_proj_example/runs/user_proj_example/logs/routing/15-fill.log
new file mode 100644
index 0000000..a56e870
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/routing/15-fill.log
@@ -0,0 +1,9 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO DPL-0001] Placed 10313 filler instances.
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/15-fill.odb...
+Writing netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/15-fill.nl.v...
+Writing powered netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/15-fill.pnl.v...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/15-fill.def...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/routing/16-global.log b/openlane/user_proj_example/runs/user_proj_example/logs/routing/16-global.log
new file mode 100644
index 0000000..0f02790
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/routing/16-global.log
@@ -0,0 +1,783 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO]: Setting signal min routing layer to: Metal2 and clock min routing layer to Metal2.
+[INFO]: Setting signal max routing layer to: Metal4 and clock max routing layer to Metal4.
+-congestion_iterations 50 -verbose
+[INFO GRT-0020] Min routing layer: Metal2
+[INFO GRT-0021] Max routing layer: Metal4
+[INFO GRT-0022] Global adjustment: 30%
+[INFO GRT-0023] Grid origin: (0, 0)
+[INFO GRT-0043] No OR_DEFAULT vias defined.
+[INFO GRT-0088] Layer Metal1 Track-Pitch = 0.5600 line-2-Via Pitch: 0.5450
+[INFO GRT-0088] Layer Metal2 Track-Pitch = 0.5600 line-2-Via Pitch: 0.5800
+[INFO GRT-0088] Layer Metal3 Track-Pitch = 0.5600 line-2-Via Pitch: 0.5800
+[INFO GRT-0088] Layer Metal4 Track-Pitch = 0.5600 line-2-Via Pitch: 0.5800
+[INFO GRT-0019] Found 4 clock nets.
+[INFO GRT-0001] Minimum degree: 2
+[INFO GRT-0002] Maximum degree: 9
+[INFO GRT-0003] Macros: 0
+[INFO GRT-0004] Blockages: 0
+
+[INFO GRT-0053] Routing resources analysis:
+ Routing Original Derated Resource
+Layer Direction Resources Resources Reduction (%)
+---------------------------------------------------------------
+Metal1 Horizontal 0 0 0.00%
+Metal2 Vertical 106358 67970 36.09%
+Metal3 Horizontal 106358 69006 35.12%
+Metal4 Vertical 106358 67290 36.73%
+---------------------------------------------------------------
+
+[INFO GRT-0197] Via related to pin nodes: 615
+[INFO GRT-0198] Via related Steiner nodes: 4
+[INFO GRT-0199] Via filling finished.
+[INFO GRT-0111] Final number of vias: 675
+[INFO GRT-0112] Final usage 3D: 3154
+
+[INFO GRT-0096] Final congestion report:
+Layer Resource Demand Usage (%) Max H / Max V / Total Overflow
+---------------------------------------------------------------------------------------
+Metal1 0 0 0.00% 0 / 0 / 0
+Metal2 67970 736 1.08% 0 / 0 / 0
+Metal3 69006 393 0.57% 0 / 0 / 0
+Metal4 67290 0 0.00% 0 / 0 / 0
+---------------------------------------------------------------------------------------
+Total 204266 1129 0.55% 0 / 0 / 0
+
+[INFO GRT-0018] Total wirelength: 14347 um
+[INFO GRT-0014] Routed nets: 171
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/16-global.odb...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/16-global.def...
+Writing routing guides to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/16-global.guide...
+[INFO]: Setting RC values...
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.28 0.74 1.24 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.28 0.00 1.24 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.29 0.25 1.49 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.29 0.00 1.49 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.17 0.13 1.62 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.01 fsm_plant_opt.tmp3555 (net)
+ 0.17 0.00 1.62 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.62 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.07 0.82 library hold time
+ 0.82 data required time
+-----------------------------------------------------------------------------
+ 0.82 data required time
+ -1.62 data arrival time
+-----------------------------------------------------------------------------
+ 0.80 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.34 0.78 1.28 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.34 0.00 1.28 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.24 0.21 1.49 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.01 _033_ (net)
+ 0.24 0.00 1.49 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.16 0.13 1.62 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _041_ (net)
+ 0.16 0.00 1.62 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.13 1.75 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _045_ (net)
+ 0.16 0.00 1.75 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.15 0.12 1.88 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.01 fsm_plant_opt.tmp2410 (net)
+ 0.15 0.00 1.88 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.88 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.07 0.82 library hold time
+ 0.82 data required time
+-----------------------------------------------------------------------------
+ 0.82 data required time
+ -1.88 data arrival time
+-----------------------------------------------------------------------------
+ 1.06 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.28 0.74 1.24 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.28 0.00 1.24 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.29 0.25 1.49 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.29 0.00 1.49 ^ _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.23 0.21 1.70 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 4 0.01 _048_ (net)
+ 0.23 0.00 1.70 v _121_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.26 1.96 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 1.96 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.21 0.25 2.21 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.21 0.00 2.21 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.21 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.05 0.75 clock reconvergence pessimism
+ 0.05 0.80 library hold time
+ 0.80 data required time
+-----------------------------------------------------------------------------
+ 0.80 data required time
+ -2.21 data arrival time
+-----------------------------------------------------------------------------
+ 1.41 slack (MET)
+
+
+Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.53 0.91 1.41 ^ _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.03 fsm_plant_opt.state_temperature_synth_2 (net)
+ 0.53 0.00 1.41 ^ _070_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.29 0.29 1.70 v _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.29 0.00 1.70 v _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand4_1)
+ 0.21 0.22 1.92 ^ _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand4_1)
+ 1 0.00 _017_ (net)
+ 0.21 0.00 1.92 ^ _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.16 0.28 2.19 ^ _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _018_ (net)
+ 0.16 0.00 2.19 ^ _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.14 0.12 2.32 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.01 fsm_plant_opt.tmp2409 (net)
+ 0.14 0.00 2.32 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.32 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.03 0.77 clock reconvergence pessimism
+ 0.07 0.84 library hold time
+ 0.84 data required time
+-----------------------------------------------------------------------------
+ 0.84 data required time
+ -2.32 data arrival time
+-----------------------------------------------------------------------------
+ 1.47 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.29 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.50 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.50 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.28 0.74 1.24 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.02 fsm_plant_opt.state_water_synth_2 (net)
+ 0.28 0.00 1.24 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.29 0.25 1.49 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.29 0.00 1.49 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.39 0.27 1.76 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 6 0.01 _008_ (net)
+ 0.39 0.00 1.76 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.12 0.36 2.12 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.12 0.00 2.12 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.14 0.21 2.33 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp2411 (net)
+ 0.14 0.00 2.33 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.33 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.80 clock uncertainty
+ -0.03 0.77 clock reconvergence pessimism
+ 0.07 0.84 library hold time
+ 0.84 data required time
+-----------------------------------------------------------------------------
+ 0.84 data required time
+ -2.33 data arrival time
+-----------------------------------------------------------------------------
+ 1.49 slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.12 0.04 6.04 ^ io_in[1] (in)
+ 2 0.00 io_in[1] (net)
+ 0.12 0.00 6.04 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.96 7.00 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 7.00 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.35 0.63 7.63 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 4 0.02 _034_ (net)
+ 0.35 0.00 7.63 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.36 0.24 7.87 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 6 0.02 _043_ (net)
+ 0.36 0.00 7.87 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.29 0.74 8.61 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.29 0.00 8.61 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.85 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.85 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.35 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.35 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.15 0.24 9.60 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp2411 (net)
+ 0.15 0.00 9.60 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.60 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.23 30.02 library setup time
+ 30.02 data required time
+-----------------------------------------------------------------------------
+ 30.02 data required time
+ -9.60 data arrival time
+-----------------------------------------------------------------------------
+ 20.43 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.55 1.02 1.57 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.55 0.00 1.57 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.37 0.32 1.89 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.37 0.00 1.89 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.62 0.47 2.36 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.62 0.00 2.36 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.18 2.54 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 2.54 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.32 0.27 2.82 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 net11 (net)
+ 0.32 0.00 2.82 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.47 3.29 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[1] (net)
+ 0.33 0.00 3.29 ^ io_oeb[1] (out)
+ 3.29 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -3.29 data arrival time
+-----------------------------------------------------------------------------
+ 20.46 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.55 1.02 1.57 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.03 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.55 0.00 1.57 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.37 0.32 1.89 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.37 0.00 1.89 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.62 0.47 2.36 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.62 0.00 2.36 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.18 2.54 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 2.54 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.29 0.24 2.79 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 net10 (net)
+ 0.29 0.00 2.79 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.46 3.25 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[0] (net)
+ 0.33 0.00 3.25 ^ io_oeb[0] (out)
+ 3.25 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -3.25 data arrival time
+-----------------------------------------------------------------------------
+ 20.50 slack (MET)
+
+
+Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.13 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.32 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.32 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.55 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.55 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.34 0.89 1.44 ^ _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.02 fsm_plant_opt.state_water_synth_0 (net)
+ 0.34 0.00 1.44 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.29 0.26 1.71 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 3 0.01 _000_ (net)
+ 0.29 0.00 1.71 v _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.25 0.54 2.24 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 3 0.01 _001_ (net)
+ 0.25 0.00 2.24 v _118_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.24 0.21 2.45 ^ _118_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 net12 (net)
+ 0.24 0.00 2.45 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.33 0.45 2.90 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_out[0] (net)
+ 0.33 0.00 2.90 ^ io_out[0] (out)
+ 2.90 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.90 data arrival time
+-----------------------------------------------------------------------------
+ 20.85 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.12 0.05 6.05 ^ wbs_we_i (in)
+ 2 0.00 wbs_we_i (net)
+ 0.12 0.00 6.05 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.48 0.44 6.48 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.03 net9 (net)
+ 0.48 0.00 6.48 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.28 0.24 6.73 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.28 0.00 6.73 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.36 0.51 7.24 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.03 _004_ (net)
+ 0.36 0.00 7.24 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.29 0.60 7.84 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.29 0.00 7.84 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.42 0.32 8.16 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.42 0.00 8.16 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.17 0.12 8.28 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.17 0.00 8.28 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.29 8.57 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.11 0.00 8.57 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.21 0.28 8.85 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.21 0.00 8.85 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.30 0.24 9.09 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 fsm_plant_opt.tmp3553 (net)
+ 0.30 0.00 9.09 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.09 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.24 30.01 library setup time
+ 30.01 data required time
+-----------------------------------------------------------------------------
+ 30.01 data required time
+ -9.09 data arrival time
+-----------------------------------------------------------------------------
+ 20.91 slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: io_in[1] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.12 0.04 6.04 ^ io_in[1] (in)
+ 2 0.00 io_in[1] (net)
+ 0.12 0.00 6.04 ^ input2/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.21 0.96 7.00 ^ input2/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.01 net2 (net)
+ 0.21 0.00 7.00 ^ _095_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.35 0.63 7.63 ^ _095_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 4 0.02 _034_ (net)
+ 0.35 0.00 7.63 ^ _104_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.36 0.24 7.87 v _104_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 6 0.02 _043_ (net)
+ 0.36 0.00 7.87 v _105_/A3 (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 0.29 0.74 8.61 v _105_/Z (gf180mcu_fd_sc_mcu7t5v0__or3_1)
+ 2 0.01 _044_ (net)
+ 0.29 0.00 8.61 v _115_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.24 8.85 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.85 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.19 0.50 9.35 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.19 0.00 9.35 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.15 0.24 9.60 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.01 fsm_plant_opt.tmp2411 (net)
+ 0.15 0.00 9.60 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.60 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.13 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.13 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.29 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.29 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.50 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.50 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.25 clock uncertainty
+ 0.00 30.25 clock reconvergence pessimism
+ -0.23 30.02 library setup time
+ 30.02 data required time
+-----------------------------------------------------------------------------
+ 30.02 data required time
+ -9.60 data arrival time
+-----------------------------------------------------------------------------
+ 20.43 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+max fanout
+
+Pin Limit Fanout Slack
+---------------------------------------------------------
+_062_/Z 4 8 -4 (VIOLATED)
+_128_/Q 4 8 -4 (VIOLATED)
+_129_/Q 4 8 -4 (VIOLATED)
+input5/Z 4 8 -4 (VIOLATED)
+input7/Z 4 8 -4 (VIOLATED)
+input8/Z 4 8 -4 (VIOLATED)
+input9/Z 4 8 -4 (VIOLATED)
+_066_/ZN 4 6 -2 (VIOLATED)
+_074_/ZN 4 6 -2 (VIOLATED)
+_104_/ZN 4 6 -2 (VIOLATED)
+_125_/Q 4 6 -2 (VIOLATED)
+_126_/Q 4 6 -2 (VIOLATED)
+_127_/Q 4 6 -2 (VIOLATED)
+_130_/Q 4 6 -2 (VIOLATED)
+
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 14
+max cap violation count 0
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 20.43
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 0.80
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_127_/CLK ^
+ 0.55
+_129_/CLK ^
+ 0.50 -0.03 0.02
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 1.08e-04 7.82e-06 1.22e-09 1.15e-04 19.7%
+Combinational 3.76e-04 9.45e-05 7.17e-07 4.72e-04 80.3%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 4.84e-04 1.02e-04 7.18e-07 5.87e-04 100.0%
+ 82.5% 17.4% 0.1%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 18642 u^2 4% utilization.
+area_report_end
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/16-global.odb...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/16-global.def...
+Writing routing guides to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/16-global.guide...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/routing/16-global_write_netlist.log b/openlane/user_proj_example/runs/user_proj_example/logs/routing/16-global_write_netlist.log
new file mode 100644
index 0000000..18ca145
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/routing/16-global_write_netlist.log
@@ -0,0 +1,7 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Setting global connections for newly added cells...
+[WARNING] Did not save OpenROAD database!
+Writing netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/global.nl.v...
+Writing powered netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/routing/global.pnl.v...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/routing/18-detailed.log b/openlane/user_proj_example/runs/user_proj_example/logs/routing/18-detailed.log
new file mode 100644
index 0000000..fe22891
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/routing/18-detailed.log
@@ -0,0 +1,251 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO ORD-0030] Using 2 thread(s).
+[INFO DRT-0149] Reading tech and libs.
+[WARNING DRT-0140] SpacingRange unsupported.
+[WARNING DRT-0140] SpacingRange unsupported.
+[WARNING DRT-0140] SpacingRange unsupported.
+[WARNING DRT-0140] SpacingRange unsupported.
+[WARNING DRT-0140] SpacingRange unsupported.
+
+Units: 2000
+Number of layers: 11
+Number of macros: 229
+Number of vias: 60
+Number of viarulegen: 18
+
+[INFO DRT-0150] Reading design.
+
+Design: plant_example
+Die area: ( 0 0 ) ( 1800000 1200000 )
+Number of track patterns: 10
+Number of DEF vias: 3
+Number of components: 14079
+Number of terminals: 123
+Number of snets: 2
+Number of nets: 206
+
+[INFO DRT-0167] List of default vias:
+ Layer Via1
+ default via: Via1_HV
+ Layer Via2
+ default via: Via2_VH
+ Layer Via3
+ default via: Via3_HV
+ Layer Via4
+ default via: Via4_1_VH
+[INFO DRT-0162] Library cell analysis.
+[INFO DRT-0163] Instance analysis.
+ Complete 10000 instances.
+[INFO DRT-0164] Number of unique instances = 78.
+[INFO DRT-0168] Init region query.
+[INFO DRT-0018] Complete 10000 insts.
+[INFO DRT-0024] Complete Poly2.
+[INFO DRT-0024] Complete CON.
+[INFO DRT-0024] Complete Metal1.
+[INFO DRT-0024] Complete Via1.
+[INFO DRT-0024] Complete Metal2.
+[INFO DRT-0024] Complete Via2.
+[INFO DRT-0024] Complete Metal3.
+[INFO DRT-0024] Complete Via3.
+[INFO DRT-0024] Complete Metal4.
+[INFO DRT-0024] Complete Via4.
+[INFO DRT-0024] Complete Metal5.
+[INFO DRT-0033] Poly2 shape region query size = 0.
+[INFO DRT-0033] CON shape region query size = 0.
+[INFO DRT-0033] Metal1 shape region query size = 364130.
+[INFO DRT-0033] Via1 shape region query size = 2628.
+[INFO DRT-0033] Metal2 shape region query size = 1873.
+[INFO DRT-0033] Via2 shape region query size = 2628.
+[INFO DRT-0033] Metal3 shape region query size = 1752.
+[INFO DRT-0033] Via3 shape region query size = 2628.
+[INFO DRT-0033] Metal4 shape region query size = 900.
+[INFO DRT-0033] Via4 shape region query size = 0.
+[INFO DRT-0033] Metal5 shape region query size = 0.
+[INFO DRT-0165] Start pin access.
+[INFO DRT-0076] Complete 100 pins.
+[INFO DRT-0078] Complete 174 pins.
+[INFO DRT-0081] Complete 58 unique inst patterns.
+[INFO DRT-0084] Complete 240 groups.
+#scanned instances = 14079
+#unique instances = 78
+#stdCellGenAp = 991
+#stdCellValidPlanarAp = 0
+#stdCellValidViaAp = 849
+#stdCellPinNoAp = 0
+#stdCellPinCnt = 276
+#instTermValidViaApCnt = 0
+#macroGenAp = 0
+#macroValidPlanarAp = 0
+#macroValidViaAp = 0
+#macroNoAp = 0
+[INFO DRT-0166] Complete pin access.
+[INFO DRT-0267] cpu time = 00:00:03, elapsed time = 00:00:01, memory = 166.70 (MB), peak = 173.68 (MB)
+
+Number of guides: 920
+
+[INFO DRT-0169] Post process guides.
+[INFO DRT-0176] GCELLGRID X 0 DO 107 STEP 16800 ;
+[INFO DRT-0177] GCELLGRID Y 0 DO 71 STEP 16800 ;
+[INFO DRT-0028] Complete Poly2.
+[INFO DRT-0028] Complete CON.
+[INFO DRT-0028] Complete Metal1.
+[INFO DRT-0028] Complete Via1.
+[INFO DRT-0028] Complete Metal2.
+[INFO DRT-0028] Complete Via2.
+[INFO DRT-0028] Complete Metal3.
+[INFO DRT-0028] Complete Via3.
+[INFO DRT-0028] Complete Metal4.
+[INFO DRT-0028] Complete Via4.
+[INFO DRT-0028] Complete Metal5.
+[INFO DRT-0178] Init guide query.
+[INFO DRT-0035] Complete Poly2 (guide).
+[INFO DRT-0035] Complete CON (guide).
+[INFO DRT-0035] Complete Metal1 (guide).
+[INFO DRT-0035] Complete Via1 (guide).
+[INFO DRT-0035] Complete Metal2 (guide).
+[INFO DRT-0035] Complete Via2 (guide).
+[INFO DRT-0035] Complete Metal3 (guide).
+[INFO DRT-0035] Complete Via3 (guide).
+[INFO DRT-0035] Complete Metal4 (guide).
+[INFO DRT-0035] Complete Via4 (guide).
+[INFO DRT-0035] Complete Metal5 (guide).
+[INFO DRT-0036] Poly2 guide region query size = 0.
+[INFO DRT-0036] CON guide region query size = 0.
+[INFO DRT-0036] Metal1 guide region query size = 334.
+[INFO DRT-0036] Via1 guide region query size = 0.
+[INFO DRT-0036] Metal2 guide region query size = 310.
+[INFO DRT-0036] Via2 guide region query size = 0.
+[INFO DRT-0036] Metal3 guide region query size = 140.
+[INFO DRT-0036] Via3 guide region query size = 0.
+[INFO DRT-0036] Metal4 guide region query size = 0.
+[INFO DRT-0036] Via4 guide region query size = 0.
+[INFO DRT-0036] Metal5 guide region query size = 0.
+[INFO DRT-0179] Init gr pin query.
+[INFO DRT-0245] skipped writing guide updates to database.
+[INFO DRT-0185] Post process initialize RPin region query.
+[INFO DRT-0181] Start track assignment.
+[INFO DRT-0184] Done with 310 vertical wires in 3 frboxes and 474 horizontal wires in 2 frboxes.
+[INFO DRT-0186] Done with 53 vertical wires in 3 frboxes and 69 horizontal wires in 2 frboxes.
+[INFO DRT-0182] Complete track assignment.
+[INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:01, memory = 193.93 (MB), peak = 240.49 (MB)
+[INFO DRT-0187] Start routing data preparation.
+[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 193.93 (MB), peak = 240.49 (MB)
+[INFO DRT-0194] Start detail routing.
+[INFO DRT-0195] Start 0th optimization iteration.
+ Completing 10% with 0 violations.
+ elapsed time = 00:00:00, memory = 263.55 (MB).
+ Completing 20% with 0 violations.
+ elapsed time = 00:00:00, memory = 365.63 (MB).
+ Completing 30% with 18 violations.
+ elapsed time = 00:00:01, memory = 313.46 (MB).
+ Completing 40% with 18 violations.
+ elapsed time = 00:00:01, memory = 378.74 (MB).
+ Completing 50% with 18 violations.
+ elapsed time = 00:00:02, memory = 440.52 (MB).
+ Completing 60% with 19 violations.
+ elapsed time = 00:00:02, memory = 440.91 (MB).
+ Completing 70% with 19 violations.
+ elapsed time = 00:00:03, memory = 441.15 (MB).
+ Completing 80% with 71 violations.
+ elapsed time = 00:00:03, memory = 316.23 (MB).
+ Completing 90% with 71 violations.
+ elapsed time = 00:00:04, memory = 379.79 (MB).
+ Completing 100% with 75 violations.
+ elapsed time = 00:00:05, memory = 301.99 (MB).
+[INFO DRT-0199] Number of violations = 75.
+Viol/Layer Metal1 Via1 Metal2
+Cut Spacing 0 1 0
+Metal Spacing 1 0 72
+Short 0 0 1
+[INFO DRT-0267] cpu time = 00:00:09, elapsed time = 00:00:05, memory = 301.89 (MB), peak = 477.48 (MB)
+Total wire length = 10544 um.
+Total wire length on LAYER Metal1 = 0 um.
+Total wire length on LAYER Metal2 = 7318 um.
+Total wire length on LAYER Metal3 = 3225 um.
+Total wire length on LAYER Metal4 = 0 um.
+Total wire length on LAYER Metal5 = 0 um.
+Total number of vias = 767.
+Up-via summary (total 767):.
+
+--------------
+ Poly2 0
+ Metal1 431
+ Metal2 336
+ Metal3 0
+ Metal4 0
+--------------
+ 767
+
+
+[INFO DRT-0195] Start 1st optimization iteration.
+ Completing 10% with 75 violations.
+ elapsed time = 00:00:00, memory = 344.78 (MB).
+ Completing 20% with 75 violations.
+ elapsed time = 00:00:00, memory = 395.64 (MB).
+ Completing 30% with 43 violations.
+ elapsed time = 00:00:01, memory = 431.12 (MB).
+ Completing 40% with 43 violations.
+ elapsed time = 00:00:01, memory = 431.39 (MB).
+ Completing 50% with 43 violations.
+ elapsed time = 00:00:02, memory = 455.44 (MB).
+ Completing 60% with 43 violations.
+ elapsed time = 00:00:02, memory = 365.98 (MB).
+ Completing 70% with 43 violations.
+ elapsed time = 00:00:03, memory = 421.60 (MB).
+ Completing 80% with 4 violations.
+ elapsed time = 00:00:03, memory = 443.61 (MB).
+ Completing 90% with 4 violations.
+ elapsed time = 00:00:04, memory = 444.07 (MB).
+ Completing 100% with 0 violations.
+ elapsed time = 00:00:04, memory = 429.46 (MB).
+[INFO DRT-0199] Number of violations = 0.
+[INFO DRT-0267] cpu time = 00:00:08, elapsed time = 00:00:04, memory = 429.47 (MB), peak = 605.00 (MB)
+Total wire length = 10197 um.
+Total wire length on LAYER Metal1 = 3 um.
+Total wire length on LAYER Metal2 = 7105 um.
+Total wire length on LAYER Metal3 = 3087 um.
+Total wire length on LAYER Metal4 = 0 um.
+Total wire length on LAYER Metal5 = 0 um.
+Total number of vias = 737.
+Up-via summary (total 737):.
+
+--------------
+ Poly2 0
+ Metal1 430
+ Metal2 307
+ Metal3 0
+ Metal4 0
+--------------
+ 737
+
+
+[INFO DRT-0198] Complete detail routing.
+Total wire length = 10197 um.
+Total wire length on LAYER Metal1 = 3 um.
+Total wire length on LAYER Metal2 = 7105 um.
+Total wire length on LAYER Metal3 = 3087 um.
+Total wire length on LAYER Metal4 = 0 um.
+Total wire length on LAYER Metal5 = 0 um.
+Total number of vias = 737.
+Up-via summary (total 737):.
+
+--------------
+ Poly2 0
+ Metal1 430
+ Metal2 307
+ Metal3 0
+ Metal4 0
+--------------
+ 737
+
+
+[INFO DRT-0267] cpu time = 00:00:18, elapsed time = 00:00:10, memory = 429.47 (MB), peak = 605.00 (MB)
+
+[INFO DRT-0180] Post processing.
+Setting global connections for newly added cells...
+Writing OpenROAD database to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.odb...
+Writing netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.nl.v...
+Writing powered netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.pnl.v...
+Writing layout to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.def...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/routing/19-wire_lengths.log b/openlane/user_proj_example/runs/user_proj_example/logs/routing/19-wire_lengths.log
new file mode 100644
index 0000000..4e49139
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/routing/19-wire_lengths.log
@@ -0,0 +1,4 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+No wire length surpasses the threshold (Infinity μm).
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/signoff/20-parasitics_extraction.nom.log b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/20-parasitics_extraction.nom.log
new file mode 100644
index 0000000..c3b83a5
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/20-parasitics_extraction.nom.log
@@ -0,0 +1,36 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO ODB-0222] Reading LEF file: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/merged.nom.lef
+[INFO ODB-0223] Created 13 technology layers
+[INFO ODB-0224] Created 60 technology vias
+[INFO ODB-0225] Created 229 library cells
+[INFO ODB-0226] Finished LEF file: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/merged.nom.lef
+[INFO ODB-0127] Reading DEF file: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.def
+[INFO ODB-0128] Design: plant_example
+[INFO ODB-0130] Created 123 pins.
+[INFO ODB-0131] Created 14079 components and 28586 component-terminals.
+[INFO ODB-0132] Created 2 special nets and 28158 connections.
+[INFO ODB-0133] Created 206 nets and 428 connections.
+[INFO ODB-0134] Finished DEF file: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.def
+Using RCX ruleset '/localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.nom'...
+[INFO RCX-0431] Defined process_corner X with ext_model_index 0
+[INFO RCX-0029] Defined extraction corner X
+[INFO RCX-0008] extracting parasitics of plant_example ...
+[INFO RCX-0435] Reading extraction model file /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.nom ...
+[INFO RCX-0436] RC segment generation plant_example (max_merge_res 50.0) ...
+[INFO RCX-0040] Final 562 rc segments
+[INFO RCX-0439] Coupling Cap extraction plant_example ...
+[INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded.
+[INFO RCX-0043] 901 wires to be extracted
+[INFO RCX-0442] 57% completion -- 515 wires have been extracted
+[INFO RCX-0442] 100% completion -- 901 wires have been extracted
+[INFO RCX-0045] Extract 206 nets, 733 rsegs, 733 caps, 728 ccs
+[INFO RCX-0015] Finished extracting plant_example.
+Writing result to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/mca/process_corner_nom/plant_example.spef...
+Setting global connections for newly added cells...
+[WARNING] Did not save OpenROAD database!
+Writing extracted parasitics to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/mca/process_corner_nom/plant_example.spef...
+[INFO RCX-0016] Writing SPEF ...
+[INFO RCX-0443] 206 nets finished
+[INFO RCX-0017] Finished writing SPEF ...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/signoff/21-rcx_mcsta.nom.log b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/21-rcx_mcsta.nom.log
new file mode 100644
index 0000000..f2341a8
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/21-rcx_mcsta.nom.log
@@ -0,0 +1,3484 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+
+======================= Slowest Corner ===================================
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.10 0.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.43 0.53 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.53 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.37 0.91 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.14 0.00 0.91 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.77 1.54 2.45 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.77 0.00 2.45 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.60 0.58 3.03 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.60 0.00 3.03 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.70 0.50 3.53 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp3555 (net)
+ 0.70 0.00 3.54 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3.54 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.11 0.11 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.47 0.59 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.59 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.41 1.00 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.14 0.00 1.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 1.25 clock uncertainty
+ -0.10 1.16 clock reconvergence pessimism
+ -0.02 1.14 library hold time
+ 1.14 data required time
+-----------------------------------------------------------------------------
+ 1.14 data required time
+ -3.54 data arrival time
+-----------------------------------------------------------------------------
+ 2.40 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.10 0.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.43 0.53 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.53 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.38 0.91 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.15 0.00 0.91 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.93 1.64 2.55 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.93 0.00 2.55 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.53 0.51 3.06 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.01 _033_ (net)
+ 0.53 0.00 3.06 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.36 0.28 3.34 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _041_ (net)
+ 0.36 0.00 3.34 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.32 0.28 3.62 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 _045_ (net)
+ 0.32 0.00 3.62 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.85 0.57 4.19 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.03 fsm_plant_opt.tmp2410 (net)
+ 0.85 0.00 4.20 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 4.20 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.11 0.11 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.47 0.59 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.59 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.42 1.01 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.15 0.00 1.01 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 1.26 clock uncertainty
+ -0.10 1.16 clock reconvergence pessimism
+ -0.07 1.09 library hold time
+ 1.09 data required time
+-----------------------------------------------------------------------------
+ 1.09 data required time
+ -4.20 data arrival time
+-----------------------------------------------------------------------------
+ 3.10 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.10 0.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.43 0.53 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.53 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.38 0.91 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.15 0.00 0.91 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.93 1.64 2.55 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.93 0.00 2.55 v _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor4_4)
+ 1.05 0.77 3.32 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_4)
+ 3 0.02 _020_ (net)
+ 1.05 0.00 3.32 ^ _083_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.33 0.32 3.64 v _083_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 _025_ (net)
+ 0.33 0.00 3.64 v _084_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.51 0.39 4.04 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _026_ (net)
+ 0.51 0.00 4.04 ^ _089_/I1 (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 0.20 0.50 4.54 ^ _089_/Z (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 1 0.01 _030_ (net)
+ 0.20 0.00 4.54 ^ _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.74 0.49 5.03 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp2409 (net)
+ 0.74 0.00 5.03 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 5.03 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.11 0.11 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.47 0.59 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.59 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.41 1.00 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.14 0.00 1.00 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 1.25 clock uncertainty
+ -0.06 1.20 clock reconvergence pessimism
+ -0.03 1.17 library hold time
+ 1.17 data required time
+-----------------------------------------------------------------------------
+ 1.17 data required time
+ -5.03 data arrival time
+-----------------------------------------------------------------------------
+ 3.87 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.10 0.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.43 0.53 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.53 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.37 0.91 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.14 0.00 0.91 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.77 1.54 2.45 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.77 0.00 2.45 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.60 0.58 3.03 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.60 0.00 3.03 ^ _085_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.46 0.38 3.41 v _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.46 0.00 3.41 v _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.29 0.27 3.68 ^ _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.29 0.00 3.69 ^ _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.32 0.54 4.23 ^ _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.32 0.00 4.23 ^ _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1.10 0.86 5.09 ^ _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 1.10 0.00 5.09 ^ _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 5.09 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.11 0.11 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.47 0.59 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.59 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.41 1.00 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.14 0.00 1.00 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 1.25 clock uncertainty
+ -0.10 1.16 clock reconvergence pessimism
+ 0.04 1.20 library hold time
+ 1.20 data required time
+-----------------------------------------------------------------------------
+ 1.20 data required time
+ -5.09 data arrival time
+-----------------------------------------------------------------------------
+ 3.89 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.10 0.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.43 0.53 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.53 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.37 0.91 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.14 0.00 0.91 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.77 1.54 2.45 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.77 0.00 2.45 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.60 0.58 3.03 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.60 0.00 3.03 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 1.13 0.75 3.78 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 6 0.03 _008_ (net)
+ 1.13 0.00 3.78 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.25 0.81 4.59 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.01 _054_ (net)
+ 0.25 0.00 4.59 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.67 0.65 5.23 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.02 fsm_plant_opt.tmp2411 (net)
+ 0.67 0.00 5.23 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 5.23 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.11 0.11 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.47 0.59 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.59 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.42 1.01 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.15 0.00 1.01 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 1.26 clock uncertainty
+ -0.06 1.20 clock reconvergence pessimism
+ -0.01 1.19 library hold time
+ 1.19 data required time
+-----------------------------------------------------------------------------
+ 1.19 data required time
+ -5.23 data arrival time
+-----------------------------------------------------------------------------
+ 4.04 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.10 0.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.43 0.53 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.53 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.37 0.91 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.14 0.00 0.91 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.77 1.54 2.45 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.77 0.00 2.45 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.60 0.58 3.03 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.60 0.00 3.03 ^ _085_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.46 0.38 3.41 v _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.46 0.00 3.41 v _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.29 0.27 3.68 ^ _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.29 0.00 3.69 ^ _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.32 0.54 4.23 ^ _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.32 0.00 4.23 ^ _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1.10 0.86 5.09 ^ _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 1.10 0.00 5.09 ^ _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.83 0.68 5.77 v _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.03 fsm_plant_opt.tmp3553 (net)
+ 0.83 0.00 5.77 v _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 5.77 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.11 0.11 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.47 0.59 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.59 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.42 1.01 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.15 0.00 1.01 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 1.26 clock uncertainty
+ -0.06 1.20 clock reconvergence pessimism
+ -0.06 1.14 library hold time
+ 1.14 data required time
+-----------------------------------------------------------------------------
+ 1.14 data required time
+ -5.77 data arrival time
+-----------------------------------------------------------------------------
+ 4.63 slack (MET)
+
+
+Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.10 0.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.43 0.53 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.53 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.37 0.91 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.14 0.00 0.91 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.94 1.64 2.55 v _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8 0.06 fsm_plant_opt.state_temperature_synth_0 (net)
+ 0.94 0.00 2.55 v _086_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.53 0.51 3.06 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.53 0.00 3.06 ^ _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1.27 0.84 3.90 v _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.05 net10 (net)
+ 1.27 0.00 3.91 v output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.61 0.96 4.87 v output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[0] (net)
+ 0.61 0.00 4.87 v io_oeb[0] (out)
+ 4.87 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ -6.00 -5.75 output external delay
+ -5.75 data required time
+-----------------------------------------------------------------------------
+ -5.75 data required time
+ -4.87 data arrival time
+-----------------------------------------------------------------------------
+ 10.62 slack (MET)
+
+
+Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.10 0.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.43 0.53 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.53 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.37 0.91 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.14 0.00 0.91 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.94 1.64 2.55 v _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8 0.06 fsm_plant_opt.state_temperature_synth_0 (net)
+ 0.94 0.00 2.55 v _086_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.53 0.51 3.06 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.53 0.00 3.06 ^ _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 1.41 0.95 4.01 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.05 net11 (net)
+ 1.41 0.00 4.01 v output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.62 0.99 5.00 v output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[1] (net)
+ 0.62 0.00 5.00 v io_oeb[1] (out)
+ 5.00 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ -6.00 -5.75 output external delay
+ -5.75 data required time
+-----------------------------------------------------------------------------
+ -5.75 data required time
+ -5.00 data arrival time
+-----------------------------------------------------------------------------
+ 10.75 slack (MET)
+
+
+Startpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.10 0.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.43 0.53 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.53 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.37 0.91 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.14 0.00 0.91 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.96 1.66 2.56 v _128_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8 0.06 fsm_plant_opt.state_water_synth_1 (net)
+ 0.96 0.00 2.57 v _059_/A2 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.50 1.06 3.63 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 3 0.02 _001_ (net)
+ 0.50 0.00 3.63 v _118_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 1.26 0.83 4.46 ^ _118_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.04 net12 (net)
+ 1.26 0.00 4.47 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.60 0.87 5.34 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_out[0] (net)
+ 0.60 0.00 5.34 ^ io_out[0] (out)
+ 5.34 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ -6.00 -5.75 output external delay
+ -5.75 data required time
+-----------------------------------------------------------------------------
+ -5.75 data required time
+ -5.34 data arrival time
+-----------------------------------------------------------------------------
+ 11.09 slack (MET)
+
+
+
+======================= Typical Corner ===================================
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.45 0.85 1.35 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.45 0.00 1.36 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.34 0.33 1.68 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.34 0.00 1.68 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.39 0.28 1.96 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp3555 (net)
+ 0.39 0.00 1.96 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.96 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.81 clock uncertainty
+ -0.05 0.76 clock reconvergence pessimism
+ 0.00 0.76 library hold time
+ 0.76 data required time
+-----------------------------------------------------------------------------
+ 0.76 data required time
+ -1.96 data arrival time
+-----------------------------------------------------------------------------
+ 1.20 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.55 0.90 1.41 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.55 0.00 1.42 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.30 0.29 1.70 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.01 _033_ (net)
+ 0.30 0.00 1.70 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.20 0.15 1.85 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _041_ (net)
+ 0.20 0.00 1.85 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.18 0.15 2.00 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 _045_ (net)
+ 0.18 0.00 2.00 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.47 0.32 2.32 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.03 fsm_plant_opt.tmp2410 (net)
+ 0.47 0.00 2.32 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.32 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.81 clock uncertainty
+ -0.05 0.76 clock reconvergence pessimism
+ -0.03 0.73 library hold time
+ 0.73 data required time
+-----------------------------------------------------------------------------
+ 0.73 data required time
+ -2.32 data arrival time
+-----------------------------------------------------------------------------
+ 1.59 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.55 0.90 1.41 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.55 0.00 1.42 v _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor4_4)
+ 0.55 0.41 1.82 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_4)
+ 3 0.01 _020_ (net)
+ 0.55 0.00 1.82 ^ _083_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.18 0.17 1.99 v _083_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 _025_ (net)
+ 0.18 0.00 1.99 v _084_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.29 0.22 2.21 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _026_ (net)
+ 0.29 0.00 2.21 ^ _089_/I1 (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 0.11 0.27 2.49 ^ _089_/Z (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 1 0.01 _030_ (net)
+ 0.11 0.00 2.49 ^ _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.41 0.27 2.76 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp2409 (net)
+ 0.41 0.00 2.76 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.76 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.81 clock uncertainty
+ -0.03 0.78 clock reconvergence pessimism
+ -0.01 0.77 library hold time
+ 0.77 data required time
+-----------------------------------------------------------------------------
+ 0.77 data required time
+ -2.76 data arrival time
+-----------------------------------------------------------------------------
+ 1.99 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.45 0.85 1.35 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.45 0.00 1.36 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.34 0.33 1.68 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.34 0.00 1.68 ^ _085_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.26 0.21 1.90 v _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.26 0.00 1.90 v _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.15 2.05 ^ _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.16 0.00 2.05 ^ _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.18 0.29 2.34 ^ _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.18 0.00 2.34 ^ _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.64 0.49 2.83 ^ _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 0.64 0.00 2.83 ^ _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.83 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.81 clock uncertainty
+ -0.05 0.76 clock reconvergence pessimism
+ 0.04 0.80 library hold time
+ 0.80 data required time
+-----------------------------------------------------------------------------
+ 0.80 data required time
+ -2.83 data arrival time
+-----------------------------------------------------------------------------
+ 2.04 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.45 0.85 1.35 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.45 0.00 1.36 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.34 0.33 1.68 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.34 0.00 1.68 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.60 0.40 2.08 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 6 0.03 _008_ (net)
+ 0.60 0.00 2.08 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.14 0.43 2.51 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.01 _054_ (net)
+ 0.14 0.00 2.51 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.39 0.37 2.87 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.02 fsm_plant_opt.tmp2411 (net)
+ 0.39 0.00 2.88 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.88 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.81 clock uncertainty
+ -0.03 0.78 clock reconvergence pessimism
+ 0.00 0.78 library hold time
+ 0.78 data required time
+-----------------------------------------------------------------------------
+ 0.78 data required time
+ -2.88 data arrival time
+-----------------------------------------------------------------------------
+ 2.09 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.45 0.85 1.35 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.45 0.00 1.36 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.34 0.33 1.68 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.34 0.00 1.68 ^ _085_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.26 0.21 1.90 v _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.26 0.00 1.90 v _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.15 2.05 ^ _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.16 0.00 2.05 ^ _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.18 0.29 2.34 ^ _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.18 0.00 2.34 ^ _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.64 0.49 2.83 ^ _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 0.64 0.00 2.83 ^ _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.49 0.38 3.21 v _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.03 fsm_plant_opt.tmp3553 (net)
+ 0.49 0.00 3.21 v _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3.21 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.81 clock uncertainty
+ -0.03 0.78 clock reconvergence pessimism
+ -0.03 0.75 library hold time
+ 0.75 data required time
+-----------------------------------------------------------------------------
+ 0.75 data required time
+ -3.21 data arrival time
+-----------------------------------------------------------------------------
+ 2.46 slack (MET)
+
+
+Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.55 0.91 1.41 v _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8 0.05 fsm_plant_opt.state_temperature_synth_0 (net)
+ 0.55 0.00 1.42 v _086_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.30 0.29 1.71 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.30 0.00 1.71 ^ _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.71 0.47 2.18 v _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.05 net10 (net)
+ 0.71 0.00 2.18 v output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.35 0.53 2.71 v output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[0] (net)
+ 0.35 0.00 2.71 v io_oeb[0] (out)
+ 2.71 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ -6.00 -5.75 output external delay
+ -5.75 data required time
+-----------------------------------------------------------------------------
+ -5.75 data required time
+ -2.71 data arrival time
+-----------------------------------------------------------------------------
+ 8.46 slack (MET)
+
+
+Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.55 0.91 1.41 v _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8 0.05 fsm_plant_opt.state_temperature_synth_0 (net)
+ 0.55 0.00 1.42 v _086_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.30 0.29 1.71 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.30 0.00 1.71 ^ _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.81 0.54 2.25 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.05 net11 (net)
+ 0.81 0.00 2.25 v output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.35 0.55 2.80 v output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[1] (net)
+ 0.35 0.00 2.80 v io_oeb[1] (out)
+ 2.80 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ -6.00 -5.75 output external delay
+ -5.75 data required time
+-----------------------------------------------------------------------------
+ -5.75 data required time
+ -2.80 data arrival time
+-----------------------------------------------------------------------------
+ 8.55 slack (MET)
+
+
+Startpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.56 0.91 1.42 v _128_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8 0.06 fsm_plant_opt.state_water_synth_1 (net)
+ 0.56 0.00 1.42 v _059_/A2 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.28 0.58 2.00 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 3 0.02 _001_ (net)
+ 0.28 0.00 2.00 v _118_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.73 0.48 2.48 ^ _118_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.04 net12 (net)
+ 0.73 0.00 2.49 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.35 0.50 2.98 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_out[0] (net)
+ 0.35 0.00 2.99 ^ io_out[0] (out)
+ 2.99 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ -6.00 -5.75 output external delay
+ -5.75 data required time
+-----------------------------------------------------------------------------
+ -5.75 data required time
+ -2.99 data arrival time
+-----------------------------------------------------------------------------
+ 8.74 slack (MET)
+
+
+
+======================= Fastest Corner ===================================
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.04 0.04 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.04 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.13 0.33 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.05 0.00 0.33 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.30 0.53 0.86 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.30 0.00 0.87 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.22 0.21 1.08 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.22 0.00 1.08 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.25 0.17 1.25 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp3555 (net)
+ 0.25 0.00 1.25 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.25 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.05 0.05 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.05 0.00 0.36 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.61 clock uncertainty
+ -0.03 0.58 clock reconvergence pessimism
+ 0.01 0.59 library hold time
+ 0.59 data required time
+-----------------------------------------------------------------------------
+ 0.59 data required time
+ -1.25 data arrival time
+-----------------------------------------------------------------------------
+ 0.67 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.04 0.04 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.04 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.13 0.33 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.05 0.00 0.33 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.36 0.57 0.90 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.36 0.00 0.91 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.19 0.18 1.09 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.01 _033_ (net)
+ 0.19 0.00 1.09 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.12 0.09 1.18 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _041_ (net)
+ 0.12 0.00 1.18 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.11 0.10 1.28 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 _045_ (net)
+ 0.11 0.00 1.28 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.30 0.20 1.48 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.03 fsm_plant_opt.tmp2410 (net)
+ 0.30 0.00 1.48 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.48 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.05 0.05 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.15 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.05 0.00 0.36 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.61 clock uncertainty
+ -0.03 0.58 clock reconvergence pessimism
+ -0.01 0.57 library hold time
+ 0.57 data required time
+-----------------------------------------------------------------------------
+ 0.57 data required time
+ -1.48 data arrival time
+-----------------------------------------------------------------------------
+ 0.91 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.04 0.04 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.04 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.13 0.33 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.05 0.00 0.33 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.36 0.57 0.90 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.36 0.00 0.91 v _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor4_4)
+ 0.33 0.25 1.16 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_4)
+ 3 0.01 _020_ (net)
+ 0.33 0.00 1.16 ^ _083_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.12 0.10 1.26 v _083_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 _025_ (net)
+ 0.12 0.00 1.26 v _084_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.19 0.14 1.40 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _026_ (net)
+ 0.19 0.00 1.40 ^ _089_/I1 (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 0.07 0.17 1.57 ^ _089_/Z (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 1 0.01 _030_ (net)
+ 0.07 0.00 1.57 ^ _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.26 0.17 1.75 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp2409 (net)
+ 0.26 0.00 1.75 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.75 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.05 0.05 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.05 0.00 0.36 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.61 clock uncertainty
+ -0.02 0.59 clock reconvergence pessimism
+ 0.01 0.60 library hold time
+ 0.60 data required time
+-----------------------------------------------------------------------------
+ 0.60 data required time
+ -1.75 data arrival time
+-----------------------------------------------------------------------------
+ 1.15 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.04 0.04 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.04 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.13 0.33 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.05 0.00 0.33 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.30 0.53 0.86 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.30 0.00 0.87 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.22 0.21 1.08 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.22 0.00 1.08 ^ _085_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.17 0.14 1.21 v _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.17 0.00 1.21 v _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.11 0.10 1.31 ^ _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.11 0.00 1.31 ^ _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.18 1.49 ^ _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.11 0.00 1.49 ^ _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.42 0.32 1.82 ^ _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 0.42 0.00 1.82 ^ _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.82 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.05 0.05 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.15 0.36 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.05 0.00 0.36 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.61 clock uncertainty
+ -0.03 0.58 clock reconvergence pessimism
+ 0.03 0.61 library hold time
+ 0.61 data required time
+-----------------------------------------------------------------------------
+ 0.61 data required time
+ -1.82 data arrival time
+-----------------------------------------------------------------------------
+ 1.21 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.04 0.04 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.04 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.13 0.33 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.05 0.00 0.33 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.30 0.53 0.86 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.30 0.00 0.87 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.22 0.21 1.08 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.22 0.00 1.08 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.37 0.24 1.32 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 6 0.03 _008_ (net)
+ 0.37 0.00 1.32 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.09 0.26 1.58 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.01 _054_ (net)
+ 0.09 0.00 1.58 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.25 0.24 1.82 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.02 fsm_plant_opt.tmp2411 (net)
+ 0.25 0.00 1.82 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.82 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.05 0.05 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.15 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.05 0.00 0.36 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.61 clock uncertainty
+ -0.02 0.59 clock reconvergence pessimism
+ 0.01 0.60 library hold time
+ 0.60 data required time
+-----------------------------------------------------------------------------
+ 0.60 data required time
+ -1.82 data arrival time
+-----------------------------------------------------------------------------
+ 1.22 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.04 0.04 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.04 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.13 0.33 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.05 0.00 0.33 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.30 0.53 0.86 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.30 0.00 0.87 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.22 0.21 1.08 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.22 0.00 1.08 ^ _085_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.17 0.14 1.21 v _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.17 0.00 1.21 v _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.11 0.10 1.31 ^ _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.11 0.00 1.31 ^ _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.11 0.18 1.49 ^ _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.11 0.00 1.49 ^ _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.42 0.32 1.82 ^ _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 0.42 0.00 1.82 ^ _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.32 0.25 2.06 v _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.03 fsm_plant_opt.tmp3553 (net)
+ 0.32 0.00 2.06 v _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.06 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.05 0.05 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.15 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.05 0.00 0.36 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.61 clock uncertainty
+ -0.02 0.59 clock reconvergence pessimism
+ -0.01 0.58 library hold time
+ 0.58 data required time
+-----------------------------------------------------------------------------
+ 0.58 data required time
+ -2.06 data arrival time
+-----------------------------------------------------------------------------
+ 1.48 slack (MET)
+
+
+Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.04 0.04 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.04 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.13 0.33 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.05 0.00 0.33 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.37 0.58 0.90 v _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8 0.05 fsm_plant_opt.state_temperature_synth_0 (net)
+ 0.37 0.00 0.91 v _086_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.20 0.19 1.10 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.20 0.00 1.10 ^ _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.45 0.30 1.40 v _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.05 net10 (net)
+ 0.45 0.00 1.40 v output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.23 0.34 1.74 v output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[0] (net)
+ 0.23 0.00 1.74 v io_oeb[0] (out)
+ 1.74 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ -6.00 -5.75 output external delay
+ -5.75 data required time
+-----------------------------------------------------------------------------
+ -5.75 data required time
+ -1.74 data arrival time
+-----------------------------------------------------------------------------
+ 7.49 slack (MET)
+
+
+Startpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.04 0.04 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.04 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.13 0.33 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.05 0.00 0.33 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.37 0.58 0.90 v _129_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8 0.05 fsm_plant_opt.state_temperature_synth_0 (net)
+ 0.37 0.00 0.91 v _086_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.20 0.19 1.10 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.20 0.00 1.10 ^ _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.52 0.35 1.45 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.05 net11 (net)
+ 0.52 0.00 1.45 v output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.23 0.35 1.80 v output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[1] (net)
+ 0.23 0.00 1.80 v io_oeb[1] (out)
+ 1.80 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ -6.00 -5.75 output external delay
+ -5.75 data required time
+-----------------------------------------------------------------------------
+ -5.75 data required time
+ -1.80 data arrival time
+-----------------------------------------------------------------------------
+ 7.55 slack (MET)
+
+
+Startpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.04 0.04 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.04 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.13 0.33 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.05 0.00 0.33 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.37 0.58 0.91 v _128_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8 0.05 fsm_plant_opt.state_water_synth_1 (net)
+ 0.37 0.00 0.91 v _059_/A2 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.18 0.36 1.27 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 3 0.02 _001_ (net)
+ 0.18 0.00 1.27 v _118_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.49 0.32 1.59 ^ _118_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.04 net12 (net)
+ 0.49 0.00 1.59 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.23 0.33 1.92 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_out[0] (net)
+ 0.23 0.00 1.92 ^ io_out[0] (out)
+ 1.92 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ -6.00 -5.75 output external delay
+ -5.75 data required time
+-----------------------------------------------------------------------------
+ -5.75 data required time
+ -1.92 data arrival time
+-----------------------------------------------------------------------------
+ 7.67 slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+
+======================= Slowest Corner ===================================
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.25 0.10 6.10 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.25 0.00 6.10 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.93 1.44 7.55 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 1.93 0.01 7.55 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.77 0.62 8.17 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.77 0.00 8.17 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.80 1.12 9.29 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.05 _004_ (net)
+ 0.80 0.00 9.29 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.59 1.24 10.53 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.59 0.00 10.53 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.87 0.67 11.20 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.87 0.00 11.20 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.57 0.26 11.46 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.57 0.00 11.46 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.24 0.65 12.11 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.24 0.00 12.11 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1.04 0.95 13.06 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 1.04 0.00 13.06 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1.57 1.20 14.26 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.03 fsm_plant_opt.tmp3553 (net)
+ 1.57 0.00 14.26 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 14.26 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.24 0.10 30.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 30.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.43 30.53 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 30.53 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.38 30.91 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.15 0.00 30.91 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.66 clock uncertainty
+ 0.00 30.66 clock reconvergence pessimism
+ -0.56 30.10 library setup time
+ 30.10 data required time
+-----------------------------------------------------------------------------
+ 30.10 data required time
+ -14.26 data arrival time
+-----------------------------------------------------------------------------
+ 15.84 slack (MET)
+
+
+Startpoint: wbs_sel_i[2] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.25 0.10 6.10 ^ wbs_sel_i[2] (in)
+ 2 0.01 wbs_sel_i[2] (net)
+ 0.25 0.00 6.10 ^ input8/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 3.69 2.50 8.60 ^ input8/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.13 net8 (net)
+ 3.69 0.02 8.62 ^ _098_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1.57 1.14 9.76 v _098_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 _037_ (net)
+ 1.57 0.00 9.76 v _099_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.43 1.24 11.01 v _099_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _038_ (net)
+ 0.43 0.00 11.01 v _101_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai211_1)
+ 1.07 0.76 11.77 ^ _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai211_1)
+ 2 0.01 _040_ (net)
+ 1.07 0.00 11.77 ^ _113_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.41 0.34 12.10 v _113_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 1 0.01 _051_ (net)
+ 0.41 0.00 12.10 v _115_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.48 0.40 12.50 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.48 0.00 12.50 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.39 1.02 13.52 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.01 _054_ (net)
+ 0.39 0.00 13.52 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.71 0.74 14.26 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.02 fsm_plant_opt.tmp2411 (net)
+ 0.71 0.00 14.26 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 14.26 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.24 0.10 30.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 30.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.43 30.53 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 30.53 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.38 30.91 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.15 0.00 30.91 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.66 clock uncertainty
+ 0.00 30.66 clock reconvergence pessimism
+ -0.53 30.13 library setup time
+ 30.13 data required time
+-----------------------------------------------------------------------------
+ 30.13 data required time
+ -14.26 data arrival time
+-----------------------------------------------------------------------------
+ 15.87 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.11 0.11 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.47 0.59 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.59 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.42 1.01 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.15 0.00 1.01 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.57 2.26 3.27 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 1.57 0.00 3.27 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.89 0.78 4.05 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.89 0.00 4.05 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1.46 1.11 5.16 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 1.46 0.00 5.16 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.65 0.37 5.53 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.65 0.00 5.53 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1.52 1.11 6.64 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.05 net10 (net)
+ 1.52 0.00 6.65 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.60 1.00 7.65 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[0] (net)
+ 0.60 0.00 7.65 ^ io_oeb[0] (out)
+ 7.65 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -7.65 data arrival time
+-----------------------------------------------------------------------------
+ 16.10 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.11 0.11 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.47 0.59 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.59 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.42 1.01 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.15 0.00 1.01 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.57 2.26 3.27 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 1.57 0.00 3.27 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.89 0.78 4.05 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.89 0.00 4.05 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1.46 1.11 5.16 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 1.46 0.00 5.16 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.65 0.37 5.53 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.65 0.00 5.53 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 1.44 1.08 6.62 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.05 net11 (net)
+ 1.44 0.00 6.62 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.60 1.00 7.61 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[1] (net)
+ 0.60 0.00 7.62 ^ io_oeb[1] (out)
+ 7.62 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -7.62 data arrival time
+-----------------------------------------------------------------------------
+ 16.13 slack (MET)
+
+
+Startpoint: wbs_sel_i[0] (input port clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 v input external delay
+ 0.15 0.06 6.06 v wbs_sel_i[0] (in)
+ 2 0.01 wbs_sel_i[0] (net)
+ 0.15 0.00 6.06 v input6/I (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 0.98 2.54 8.60 v input6/Z (gf180mcu_fd_sc_mcu7t5v0__dlyb_1)
+ 2 0.04 net6 (net)
+ 0.98 0.00 8.61 v _098_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1.65 1.14 9.75 ^ _098_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 _037_ (net)
+ 1.65 0.00 9.75 ^ _099_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.63 1.24 10.99 ^ _099_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _038_ (net)
+ 0.63 0.00 10.99 ^ _101_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai211_1)
+ 0.92 0.55 11.54 v _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai211_1)
+ 2 0.01 _040_ (net)
+ 0.92 0.00 11.54 v _102_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.65 0.64 12.18 ^ _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _041_ (net)
+ 0.65 0.00 12.18 ^ _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.36 0.29 12.47 v _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 _045_ (net)
+ 0.36 0.00 12.47 v _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1.88 1.17 13.64 ^ _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.03 fsm_plant_opt.tmp2410 (net)
+ 1.88 0.00 13.64 ^ _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 13.64 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.24 0.10 30.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 30.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.43 30.53 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 30.53 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.38 30.91 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.15 0.00 30.91 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.66 clock uncertainty
+ 0.00 30.66 clock reconvergence pessimism
+ -0.56 30.10 library setup time
+ 30.10 data required time
+-----------------------------------------------------------------------------
+ 30.10 data required time
+ -13.64 data arrival time
+-----------------------------------------------------------------------------
+ 16.46 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.25 0.10 6.10 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.25 0.00 6.10 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.93 1.44 7.55 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 1.93 0.01 7.55 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.77 0.62 8.17 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.77 0.00 8.17 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.80 1.12 9.29 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.05 _004_ (net)
+ 0.80 0.00 9.29 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.59 1.24 10.53 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.59 0.00 10.53 v _065_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.55 0.46 10.99 ^ _065_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 _007_ (net)
+ 0.55 0.00 10.99 ^ _066_/A3 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 1.14 0.81 11.80 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 6 0.03 _008_ (net)
+ 1.14 0.00 11.80 v _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.24 0.76 12.56 v _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _018_ (net)
+ 0.24 0.00 12.56 v _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1.65 1.00 13.56 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp2409 (net)
+ 1.65 0.00 13.56 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 13.56 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.24 0.10 30.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 30.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.43 30.53 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 30.53 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.37 30.91 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.14 0.00 30.91 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.66 clock uncertainty
+ 0.00 30.66 clock reconvergence pessimism
+ -0.56 30.09 library setup time
+ 30.09 data required time
+-----------------------------------------------------------------------------
+ 30.09 data required time
+ -13.56 data arrival time
+-----------------------------------------------------------------------------
+ 16.53 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.25 0.10 6.10 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.25 0.00 6.10 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.93 1.44 7.55 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 1.93 0.01 7.55 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.77 0.62 8.17 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.77 0.00 8.17 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.80 1.12 9.29 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.05 _004_ (net)
+ 0.80 0.00 9.29 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.59 1.24 10.53 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.59 0.00 10.53 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.87 0.67 11.20 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.87 0.00 11.20 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.57 0.26 11.46 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.57 0.00 11.46 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.24 0.65 12.11 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.24 0.00 12.11 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1.04 0.95 13.06 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 1.04 0.00 13.06 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 13.06 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.24 0.10 30.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 30.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.43 30.53 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 30.53 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.37 30.91 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.14 0.00 30.91 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.66 clock uncertainty
+ 0.00 30.66 clock reconvergence pessimism
+ -0.76 29.90 library setup time
+ 29.90 data required time
+-----------------------------------------------------------------------------
+ 29.90 data required time
+ -13.06 data arrival time
+-----------------------------------------------------------------------------
+ 16.83 slack (MET)
+
+
+Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.24 0.11 0.11 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.47 0.59 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 0.59 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.42 1.01 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.15 0.00 1.01 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.19 2.03 3.03 ^ _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_0 (net)
+ 1.19 0.00 3.04 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.75 0.67 3.71 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 3 0.02 _000_ (net)
+ 0.75 0.00 3.71 v _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.50 1.14 4.85 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 3 0.02 _001_ (net)
+ 0.50 0.00 4.85 v _118_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 1.26 0.92 5.77 ^ _118_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.04 net12 (net)
+ 1.26 0.00 5.78 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.60 0.97 6.75 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_out[0] (net)
+ 0.60 0.00 6.75 ^ io_out[0] (out)
+ 6.75 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -6.75 data arrival time
+-----------------------------------------------------------------------------
+ 17.00 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.25 0.10 6.10 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.25 0.00 6.10 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.93 1.44 7.55 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 1.93 0.01 7.55 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.77 0.62 8.17 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.77 0.00 8.17 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.80 1.12 9.29 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.05 _004_ (net)
+ 0.80 0.00 9.29 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.59 1.24 10.53 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.59 0.00 10.53 v _124_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1.55 1.16 11.69 ^ _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp3555 (net)
+ 1.55 0.00 11.69 ^ _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 11.69 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.24 0.10 30.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 30.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.43 30.53 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 30.53 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.37 30.91 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.14 0.00 30.91 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.66 clock uncertainty
+ 0.00 30.66 clock reconvergence pessimism
+ -0.56 30.10 library setup time
+ 30.10 data required time
+-----------------------------------------------------------------------------
+ 30.10 data required time
+ -11.69 data arrival time
+-----------------------------------------------------------------------------
+ 18.40 slack (MET)
+
+
+
+======================= Typical Corner ===================================
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.14 0.06 6.06 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.14 0.00 6.06 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.12 0.83 6.89 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 1.12 0.01 6.90 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.44 0.35 7.25 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.44 0.00 7.25 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.46 0.63 7.88 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.04 _004_ (net)
+ 0.46 0.00 7.88 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.33 0.67 8.55 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.33 0.00 8.55 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.47 0.36 8.91 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.47 0.00 8.91 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.33 0.14 9.05 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.33 0.00 9.05 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.14 0.36 9.41 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.14 0.00 9.41 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.60 0.54 9.95 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 0.60 0.00 9.95 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.87 0.66 10.61 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.03 fsm_plant_opt.tmp3553 (net)
+ 0.87 0.00 10.61 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 10.61 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.14 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.51 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.26 clock uncertainty
+ 0.00 30.26 clock reconvergence pessimism
+ -0.26 30.00 library setup time
+ 30.00 data required time
+-----------------------------------------------------------------------------
+ 30.00 data required time
+ -10.61 data arrival time
+-----------------------------------------------------------------------------
+ 19.38 slack (MET)
+
+
+Startpoint: wbs_sel_i[2] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.14 0.06 6.06 ^ wbs_sel_i[2] (in)
+ 2 0.01 wbs_sel_i[2] (net)
+ 0.14 0.00 6.06 ^ input8/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2.15 1.46 7.51 ^ input8/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.13 net8 (net)
+ 2.15 0.02 7.54 ^ _098_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.93 0.64 8.17 v _098_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 _037_ (net)
+ 0.93 0.00 8.18 v _099_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.25 0.69 8.87 v _099_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _038_ (net)
+ 0.25 0.00 8.87 v _101_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai211_1)
+ 0.59 0.41 9.28 ^ _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai211_1)
+ 2 0.01 _040_ (net)
+ 0.59 0.00 9.28 ^ _113_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.23 0.18 9.46 v _113_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 1 0.01 _051_ (net)
+ 0.23 0.00 9.46 v _115_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.28 0.21 9.68 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.28 0.00 9.68 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.21 0.52 10.20 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.01 _054_ (net)
+ 0.21 0.00 10.20 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.41 0.41 10.61 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.02 fsm_plant_opt.tmp2411 (net)
+ 0.41 0.00 10.61 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 10.61 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.14 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.51 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.26 clock uncertainty
+ 0.00 30.26 clock reconvergence pessimism
+ -0.25 30.01 library setup time
+ 30.01 data required time
+-----------------------------------------------------------------------------
+ 30.01 data required time
+ -10.61 data arrival time
+-----------------------------------------------------------------------------
+ 19.40 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.91 1.24 1.80 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.91 0.00 1.80 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.51 0.44 2.24 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.51 0.00 2.24 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.78 0.61 2.85 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.78 0.00 2.85 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.36 0.20 3.05 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.36 0.00 3.05 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.88 0.64 3.68 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.05 net10 (net)
+ 0.88 0.00 3.69 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.35 0.57 4.26 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[0] (net)
+ 0.35 0.00 4.26 ^ io_oeb[0] (out)
+ 4.26 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -4.26 data arrival time
+-----------------------------------------------------------------------------
+ 19.49 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.91 1.24 1.80 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.91 0.00 1.80 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.51 0.44 2.24 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.51 0.00 2.24 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.78 0.61 2.85 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.78 0.00 2.85 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.36 0.20 3.05 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.36 0.00 3.05 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.84 0.62 3.67 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.05 net11 (net)
+ 0.84 0.00 3.67 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.35 0.57 4.24 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[1] (net)
+ 0.35 0.00 4.24 ^ io_oeb[1] (out)
+ 4.24 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -4.24 data arrival time
+-----------------------------------------------------------------------------
+ 19.51 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.14 0.06 6.06 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.14 0.00 6.06 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.12 0.83 6.89 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 1.12 0.01 6.90 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.44 0.35 7.25 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.44 0.00 7.25 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.46 0.63 7.88 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.04 _004_ (net)
+ 0.46 0.00 7.88 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.33 0.67 8.55 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.33 0.00 8.55 v _065_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.30 0.25 8.80 ^ _065_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 _007_ (net)
+ 0.30 0.00 8.80 ^ _066_/A3 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.61 0.43 9.23 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 6 0.03 _008_ (net)
+ 0.61 0.00 9.23 v _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.13 0.40 9.63 v _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _018_ (net)
+ 0.13 0.00 9.63 v _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.91 0.55 10.18 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp2409 (net)
+ 0.91 0.00 10.18 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 10.18 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.14 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 30.51 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.26 clock uncertainty
+ 0.00 30.26 clock reconvergence pessimism
+ -0.26 30.00 library setup time
+ 30.00 data required time
+-----------------------------------------------------------------------------
+ 30.00 data required time
+ -10.18 data arrival time
+-----------------------------------------------------------------------------
+ 19.81 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.14 0.06 6.06 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.14 0.00 6.06 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.12 0.83 6.89 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 1.12 0.01 6.90 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.44 0.35 7.25 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.44 0.00 7.25 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.46 0.63 7.88 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.04 _004_ (net)
+ 0.46 0.00 7.88 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.33 0.67 8.55 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.33 0.00 8.55 v _109_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.74 0.54 9.10 ^ _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 4 0.02 _048_ (net)
+ 0.74 0.00 9.10 ^ _110_/B1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.45 0.34 9.44 v _110_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 2 0.01 _049_ (net)
+ 0.45 0.00 9.44 v _112_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1.04 0.75 10.18 ^ _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.03 fsm_plant_opt.tmp2410 (net)
+ 1.04 0.00 10.19 ^ _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 10.19 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.14 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.51 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.26 clock uncertainty
+ 0.00 30.26 clock reconvergence pessimism
+ -0.26 30.00 library setup time
+ 30.00 data required time
+-----------------------------------------------------------------------------
+ 30.00 data required time
+ -10.19 data arrival time
+-----------------------------------------------------------------------------
+ 19.81 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.14 0.06 6.06 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.14 0.00 6.06 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.12 0.83 6.89 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 1.12 0.01 6.90 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.44 0.35 7.25 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.44 0.00 7.25 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.46 0.63 7.88 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.04 _004_ (net)
+ 0.46 0.00 7.88 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.33 0.67 8.55 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.33 0.00 8.55 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.47 0.36 8.91 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.47 0.00 8.91 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.33 0.14 9.05 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.33 0.00 9.05 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.14 0.36 9.41 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.14 0.00 9.41 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.60 0.54 9.95 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 0.60 0.00 9.95 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.95 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.14 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 30.51 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.26 clock uncertainty
+ 0.00 30.26 clock reconvergence pessimism
+ -0.40 29.86 library setup time
+ 29.86 data required time
+-----------------------------------------------------------------------------
+ 29.86 data required time
+ -9.95 data arrival time
+-----------------------------------------------------------------------------
+ 19.90 slack (MET)
+
+
+Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.69 1.10 1.67 ^ _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_0 (net)
+ 0.69 0.00 1.67 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.43 0.38 2.04 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 3 0.02 _000_ (net)
+ 0.43 0.00 2.04 v _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.28 0.62 2.66 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 3 0.02 _001_ (net)
+ 0.28 0.00 2.66 v _118_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.73 0.53 3.19 ^ _118_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.04 net12 (net)
+ 0.73 0.00 3.20 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.35 0.55 3.75 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_out[0] (net)
+ 0.35 0.00 3.75 ^ io_out[0] (out)
+ 3.75 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -3.75 data arrival time
+-----------------------------------------------------------------------------
+ 20.00 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.14 0.06 6.06 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.14 0.00 6.06 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.12 0.83 6.89 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 1.12 0.01 6.90 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.44 0.35 7.25 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.44 0.00 7.25 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.46 0.63 7.88 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.04 _004_ (net)
+ 0.46 0.00 7.88 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.33 0.67 8.55 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.33 0.00 8.55 v _124_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.86 0.63 9.18 ^ _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp3555 (net)
+ 0.86 0.00 9.18 ^ _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 9.18 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.14 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 30.51 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.26 clock uncertainty
+ 0.00 30.26 clock reconvergence pessimism
+ -0.26 29.99 library setup time
+ 29.99 data required time
+-----------------------------------------------------------------------------
+ 29.99 data required time
+ -9.18 data arrival time
+-----------------------------------------------------------------------------
+ 20.82 slack (MET)
+
+
+
+======================= Fastest Corner ===================================
+
+Startpoint: wbs_sel_i[2] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.09 0.04 6.04 ^ wbs_sel_i[2] (in)
+ 2 0.01 wbs_sel_i[2] (net)
+ 0.09 0.00 6.04 ^ input8/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.42 0.97 7.01 ^ input8/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.13 net8 (net)
+ 1.42 0.02 7.03 ^ _098_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.63 0.41 7.44 v _098_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 _037_ (net)
+ 0.63 0.00 7.44 v _099_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.17 0.45 7.89 v _099_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _038_ (net)
+ 0.17 0.00 7.89 v _101_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai211_1)
+ 0.38 0.25 8.15 ^ _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai211_1)
+ 2 0.01 _040_ (net)
+ 0.38 0.00 8.15 ^ _113_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.15 0.12 8.27 v _113_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 1 0.01 _051_ (net)
+ 0.15 0.00 8.27 v _115_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.18 0.13 8.40 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.18 0.00 8.40 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.13 0.31 8.71 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.01 _054_ (net)
+ 0.13 0.00 8.71 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.27 0.27 8.98 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.02 fsm_plant_opt.tmp2411 (net)
+ 0.27 0.00 8.98 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.98 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.09 0.04 30.04 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 30.04 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.15 30.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 30.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.13 30.33 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.05 0.00 30.33 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.08 clock uncertainty
+ 0.00 30.08 clock reconvergence pessimism
+ -0.15 29.93 library setup time
+ 29.93 data required time
+-----------------------------------------------------------------------------
+ 29.93 data required time
+ -8.98 data arrival time
+-----------------------------------------------------------------------------
+ 20.95 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.09 0.04 6.04 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.09 0.00 6.04 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.73 0.55 6.59 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 0.73 0.01 6.60 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.29 0.23 6.82 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.29 0.00 6.82 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.30 0.41 7.23 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.04 _004_ (net)
+ 0.30 0.00 7.23 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.21 0.42 7.65 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.21 0.00 7.65 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.28 0.22 7.88 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.28 0.00 7.88 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.21 0.09 7.96 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.21 0.00 7.96 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.09 0.23 8.19 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.09 0.00 8.19 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.39 0.35 8.54 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 0.39 0.00 8.54 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.54 0.41 8.95 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.03 fsm_plant_opt.tmp3553 (net)
+ 0.54 0.00 8.96 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.96 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.09 0.04 30.04 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 30.04 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.15 30.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 30.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.13 30.33 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.05 0.00 30.33 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.08 clock uncertainty
+ 0.00 30.08 clock reconvergence pessimism
+ -0.15 29.93 library setup time
+ 29.93 data required time
+-----------------------------------------------------------------------------
+ 29.93 data required time
+ -8.96 data arrival time
+-----------------------------------------------------------------------------
+ 20.97 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.05 0.05 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.15 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.05 0.00 0.36 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.60 0.78 1.14 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.60 0.00 1.15 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.33 0.28 1.43 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.33 0.00 1.43 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.48 0.38 1.81 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.48 0.00 1.81 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.24 0.12 1.94 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.24 0.00 1.94 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.58 0.42 2.36 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.05 net10 (net)
+ 0.58 0.00 2.36 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.23 0.38 2.74 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[0] (net)
+ 0.23 0.00 2.74 ^ io_oeb[0] (out)
+ 2.74 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.74 data arrival time
+-----------------------------------------------------------------------------
+ 21.01 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.05 0.05 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.15 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.05 0.00 0.36 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.60 0.78 1.14 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.60 0.00 1.15 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.33 0.28 1.43 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.33 0.00 1.43 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.48 0.38 1.81 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.48 0.00 1.81 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.24 0.12 1.94 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.24 0.00 1.94 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.55 0.41 2.35 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.05 net11 (net)
+ 0.55 0.00 2.35 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.23 0.37 2.72 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[1] (net)
+ 0.23 0.00 2.72 ^ io_oeb[1] (out)
+ 2.72 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.72 data arrival time
+-----------------------------------------------------------------------------
+ 21.03 slack (MET)
+
+
+Startpoint: wbs_sel_i[2] (input port clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.09 0.04 6.04 ^ wbs_sel_i[2] (in)
+ 2 0.01 wbs_sel_i[2] (net)
+ 0.09 0.00 6.04 ^ input8/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.42 0.97 7.01 ^ input8/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.13 net8 (net)
+ 1.42 0.02 7.03 ^ _098_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.63 0.41 7.44 v _098_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 _037_ (net)
+ 0.63 0.00 7.44 v _099_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.17 0.45 7.89 v _099_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _038_ (net)
+ 0.17 0.00 7.89 v _101_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai211_1)
+ 0.38 0.25 8.15 ^ _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai211_1)
+ 2 0.01 _040_ (net)
+ 0.38 0.00 8.15 ^ _102_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.17 0.14 8.29 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _041_ (net)
+ 0.17 0.00 8.29 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.14 0.12 8.41 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 _045_ (net)
+ 0.14 0.00 8.41 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.37 0.23 8.64 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.03 fsm_plant_opt.tmp2410 (net)
+ 0.37 0.00 8.64 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.64 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.09 0.04 30.04 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 30.04 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.15 30.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 30.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.13 30.33 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.05 0.00 30.33 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.08 clock uncertainty
+ 0.00 30.08 clock reconvergence pessimism
+ -0.23 29.85 library setup time
+ 29.85 data required time
+-----------------------------------------------------------------------------
+ 29.85 data required time
+ -8.64 data arrival time
+-----------------------------------------------------------------------------
+ 21.21 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.09 0.04 6.04 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.09 0.00 6.04 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.73 0.55 6.59 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 0.73 0.01 6.60 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.29 0.23 6.82 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.29 0.00 6.82 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.30 0.41 7.23 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.04 _004_ (net)
+ 0.30 0.00 7.23 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.21 0.42 7.65 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.21 0.00 7.65 v _065_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.19 0.16 7.81 ^ _065_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 _007_ (net)
+ 0.19 0.00 7.81 ^ _066_/A3 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.37 0.26 8.07 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 6 0.03 _008_ (net)
+ 0.37 0.00 8.07 v _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.09 0.25 8.32 v _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _018_ (net)
+ 0.09 0.00 8.32 v _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.56 0.34 8.66 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp2409 (net)
+ 0.56 0.00 8.66 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.66 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.09 0.04 30.04 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 30.04 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.15 30.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 30.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.13 30.33 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.05 0.00 30.33 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.08 clock uncertainty
+ 0.00 30.08 clock reconvergence pessimism
+ -0.15 29.93 library setup time
+ 29.93 data required time
+-----------------------------------------------------------------------------
+ 29.93 data required time
+ -8.66 data arrival time
+-----------------------------------------------------------------------------
+ 21.27 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.09 0.04 6.04 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.09 0.00 6.04 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.73 0.55 6.59 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 0.73 0.01 6.60 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.29 0.23 6.82 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.29 0.00 6.82 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.30 0.41 7.23 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.04 _004_ (net)
+ 0.30 0.00 7.23 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.21 0.42 7.65 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.21 0.00 7.65 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.28 0.22 7.88 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.28 0.00 7.88 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.21 0.09 7.96 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.21 0.00 7.96 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.09 0.23 8.19 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.09 0.00 8.19 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.39 0.35 8.54 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 0.39 0.00 8.55 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.55 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.09 0.04 30.04 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 30.04 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.15 30.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 30.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.13 30.33 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.05 0.00 30.33 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.08 clock uncertainty
+ 0.00 30.08 clock reconvergence pessimism
+ -0.24 29.84 library setup time
+ 29.84 data required time
+-----------------------------------------------------------------------------
+ 29.84 data required time
+ -8.55 data arrival time
+-----------------------------------------------------------------------------
+ 21.29 slack (MET)
+
+
+Startpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.09 0.05 0.05 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.15 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.05 0.00 0.36 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.45 0.69 1.05 ^ _127_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_0 (net)
+ 0.45 0.00 1.06 ^ _058_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.28 0.24 1.30 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 3 0.02 _000_ (net)
+ 0.28 0.00 1.30 v _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.18 0.38 1.68 v _059_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 3 0.02 _001_ (net)
+ 0.18 0.00 1.68 v _118_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.49 0.35 2.03 ^ _118_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.04 net12 (net)
+ 0.49 0.00 2.04 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.23 0.36 2.40 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_out[0] (net)
+ 0.23 0.00 2.40 ^ io_out[0] (out)
+ 2.40 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.40 data arrival time
+-----------------------------------------------------------------------------
+ 21.35 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.09 0.04 6.04 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.09 0.00 6.04 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.73 0.55 6.59 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 0.73 0.01 6.60 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.29 0.23 6.82 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.29 0.00 6.82 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.30 0.41 7.23 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.04 _004_ (net)
+ 0.30 0.00 7.23 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.21 0.42 7.65 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.21 0.00 7.65 v _124_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.53 0.39 8.04 ^ _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp3555 (net)
+ 0.53 0.00 8.04 ^ _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.04 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.09 0.04 30.04 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 30.04 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.15 30.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 30.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.13 30.33 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.05 0.00 30.33 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.08 clock uncertainty
+ 0.00 30.08 clock reconvergence pessimism
+ -0.15 29.93 library setup time
+ 29.93 data required time
+-----------------------------------------------------------------------------
+ 29.93 data required time
+ -8.04 data arrival time
+-----------------------------------------------------------------------------
+ 21.89 slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+
+======================= Slowest Corner ===================================
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ss
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.25 0.10 6.10 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.25 0.00 6.10 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.93 1.44 7.55 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 1.93 0.01 7.55 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.77 0.62 8.17 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.77 0.00 8.17 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.80 1.12 9.29 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.05 _004_ (net)
+ 0.80 0.00 9.29 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.59 1.24 10.53 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.59 0.00 10.53 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.87 0.67 11.20 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.87 0.00 11.20 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.57 0.26 11.46 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.57 0.00 11.46 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.24 0.65 12.11 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.24 0.00 12.11 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 1.04 0.95 13.06 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 1.04 0.00 13.06 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1.57 1.20 14.26 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.03 fsm_plant_opt.tmp3553 (net)
+ 1.57 0.00 14.26 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 14.26 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.24 0.10 30.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.24 0.00 30.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.20 0.43 30.53 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.20 0.00 30.53 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.38 30.91 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.15 0.00 30.91 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.66 clock uncertainty
+ 0.00 30.66 clock reconvergence pessimism
+ -0.56 30.10 library setup time
+ 30.10 data required time
+-----------------------------------------------------------------------------
+ 30.10 data required time
+ -14.26 data arrival time
+-----------------------------------------------------------------------------
+ 15.84 slack (MET)
+
+
+
+======================= Typical Corner ===================================
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: tt
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.14 0.06 6.06 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.14 0.00 6.06 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.12 0.83 6.89 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 1.12 0.01 6.90 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.44 0.35 7.25 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.44 0.00 7.25 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.46 0.63 7.88 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.04 _004_ (net)
+ 0.46 0.00 7.88 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.33 0.67 8.55 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.33 0.00 8.55 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.47 0.36 8.91 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.47 0.00 8.91 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.33 0.14 9.05 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.33 0.00 9.05 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.14 0.36 9.41 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.14 0.00 9.41 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.60 0.54 9.95 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 0.60 0.00 9.95 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.87 0.66 10.61 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.03 fsm_plant_opt.tmp3553 (net)
+ 0.87 0.00 10.61 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 10.61 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.14 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.51 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.26 clock uncertainty
+ 0.00 30.26 clock reconvergence pessimism
+ -0.26 30.00 library setup time
+ 30.00 data required time
+-----------------------------------------------------------------------------
+ 30.00 data required time
+ -10.61 data arrival time
+-----------------------------------------------------------------------------
+ 19.38 slack (MET)
+
+
+
+======================= Fastest Corner ===================================
+
+Startpoint: wbs_sel_i[2] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+Corner: ff
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.09 0.04 6.04 ^ wbs_sel_i[2] (in)
+ 2 0.01 wbs_sel_i[2] (net)
+ 0.09 0.00 6.04 ^ input8/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.42 0.97 7.01 ^ input8/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.13 net8 (net)
+ 1.42 0.02 7.03 ^ _098_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.63 0.41 7.44 v _098_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 _037_ (net)
+ 0.63 0.00 7.44 v _099_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.17 0.45 7.89 v _099_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _038_ (net)
+ 0.17 0.00 7.89 v _101_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai211_1)
+ 0.38 0.25 8.15 ^ _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai211_1)
+ 2 0.01 _040_ (net)
+ 0.38 0.00 8.15 ^ _113_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.15 0.12 8.27 v _113_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 1 0.01 _051_ (net)
+ 0.15 0.00 8.27 v _115_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.18 0.13 8.40 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.18 0.00 8.40 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.13 0.31 8.71 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.01 _054_ (net)
+ 0.13 0.00 8.71 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.27 0.27 8.98 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.02 fsm_plant_opt.tmp2411 (net)
+ 0.27 0.00 8.98 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.98 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.09 0.04 30.04 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.09 0.00 30.04 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.07 0.15 30.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.07 0.00 30.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.05 0.13 30.33 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.05 0.00 30.33 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.08 clock uncertainty
+ 0.00 30.08 clock reconvergence pessimism
+ -0.15 29.93 library setup time
+ 29.93 data required time
+-----------------------------------------------------------------------------
+ 29.93 data required time
+ -8.98 data arrival time
+-----------------------------------------------------------------------------
+ 20.95 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+
+======================= Slowest Corner ===================================
+
+No paths found.
+
+======================= Typical Corner ===================================
+
+No paths found.
+
+======================= Fastest Corner ===================================
+
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+======================= Slowest Corner ===================================
+
+max fanout
+
+Pin Limit Fanout Slack
+---------------------------------------------------------
+_062_/Z 4 8 -4 (VIOLATED)
+_128_/Q 4 8 -4 (VIOLATED)
+_129_/Q 4 8 -4 (VIOLATED)
+input5/Z 4 8 -4 (VIOLATED)
+input7/Z 4 8 -4 (VIOLATED)
+input8/Z 4 8 -4 (VIOLATED)
+input9/Z 4 8 -4 (VIOLATED)
+_066_/ZN 4 6 -2 (VIOLATED)
+_074_/ZN 4 6 -2 (VIOLATED)
+_104_/ZN 4 6 -2 (VIOLATED)
+_125_/Q 4 6 -2 (VIOLATED)
+_126_/Q 4 6 -2 (VIOLATED)
+_127_/Q 4 6 -2 (VIOLATED)
+_130_/Q 4 6 -2 (VIOLATED)
+
+
+======================= Typical Corner ===================================
+
+max fanout
+
+Pin Limit Fanout Slack
+---------------------------------------------------------
+_062_/Z 4 8 -4 (VIOLATED)
+_128_/Q 4 8 -4 (VIOLATED)
+_129_/Q 4 8 -4 (VIOLATED)
+input5/Z 4 8 -4 (VIOLATED)
+input7/Z 4 8 -4 (VIOLATED)
+input8/Z 4 8 -4 (VIOLATED)
+input9/Z 4 8 -4 (VIOLATED)
+_066_/ZN 4 6 -2 (VIOLATED)
+_074_/ZN 4 6 -2 (VIOLATED)
+_104_/ZN 4 6 -2 (VIOLATED)
+_125_/Q 4 6 -2 (VIOLATED)
+_126_/Q 4 6 -2 (VIOLATED)
+_127_/Q 4 6 -2 (VIOLATED)
+_130_/Q 4 6 -2 (VIOLATED)
+
+
+======================= Fastest Corner ===================================
+
+max fanout
+
+Pin Limit Fanout Slack
+---------------------------------------------------------
+_062_/Z 4 8 -4 (VIOLATED)
+_128_/Q 4 8 -4 (VIOLATED)
+_129_/Q 4 8 -4 (VIOLATED)
+input5/Z 4 8 -4 (VIOLATED)
+input7/Z 4 8 -4 (VIOLATED)
+input8/Z 4 8 -4 (VIOLATED)
+input9/Z 4 8 -4 (VIOLATED)
+_066_/ZN 4 6 -2 (VIOLATED)
+_074_/ZN 4 6 -2 (VIOLATED)
+_104_/ZN 4 6 -2 (VIOLATED)
+_125_/Q 4 6 -2 (VIOLATED)
+_126_/Q 4 6 -2 (VIOLATED)
+_127_/Q 4 6 -2 (VIOLATED)
+_130_/Q 4 6 -2 (VIOLATED)
+
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 14
+max cap violation count 0
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 15.84
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 0.67
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+
+======================== Slowest Corner ==================================
+
+Clock wb_clk_i
+Latency CRPR Skew
+_127_/CLK ^
+ 1.01
+_130_/CLK ^
+ 0.91 -0.06 0.04
+
+
+======================= Typical Corner ===================================
+
+Clock wb_clk_i
+Latency CRPR Skew
+_127_/CLK ^
+ 0.56
+_130_/CLK ^
+ 0.51 -0.03 0.02
+
+
+======================= Fastest Corner ===================================
+
+Clock wb_clk_i
+Latency CRPR Skew
+_127_/CLK ^
+ 0.36
+_130_/CLK ^
+ 0.33 -0.02 0.02
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+
+
+======================= Slowest Corner =================================
+
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 8.96e-05 1.25e-05 3.47e-09 1.02e-04 19.7%
+Combinational 3.00e-04 1.08e-04 8.82e-06 4.17e-04 80.3%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 3.89e-04 1.21e-04 8.82e-06 5.19e-04 100.0%
+ 75.0% 23.3% 1.7%
+
+======================= Typical Corner ===================================
+
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 1.08e-04 1.52e-05 1.22e-09 1.23e-04 19.3%
+Combinational 3.81e-04 1.32e-04 7.17e-07 5.14e-04 80.7%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 4.89e-04 1.48e-04 7.18e-07 6.37e-04 100.0%
+ 76.7% 23.2% 0.1%
+
+
+======================= Fastest Corner =================================
+
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 1.31e-04 1.82e-05 1.46e-09 1.49e-04 18.7%
+Combinational 4.88e-04 1.60e-04 8.67e-07 6.49e-04 81.3%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 6.19e-04 1.78e-04 8.69e-07 7.98e-04 100.0%
+ 77.6% 22.3% 0.1%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 18642 u^2 4% utilization.
+area_report_end
+Setting global connections for newly added cells...
+[WARNING] Did not save OpenROAD database!
+Writing SDF files for all corners...
+Writing SDF for the ff corner to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/mca/process_corner_nom/plant_example.ff.sdf...
+Writing SDF for the ss corner to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/mca/process_corner_nom/plant_example.ss.sdf...
+Writing SDF for the tt corner to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/mca/process_corner_nom/plant_example.tt.sdf...
+Writing timing models for all corners...
+Writing timing models for the ff corner to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/mca/process_corner_nom/plant_example.ff.lib...
+Writing timing models for the ss corner to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/mca/process_corner_nom/plant_example.ss.lib...
+Writing timing models for the tt corner to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/mca/process_corner_nom/plant_example.tt.lib...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/signoff/22-rcx_sta.log b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/22-rcx_sta.log
new file mode 100644
index 0000000..b35a0dc
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/22-rcx_sta.log
@@ -0,0 +1,760 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.45 0.85 1.35 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.45 0.00 1.36 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.34 0.33 1.68 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.34 0.00 1.68 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.39 0.28 1.96 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp3555 (net)
+ 0.39 0.00 1.96 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.96 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.81 clock uncertainty
+ -0.05 0.76 clock reconvergence pessimism
+ 0.00 0.76 library hold time
+ 0.76 data required time
+-----------------------------------------------------------------------------
+ 0.76 data required time
+ -1.96 data arrival time
+-----------------------------------------------------------------------------
+ 1.20 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.55 0.90 1.41 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.55 0.00 1.42 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.30 0.29 1.70 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.01 _033_ (net)
+ 0.30 0.00 1.70 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.20 0.15 1.85 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _041_ (net)
+ 0.20 0.00 1.85 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.18 0.15 2.00 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 _045_ (net)
+ 0.18 0.00 2.00 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.47 0.32 2.32 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.03 fsm_plant_opt.tmp2410 (net)
+ 0.47 0.00 2.32 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.32 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.81 clock uncertainty
+ -0.05 0.76 clock reconvergence pessimism
+ -0.03 0.73 library hold time
+ 0.73 data required time
+-----------------------------------------------------------------------------
+ 0.73 data required time
+ -2.32 data arrival time
+-----------------------------------------------------------------------------
+ 1.59 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.55 0.90 1.41 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.55 0.00 1.42 v _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor4_4)
+ 0.55 0.41 1.82 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_4)
+ 3 0.01 _020_ (net)
+ 0.55 0.00 1.82 ^ _083_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.18 0.17 1.99 v _083_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.01 _025_ (net)
+ 0.18 0.00 1.99 v _084_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.29 0.22 2.21 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _026_ (net)
+ 0.29 0.00 2.21 ^ _089_/I1 (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 0.11 0.27 2.49 ^ _089_/Z (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 1 0.01 _030_ (net)
+ 0.11 0.00 2.49 ^ _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.41 0.27 2.76 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp2409 (net)
+ 0.41 0.00 2.76 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.76 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.81 clock uncertainty
+ -0.03 0.78 clock reconvergence pessimism
+ -0.01 0.77 library hold time
+ 0.77 data required time
+-----------------------------------------------------------------------------
+ 0.77 data required time
+ -2.76 data arrival time
+-----------------------------------------------------------------------------
+ 1.99 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.45 0.85 1.35 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.45 0.00 1.36 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.34 0.33 1.68 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.34 0.00 1.68 ^ _085_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.26 0.21 1.90 v _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.26 0.00 1.90 v _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.15 2.05 ^ _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.16 0.00 2.05 ^ _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.18 0.29 2.34 ^ _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.18 0.00 2.34 ^ _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.64 0.49 2.83 ^ _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 0.64 0.00 2.83 ^ _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.83 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.81 clock uncertainty
+ -0.05 0.76 clock reconvergence pessimism
+ 0.04 0.80 library hold time
+ 0.80 data required time
+-----------------------------------------------------------------------------
+ 0.80 data required time
+ -2.83 data arrival time
+-----------------------------------------------------------------------------
+ 2.04 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.06 0.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 0.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 0.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 0.51 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.45 0.85 1.35 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.04 fsm_plant_opt.state_water_synth_2 (net)
+ 0.45 0.00 1.36 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 0.34 0.33 1.68 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_2)
+ 4 0.02 _002_ (net)
+ 0.34 0.00 1.68 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.60 0.40 2.08 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 6 0.03 _008_ (net)
+ 0.60 0.00 2.08 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.14 0.43 2.51 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.01 _054_ (net)
+ 0.14 0.00 2.51 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.39 0.37 2.87 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.02 fsm_plant_opt.tmp2411 (net)
+ 0.39 0.00 2.88 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.88 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 0.81 clock uncertainty
+ -0.03 0.78 clock reconvergence pessimism
+ 0.00 0.78 library hold time
+ 0.78 data required time
+-----------------------------------------------------------------------------
+ 0.78 data required time
+ -2.88 data arrival time
+-----------------------------------------------------------------------------
+ 2.09 slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.14 0.06 6.06 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.14 0.00 6.06 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.12 0.83 6.89 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 1.12 0.01 6.90 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.44 0.35 7.25 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.44 0.00 7.25 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.46 0.63 7.88 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.04 _004_ (net)
+ 0.46 0.00 7.88 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.33 0.67 8.55 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.33 0.00 8.55 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.47 0.36 8.91 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.47 0.00 8.91 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.33 0.14 9.05 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.33 0.00 9.05 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.14 0.36 9.41 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.14 0.00 9.41 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.60 0.54 9.95 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 0.60 0.00 9.95 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.87 0.66 10.61 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.03 fsm_plant_opt.tmp3553 (net)
+ 0.87 0.00 10.61 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 10.61 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.14 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.51 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.26 clock uncertainty
+ 0.00 30.26 clock reconvergence pessimism
+ -0.26 30.00 library setup time
+ 30.00 data required time
+-----------------------------------------------------------------------------
+ 30.00 data required time
+ -10.61 data arrival time
+-----------------------------------------------------------------------------
+ 19.38 slack (MET)
+
+
+Startpoint: wbs_sel_i[2] (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.14 0.06 6.06 ^ wbs_sel_i[2] (in)
+ 2 0.01 wbs_sel_i[2] (net)
+ 0.14 0.00 6.06 ^ input8/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2.15 1.46 7.51 ^ input8/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.13 net8 (net)
+ 2.15 0.02 7.54 ^ _098_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.93 0.64 8.17 v _098_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 _037_ (net)
+ 0.93 0.00 8.18 v _099_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.25 0.69 8.87 v _099_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _038_ (net)
+ 0.25 0.00 8.87 v _101_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai211_1)
+ 0.59 0.41 9.28 ^ _101_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai211_1)
+ 2 0.01 _040_ (net)
+ 0.59 0.00 9.28 ^ _113_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.23 0.18 9.46 v _113_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 1 0.01 _051_ (net)
+ 0.23 0.00 9.46 v _115_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.28 0.21 9.68 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.28 0.00 9.68 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.21 0.52 10.20 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.01 _054_ (net)
+ 0.21 0.00 10.20 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.41 0.41 10.61 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 2 0.02 fsm_plant_opt.tmp2411 (net)
+ 0.41 0.00 10.61 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 10.61 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.14 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.51 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.26 clock uncertainty
+ 0.00 30.26 clock reconvergence pessimism
+ -0.25 30.01 library setup time
+ 30.01 data required time
+-----------------------------------------------------------------------------
+ 30.01 data required time
+ -10.61 data arrival time
+-----------------------------------------------------------------------------
+ 19.40 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.91 1.24 1.80 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.91 0.00 1.80 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.51 0.44 2.24 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.51 0.00 2.24 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.78 0.61 2.85 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.78 0.00 2.85 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.36 0.20 3.05 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.36 0.00 3.05 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.88 0.64 3.68 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.05 net10 (net)
+ 0.88 0.00 3.69 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.35 0.57 4.26 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[0] (net)
+ 0.35 0.00 4.26 ^ io_oeb[0] (out)
+ 4.26 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -4.26 data arrival time
+-----------------------------------------------------------------------------
+ 19.49 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.14 0.07 0.07 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 0.07 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.26 0.33 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 0.33 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.23 0.56 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 0.56 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.91 1.24 1.80 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.05 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.91 0.00 1.80 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.51 0.44 2.24 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.51 0.00 2.24 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.78 0.61 2.85 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.78 0.00 2.85 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.36 0.20 3.05 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.36 0.00 3.05 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.84 0.62 3.67 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.05 net11 (net)
+ 0.84 0.00 3.67 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 0.35 0.57 4.24 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_3)
+ 1 0.07 io_oeb[1] (net)
+ 0.35 0.00 4.24 ^ io_oeb[1] (out)
+ 4.24 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (propagated)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -4.24 data arrival time
+-----------------------------------------------------------------------------
+ 19.51 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.14 0.06 6.06 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.14 0.00 6.06 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.12 0.83 6.89 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 1.12 0.01 6.90 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.44 0.35 7.25 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.44 0.00 7.25 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.46 0.63 7.88 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.04 _004_ (net)
+ 0.46 0.00 7.88 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.33 0.67 8.55 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.33 0.00 8.55 v _065_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.30 0.25 8.80 ^ _065_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 _007_ (net)
+ 0.30 0.00 8.80 ^ _066_/A3 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.61 0.43 9.23 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 6 0.03 _008_ (net)
+ 0.61 0.00 9.23 v _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.13 0.40 9.63 v _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _018_ (net)
+ 0.13 0.00 9.63 v _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.91 0.55 10.18 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 fsm_plant_opt.tmp2409 (net)
+ 0.91 0.00 10.18 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 10.18 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.14 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.30 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.51 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_1__leaf_wb_clk_i (net)
+ 0.08 0.00 30.51 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.26 clock uncertainty
+ 0.00 30.26 clock reconvergence pessimism
+ -0.26 30.00 library setup time
+ 30.00 data required time
+-----------------------------------------------------------------------------
+ 30.00 data required time
+ -10.18 data arrival time
+-----------------------------------------------------------------------------
+ 19.81 slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 6.00 6.00 ^ input external delay
+ 0.14 0.06 6.06 ^ wbs_we_i (in)
+ 2 0.01 wbs_we_i (net)
+ 0.14 0.00 6.06 ^ input9/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.12 0.83 6.89 ^ input9/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.07 net9 (net)
+ 1.12 0.01 6.90 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.44 0.35 7.25 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.44 0.00 7.25 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.46 0.63 7.88 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 8 0.04 _004_ (net)
+ 0.46 0.00 7.88 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.33 0.67 8.55 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.33 0.00 8.55 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.47 0.36 8.91 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.47 0.00 8.91 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.33 0.14 9.05 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.33 0.00 9.05 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.14 0.36 9.41 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.01 _057_ (net)
+ 0.14 0.00 9.41 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 0.60 0.54 9.95 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_1)
+ 4 0.04 fsm_plant_opt.tmp3554 (net)
+ 0.60 0.00 9.95 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.87 0.66 10.61 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.03 fsm_plant_opt.tmp3553 (net)
+ 0.87 0.00 10.61 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 10.61 data arrival time
+
+ 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock source latency
+ 0.14 0.06 30.06 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.14 0.00 30.06 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.11 0.24 30.30 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.11 0.00 30.30 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.08 0.21 30.51 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 3 0.01 clknet_1_0__leaf_wb_clk_i (net)
+ 0.08 0.00 30.51 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.25 30.26 clock uncertainty
+ 0.00 30.26 clock reconvergence pessimism
+ -0.26 30.00 library setup time
+ 30.00 data required time
+-----------------------------------------------------------------------------
+ 30.00 data required time
+ -10.61 data arrival time
+-----------------------------------------------------------------------------
+ 19.38 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+max fanout
+
+Pin Limit Fanout Slack
+---------------------------------------------------------
+_062_/Z 4 8 -4 (VIOLATED)
+_128_/Q 4 8 -4 (VIOLATED)
+_129_/Q 4 8 -4 (VIOLATED)
+input5/Z 4 8 -4 (VIOLATED)
+input7/Z 4 8 -4 (VIOLATED)
+input8/Z 4 8 -4 (VIOLATED)
+input9/Z 4 8 -4 (VIOLATED)
+_066_/ZN 4 6 -2 (VIOLATED)
+_074_/ZN 4 6 -2 (VIOLATED)
+_104_/ZN 4 6 -2 (VIOLATED)
+_125_/Q 4 6 -2 (VIOLATED)
+_126_/Q 4 6 -2 (VIOLATED)
+_127_/Q 4 6 -2 (VIOLATED)
+_130_/Q 4 6 -2 (VIOLATED)
+
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 14
+max cap violation count 0
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 19.38
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 1.20
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_127_/CLK ^
+ 0.56
+_130_/CLK ^
+ 0.51 -0.03 0.02
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 1.08e-04 1.52e-05 1.22e-09 1.23e-04 19.3%
+Combinational 3.81e-04 1.32e-04 7.17e-07 5.14e-04 80.7%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 4.89e-04 1.48e-04 7.18e-07 6.37e-04 100.0%
+ 76.7% 23.2% 0.1%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 18642 u^2 4% utilization.
+area_report_end
+Setting global connections for newly added cells...
+[WARNING] Did not save OpenROAD database!
+Writing SDF to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/mca/process_corner_nom/plant_example.sdf...
+Writing timing model to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/mca/process_corner_nom/plant_example.lib...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/signoff/23-gds_ptrs.log b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/23-gds_ptrs.log
new file mode 100644
index 0000000..eb82ea0
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/23-gds_ptrs.log
@@ -0,0 +1,59 @@
+
+Magic 8.3 revision 331 - Compiled on Sat Oct 22 18:40:56 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+ obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Using technology "gf180mcuC", version 1.0.359-0-g35c7265
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: plant_example
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_32".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_64".
+Reading "gf180mcu_fd_sc_mcu7t5v0__endcap".
+Reading "gf180mcu_fd_sc_mcu7t5v0__filltie".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_16".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffq_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16".
+Reading "gf180mcu_fd_sc_mcu7t5v0__antenna".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_8".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__dlyb_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor2_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand2_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand3_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__or2_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__and3_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor4_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand3_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi21_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor4_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi22_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai21_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__and4_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__and2_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__mux2_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand4_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor4_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai211_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__or3_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor3_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_3".
+Reading "gf180mcu_fd_sc_mcu7t5v0__tiel".
+Reading "plant_example".
+ 5000 uses
+ 10000 uses
+[INFO]: Wrote /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/signoff/gds_ptrs.mag including GDS pointers.
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/signoff/23-gdsii.log b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/23-gdsii.log
new file mode 100644
index 0000000..88c264f
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/23-gdsii.log
@@ -0,0 +1,110 @@
+
+Magic 8.3 revision 331 - Compiled on Sat Oct 22 18:40:56 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+ obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Using technology "gf180mcuC", version 1.0.359-0-g35c7265
+Reading LEF data from file /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef.
+This action cannot be undone.
+LEF read, Line 78 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 85 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 95 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 96 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 110 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 114 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 126 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 133 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 134 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 135 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 144 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 145 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 161 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 165 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 177 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 184 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 185 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 186 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 195 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 196 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 212 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 216 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 228 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 235 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 236 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 237 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 246 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 247 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 264 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 268 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 282 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 294 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 295 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 296 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 301 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 302 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read: Processed 1366 lines.
+Reading DEF data from file /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.def.
+This action cannot be undone.
+ Processed 3 vias total.
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_2 geometry by factor of 2
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_1 geometry by factor of 2
+ Processed 14079 subcell instances total.
+ Processed 123 pins total.
+ Processed 2 special nets total.
+ Processed 206 nets total.
+DEF read: Processed 19365 lines.
+Moving label "_016_" from metal3 to via2 in cell plant_example.
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 900.000 x 600.000 ( 0.000, 0.000), ( 900.000, 600.000) 540000.000
+lambda: 18000.00 x 12000.00 ( 0.00, 0.00 ), ( 18000.00, 12000.00) 216000000.00
+internal: 180000 x 120000 ( 0, 0 ), ( 180000, 120000) 21600000000
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fill_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__endcap
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__filltie
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dffq_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__antenna
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fill_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__buf_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__dlyb_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nor2_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nand2_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nand3_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__or2_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__and3_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nor4_4
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nand3_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nor4_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__oai21_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__and4_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__and2_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__mux2_2
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nand4_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nor4_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__oai211_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__or3_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__nor3_1
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_3
+ Generating output for cell gf180mcu_fd_sc_mcu7t5v0__tiel
+ Generating output for cell plant_example
+[INFO]: GDS Write Complete
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/signoff/23-lef.log b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/23-lef.log
new file mode 100644
index 0000000..80371af
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/23-lef.log
@@ -0,0 +1,179 @@
+
+Magic 8.3 revision 331 - Compiled on Sat Oct 22 18:40:56 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+ obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Using technology "gf180mcuC", version 1.0.359-0-g35c7265
+Reading LEF data from file /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef.
+This action cannot be undone.
+LEF read, Line 78 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 85 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 95 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 96 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 110 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 114 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 126 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 133 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 134 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 135 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 144 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 145 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 161 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 165 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 177 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 184 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 185 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 186 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 195 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 196 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 212 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 216 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 228 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 235 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 236 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 237 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 246 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 247 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 264 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 268 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 282 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 294 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 295 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 296 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 301 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 302 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read: Processed 1366 lines.
+plant_example: 10000 rects
+plant_example: 20000 rects
+plant_example: 30000 rects
+[INFO]: Writing abstract LEF
+Generating LEF output /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/plant_example.lef for cell plant_example:
+Diagnostic: Write LEF header for cell plant_example
+Diagnostic: Writing LEF output for cell plant_example
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_32" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_32.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fillcap_32.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fill_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fill_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fill_1.mag.
+The discovered version will be used.
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_1 geometry by factor of 2
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_64" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_64.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fillcap_64.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__endcap" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__endcap.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__endcap.mag.
+The discovered version will be used.
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__endcap geometry by factor of 2
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__filltie" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__filltie.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__filltie.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_16" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_4" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_4.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fillcap_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffq_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__dffq_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__dffq_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__antenna" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__antenna.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__antenna.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fill_2" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fill_2.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fill_2.mag.
+The discovered version will be used.
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_2 geometry by factor of 2
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_8" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_8.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fillcap_8.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_2" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__buf_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__buf_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__buf_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dlyb_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__dlyb_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__dlyb_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nor2_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nor2_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__nor2_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nand2_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nand2_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__nand2_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkinv_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__clkinv_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__clkinv_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nand3_2" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nand3_2.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__nand3_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__or2_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__or2_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__or2_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__and3_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__and3_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__and3_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nor4_4" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nor4_4.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__nor4_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nand3_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nand3_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__nand3_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__aoi21_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__aoi21_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__aoi21_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nor4_2" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nor4_2.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__nor4_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__aoi22_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__aoi22_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__aoi22_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai21_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__oai21_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__oai21_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__and4_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__and4_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__and4_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__and2_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__and2_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__and2_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__mux2_2" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__mux2_2.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__mux2_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nand4_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nand4_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__nand4_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nor4_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nor4_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__nor4_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai211_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__oai211_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__oai211_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__or3_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__or3_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__or3_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nor3_1" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nor3_1.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__nor3_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_3" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__tiel" at bad file path /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/gf180mcu_fd_sc_mcu7t5v0__tiel.mag.
+The cell exists in the search paths at /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__tiel.mag.
+The discovered version will be used.
+Diagnostic: Scale value is 0.005000
+[INFO]: LEF Write Complete
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/signoff/23-maglef.log b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/23-maglef.log
new file mode 100644
index 0000000..36753b3
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/23-maglef.log
@@ -0,0 +1,18 @@
+
+Magic 8.3 revision 331 - Compiled on Sat Oct 22 18:40:56 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+ obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Using technology "gf180mcuC", version 1.0.359-0-g35c7265
+Reading LEF data from file /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/plant_example.lef.
+This action cannot be undone.
+LEF read: Processed 1164 lines.
+[INFO]: DONE GENERATING MAGLEF VIEW
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/signoff/24-spice.log b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/24-spice.log
new file mode 100644
index 0000000..2e82c47
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/24-spice.log
@@ -0,0 +1,106 @@
+
+Magic 8.3 revision 331 - Compiled on Sat Oct 22 18:40:56 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+ obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Using technology "gf180mcuC", version 1.0.359-0-g35c7265
+Reading LEF data from file /localtmp/asic/gf180/pdk/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef.
+This action cannot be undone.
+LEF read, Line 78 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 85 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 95 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 96 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 110 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 114 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 126 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 133 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 134 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 135 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 144 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 145 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 161 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 165 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 177 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 184 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 185 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 186 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 195 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 196 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 212 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 216 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 228 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 235 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 236 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 237 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 246 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 247 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read, Line 264 (Message): Unknown keyword "ARRAYSPACING" in LEF file; ignoring.
+LEF read, Line 268 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 282 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 294 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
+LEF read, Line 295 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 296 (Message): Unknown keyword "ANTENNAGATEPLUSDIFF" in LEF file; ignoring.
+LEF read, Line 301 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
+LEF read, Line 302 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
+LEF read: Processed 1366 lines.
+Reading DEF data from file /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.def.
+This action cannot be undone.
+ Processed 3 vias total.
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_2 geometry by factor of 2
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_1 geometry by factor of 2
+Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__endcap geometry by factor of 2
+ Processed 14079 subcell instances total.
+ Processed 123 pins total.
+ Processed 2 special nets total.
+ Processed 206 nets total.
+DEF read: Processed 19365 lines.
+Moving label "_016_" from metal3 to via2 in cell plant_example.
+Processing plant_example
+Extracting gf180mcu_fd_sc_mcu7t5v0__fillcap_32 into gf180mcu_fd_sc_mcu7t5v0__fillcap_32.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__fill_1 into gf180mcu_fd_sc_mcu7t5v0__fill_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__fillcap_64 into gf180mcu_fd_sc_mcu7t5v0__fillcap_64.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__endcap into gf180mcu_fd_sc_mcu7t5v0__endcap.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__filltie into gf180mcu_fd_sc_mcu7t5v0__filltie.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__fillcap_16 into gf180mcu_fd_sc_mcu7t5v0__fillcap_16.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__fillcap_4 into gf180mcu_fd_sc_mcu7t5v0__fillcap_4.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__dffq_1 into gf180mcu_fd_sc_mcu7t5v0__dffq_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 into gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__fill_2 into gf180mcu_fd_sc_mcu7t5v0__fill_2.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__antenna into gf180mcu_fd_sc_mcu7t5v0__antenna.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__fillcap_8 into gf180mcu_fd_sc_mcu7t5v0__fillcap_8.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 into gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__buf_1 into gf180mcu_fd_sc_mcu7t5v0__buf_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__dlyb_1 into gf180mcu_fd_sc_mcu7t5v0__dlyb_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__nor2_1 into gf180mcu_fd_sc_mcu7t5v0__nor2_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__nand2_1 into gf180mcu_fd_sc_mcu7t5v0__nand2_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__clkinv_1 into gf180mcu_fd_sc_mcu7t5v0__clkinv_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 into gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__nand3_2 into gf180mcu_fd_sc_mcu7t5v0__nand3_2.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__or2_1 into gf180mcu_fd_sc_mcu7t5v0__or2_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__and3_1 into gf180mcu_fd_sc_mcu7t5v0__and3_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__nor4_4 into gf180mcu_fd_sc_mcu7t5v0__nor4_4.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__aoi21_1 into gf180mcu_fd_sc_mcu7t5v0__aoi21_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__nor4_2 into gf180mcu_fd_sc_mcu7t5v0__nor4_2.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__and4_1 into gf180mcu_fd_sc_mcu7t5v0__and4_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__nand3_1 into gf180mcu_fd_sc_mcu7t5v0__nand3_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__oai21_1 into gf180mcu_fd_sc_mcu7t5v0__oai21_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__aoi22_1 into gf180mcu_fd_sc_mcu7t5v0__aoi22_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__and2_1 into gf180mcu_fd_sc_mcu7t5v0__and2_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__mux2_2 into gf180mcu_fd_sc_mcu7t5v0__mux2_2.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__nand4_1 into gf180mcu_fd_sc_mcu7t5v0__nand4_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__nor4_1 into gf180mcu_fd_sc_mcu7t5v0__nor4_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__oai211_1 into gf180mcu_fd_sc_mcu7t5v0__oai211_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__or3_1 into gf180mcu_fd_sc_mcu7t5v0__or3_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__nor3_1 into gf180mcu_fd_sc_mcu7t5v0__nor3_1.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 into gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.ext:
+Extracting gf180mcu_fd_sc_mcu7t5v0__tiel into gf180mcu_fd_sc_mcu7t5v0__tiel.ext:
+Extracting plant_example into plant_example.ext:
+exttospice finished.
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/signoff/25-write_powered_def.log b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/25-write_powered_def.log
new file mode 100644
index 0000000..f5bc975
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/25-write_powered_def.log
@@ -0,0 +1,21 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO ODB-0222] Reading LEF file: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/merged.nom.lef
+[INFO ODB-0223] Created 13 technology layers
+[INFO ODB-0224] Created 60 technology vias
+[INFO ODB-0225] Created 229 library cells
+[INFO ODB-0226] Finished LEF file: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/merged.nom.lef
+[INFO ODB-0127] Reading DEF file: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.def
+[INFO ODB-0128] Design: plant_example
+[INFO ODB-0130] Created 123 pins.
+[INFO ODB-0131] Created 14079 components and 28586 component-terminals.
+[INFO ODB-0132] Created 2 special nets and 28158 connections.
+[INFO ODB-0133] Created 206 nets and 428 connections.
+[INFO ODB-0134] Finished DEF file: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/routing/plant_example.def
+Top-level design name: plant_example
+Found default power net 'vdd'
+Found default ground net 'vss'
+Found 1 power ports.
+Found 1 ground ports.
+Modified power connections of 14079/14079 cells.
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/signoff/25-write_powered_verilog.log b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/25-write_powered_verilog.log
new file mode 100644
index 0000000..5b04305
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/25-write_powered_verilog.log
@@ -0,0 +1,7 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Setting global connections for newly added cells...
+[WARNING] Did not save OpenROAD database!
+Writing netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/signoff/24-plant_example.nl.v...
+Writing powered netlist to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/signoff/24-plant_example.pnl.v...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/signoff/27-lvs.lef.log b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/27-lvs.lef.log
new file mode 100644
index 0000000..efe567b
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/27-lvs.lef.log
@@ -0,0 +1,517 @@
+Netgen 1.5.242 compiled on Wed Nov 16 22:54:20 UTC 2022
+Warning: netgen command 'format' use fully-qualified name '::netgen::format'
+Warning: netgen command 'global' use fully-qualified name '::netgen::global'
+Generating JSON file result
+Reading netlist file /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/plant_example.spice
+Reading netlist file /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/signoff/24-plant_example.pnl.v
+Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to match.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__clkinv_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__or2_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__nand3_2.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__buf_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__nor2_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__nand3_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__nand2_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__nor4_2.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__nand4_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__and2_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__nor4_4.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__and3_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__oai21_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__mux2_2.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__aoi21_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__aoi22_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__and4_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__nor4_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__oai211_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__or3_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__nor3_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__dffq_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__tiel.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__endcap.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__filltie.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__dlyb_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__antenna.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__fillcap_32.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__fill_1.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__fill_2.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__fillcap_8.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__fillcap_4.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__fillcap_16.
+Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
+Reading setup file /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/netgen/gf180mcuC_setup.tcl
+Comparison output logged to file /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/27-plant_example.lef.lvs.log
+Logging to file "/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/27-plant_example.lef.lvs.log" enabled
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_64'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_64 contains 0 device instances.
+Circuit contains 0 nets, and 2 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_64'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_64 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_64 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_4'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_4 contains 0 device instances.
+Circuit contains 0 nets, and 2 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_4'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_4 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_16'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_16 contains 0 device instances.
+Circuit contains 0 nets, and 2 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_16'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_16 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_16 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_8'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_8 contains 0 device instances.
+Circuit contains 0 nets, and 2 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_8'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_8 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_8 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_32'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_32 contains 0 device instances.
+Circuit contains 0 nets, and 2 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_32'
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_32 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_32 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__antenna'
+Circuit gf180mcu_fd_sc_mcu7t5v0__antenna contains 0 device instances.
+Circuit contains 0 nets, and 3 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__antenna'
+Circuit gf180mcu_fd_sc_mcu7t5v0__antenna contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__antenna contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__buf_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__buf_1 contains 0 device instances.
+Circuit contains 0 nets, and 4 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__buf_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__buf_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__buf_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__aoi21_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__aoi21_1 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__aoi21_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__aoi21_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__aoi21_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__dffq_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__dffq_1 contains 0 device instances.
+Circuit contains 0 nets, and 5 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__dffq_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__dffq_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__dffq_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__clkinv_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkinv_1 contains 0 device instances.
+Circuit contains 0 nets, and 4 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__clkinv_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkinv_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkinv_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__clkbuf_3'
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 contains 0 device instances.
+Circuit contains 0 nets, and 4 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__clkbuf_3'
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nand3_2'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand3_2 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nand3_2'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand3_2 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand3_2 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nand2_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand2_1 contains 0 device instances.
+Circuit contains 0 nets, and 5 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nand2_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand2_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand2_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__aoi22_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__aoi22_1 contains 0 device instances.
+Circuit contains 0 nets, and 7 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__aoi22_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__aoi22_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__aoi22_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__and4_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__and4_1 contains 0 device instances.
+Circuit contains 0 nets, and 7 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__and4_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__and4_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__and4_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__tiel'
+Circuit gf180mcu_fd_sc_mcu7t5v0__tiel contains 0 device instances.
+Circuit contains 0 nets, and 3 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__tiel'
+Circuit gf180mcu_fd_sc_mcu7t5v0__tiel contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__tiel contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__and3_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__and3_1 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__and3_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__and3_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__and3_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nor4_4'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor4_4 contains 0 device instances.
+Circuit contains 0 nets, and 7 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nor4_4'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor4_4 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor4_4 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__and2_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__and2_1 contains 0 device instances.
+Circuit contains 0 nets, and 5 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__and2_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__and2_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__and2_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__dlyb_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__dlyb_1 contains 0 device instances.
+Circuit contains 0 nets, and 4 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__dlyb_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__dlyb_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__dlyb_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__or2_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__or2_1 contains 0 device instances.
+Circuit contains 0 nets, and 5 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__or2_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__or2_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__or2_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nand3_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand3_1 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nand3_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand3_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand3_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nand4_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand4_1 contains 0 device instances.
+Circuit contains 0 nets, and 7 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nand4_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand4_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__nand4_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__clkbuf_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 contains 0 device instances.
+Circuit contains 0 nets, and 4 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__clkbuf_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nor2_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor2_1 contains 0 device instances.
+Circuit contains 0 nets, and 5 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nor2_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor2_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor2_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__oai21_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__oai21_1 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__oai21_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__oai21_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__oai21_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nor3_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor3_1 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nor3_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor3_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor3_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__clkbuf_2'
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 contains 0 device instances.
+Circuit contains 0 nets, and 4 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__clkbuf_2'
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nor4_2'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor4_2 contains 0 device instances.
+Circuit contains 0 nets, and 7 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nor4_2'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor4_2 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor4_2 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__or3_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__or3_1 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__or3_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__or3_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__or3_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__oai211_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__oai211_1 contains 0 device instances.
+Circuit contains 0 nets, and 7 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__oai211_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__oai211_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__oai211_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nor4_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor4_1 contains 0 device instances.
+Circuit contains 0 nets, and 7 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__nor4_1'
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor4_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__nor4_1 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__clkbuf_16'
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 contains 0 device instances.
+Circuit contains 0 nets, and 4 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__clkbuf_16'
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 contains no devices.
+
+Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__mux2_2'
+Circuit gf180mcu_fd_sc_mcu7t5v0__mux2_2 contains 0 device instances.
+Circuit contains 0 nets, and 6 disconnected pins.
+Contents of circuit 2: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__mux2_2'
+Circuit gf180mcu_fd_sc_mcu7t5v0__mux2_2 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit gf180mcu_fd_sc_mcu7t5v0__mux2_2 contains no devices.
+
+Contents of circuit 1: Circuit: 'plant_example'
+Circuit plant_example contains 6947 device instances.
+ Class: gf180mcu_fd_sc_mcu7t5v0__nand3_1 instances: 2
+ Class: gf180mcu_fd_sc_mcu7t5v0__nand3_2 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__dffq_1 instances: 6
+ Class: gf180mcu_fd_sc_mcu7t5v0__dlyb_1 instances: 5
+ Class: gf180mcu_fd_sc_mcu7t5v0__and3_1 instances: 2
+ Class: gf180mcu_fd_sc_mcu7t5v0__nand2_1 instances: 12
+ Class: gf180mcu_fd_sc_mcu7t5v0__oai211_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__aoi22_1 instances: 2
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 instances: 5
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__mux2_2 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 instances: 3
+ Class: gf180mcu_fd_sc_mcu7t5v0__and2_1 instances: 3
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor4_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor4_2 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor4_4 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkinv_1 instances: 8
+ Class: gf180mcu_fd_sc_mcu7t5v0__buf_1 instances: 4
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 instances: 3
+ Class: gf180mcu_fd_sc_mcu7t5v0__aoi21_1 instances: 6
+ Class: gf180mcu_fd_sc_mcu7t5v0__tiel instances: 73
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor3_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__or3_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__oai21_1 instances: 5
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_4 instances: 3204
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_8 instances: 74
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_64 instances: 3039
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_16 instances: 196
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor2_1 instances: 6
+ Class: gf180mcu_fd_sc_mcu7t5v0__antenna instances: 79
+ Class: gf180mcu_fd_sc_mcu7t5v0__nand4_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__or2_1 instances: 2
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_32 instances: 194
+ Class: gf180mcu_fd_sc_mcu7t5v0__and4_1 instances: 4
+Circuit contains 173 nets, and 35 disconnected pins.
+Contents of circuit 2: Circuit: 'plant_example'
+Circuit plant_example contains 6947 device instances.
+ Class: gf180mcu_fd_sc_mcu7t5v0__nand3_1 instances: 2
+ Class: gf180mcu_fd_sc_mcu7t5v0__nand3_2 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__dffq_1 instances: 6
+ Class: gf180mcu_fd_sc_mcu7t5v0__dlyb_1 instances: 5
+ Class: gf180mcu_fd_sc_mcu7t5v0__and3_1 instances: 2
+ Class: gf180mcu_fd_sc_mcu7t5v0__nand2_1 instances: 12
+ Class: gf180mcu_fd_sc_mcu7t5v0__oai211_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__aoi22_1 instances: 2
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 instances: 5
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 instances: 3
+ Class: gf180mcu_fd_sc_mcu7t5v0__mux2_2 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__and2_1 instances: 3
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor4_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor4_2 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor4_4 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkinv_1 instances: 8
+ Class: gf180mcu_fd_sc_mcu7t5v0__buf_1 instances: 4
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 instances: 3
+ Class: gf180mcu_fd_sc_mcu7t5v0__aoi21_1 instances: 6
+ Class: gf180mcu_fd_sc_mcu7t5v0__tiel instances: 73
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor3_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__or3_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__oai21_1 instances: 5
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_4 instances: 3204
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_8 instances: 74
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_64 instances: 3039
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_16 instances: 196
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor2_1 instances: 6
+ Class: gf180mcu_fd_sc_mcu7t5v0__antenna instances: 79
+ Class: gf180mcu_fd_sc_mcu7t5v0__nand4_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__or2_1 instances: 2
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_32 instances: 194
+ Class: gf180mcu_fd_sc_mcu7t5v0__and4_1 instances: 4
+Circuit contains 173 nets, and 35 disconnected pins.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1: Circuit: 'plant_example'
+Circuit plant_example contains 205 device instances.
+ Class: gf180mcu_fd_sc_mcu7t5v0__nand3_1 instances: 2
+ Class: gf180mcu_fd_sc_mcu7t5v0__nand3_2 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__dffq_1 instances: 6
+ Class: gf180mcu_fd_sc_mcu7t5v0__dlyb_1 instances: 5
+ Class: gf180mcu_fd_sc_mcu7t5v0__and3_1 instances: 2
+ Class: gf180mcu_fd_sc_mcu7t5v0__nand2_1 instances: 12
+ Class: gf180mcu_fd_sc_mcu7t5v0__oai211_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__aoi22_1 instances: 2
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 instances: 5
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__mux2_2 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 instances: 3
+ Class: gf180mcu_fd_sc_mcu7t5v0__and2_1 instances: 3
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor4_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor4_2 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor4_4 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkinv_1 instances: 8
+ Class: gf180mcu_fd_sc_mcu7t5v0__buf_1 instances: 4
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 instances: 3
+ Class: gf180mcu_fd_sc_mcu7t5v0__aoi21_1 instances: 6
+ Class: gf180mcu_fd_sc_mcu7t5v0__tiel instances: 73
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor3_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__or3_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__oai21_1 instances: 5
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_4 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_8 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_64 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_16 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor2_1 instances: 6
+ Class: gf180mcu_fd_sc_mcu7t5v0__antenna instances: 39
+ Class: gf180mcu_fd_sc_mcu7t5v0__nand4_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__or2_1 instances: 2
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_32 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__and4_1 instances: 4
+Circuit contains 173 nets, and 35 disconnected pins.
+Contents of circuit 2: Circuit: 'plant_example'
+Circuit plant_example contains 205 device instances.
+ Class: gf180mcu_fd_sc_mcu7t5v0__nand3_1 instances: 2
+ Class: gf180mcu_fd_sc_mcu7t5v0__nand3_2 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__dffq_1 instances: 6
+ Class: gf180mcu_fd_sc_mcu7t5v0__dlyb_1 instances: 5
+ Class: gf180mcu_fd_sc_mcu7t5v0__and3_1 instances: 2
+ Class: gf180mcu_fd_sc_mcu7t5v0__nand2_1 instances: 12
+ Class: gf180mcu_fd_sc_mcu7t5v0__oai211_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__aoi22_1 instances: 2
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 instances: 5
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 instances: 3
+ Class: gf180mcu_fd_sc_mcu7t5v0__mux2_2 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__and2_1 instances: 3
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor4_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor4_2 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor4_4 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkinv_1 instances: 8
+ Class: gf180mcu_fd_sc_mcu7t5v0__buf_1 instances: 4
+ Class: gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 instances: 3
+ Class: gf180mcu_fd_sc_mcu7t5v0__aoi21_1 instances: 6
+ Class: gf180mcu_fd_sc_mcu7t5v0__tiel instances: 73
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor3_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__or3_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__oai21_1 instances: 5
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_4 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_8 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_64 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_16 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__nor2_1 instances: 6
+ Class: gf180mcu_fd_sc_mcu7t5v0__antenna instances: 39
+ Class: gf180mcu_fd_sc_mcu7t5v0__nand4_1 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__or2_1 instances: 2
+ Class: gf180mcu_fd_sc_mcu7t5v0__fillcap_32 instances: 1
+ Class: gf180mcu_fd_sc_mcu7t5v0__and4_1 instances: 4
+Circuit contains 173 nets, and 35 disconnected pins.
+
+Circuit 1 contains 205 devices, Circuit 2 contains 205 devices.
+Circuit 1 contains 173 nets, Circuit 2 contains 173 nets.
+
+
+Final result:
+Circuits match uniquely.
+.
+Logging to file "/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/27-plant_example.lef.lvs.log" disabled
+LVS Done.
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/signoff/27-plant_example.lef.lvs.json b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/27-plant_example.lef.lvs.json
new file mode 100644
index 0000000..9ed1d23
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/27-plant_example.lef.lvs.json
@@ -0,0 +1,910 @@
+[
+ {
+ "pins": [
+ [
+ "VDD",
+ "VSS"
+ ], [
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "VDD",
+ "VSS"
+ ], [
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "VDD",
+ "VSS"
+ ], [
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "VDD",
+ "VSS"
+ ], [
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "VDD",
+ "VSS"
+ ], [
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "I",
+ "VDD",
+ "VSS"
+ ], [
+ "I",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "I",
+ "Z",
+ "VDD",
+ "VSS"
+ ], [
+ "I",
+ "Z",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "B",
+ "ZN",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "B",
+ "ZN",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "D",
+ "CLK",
+ "Q",
+ "VDD",
+ "VSS"
+ ], [
+ "D",
+ "CLK",
+ "Q",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "I",
+ "ZN",
+ "VDD",
+ "VSS"
+ ], [
+ "I",
+ "ZN",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "I",
+ "Z",
+ "VDD",
+ "VSS"
+ ], [
+ "I",
+ "Z",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "A3",
+ "ZN",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "A3",
+ "ZN",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "ZN",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "ZN",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "B1",
+ "B2",
+ "ZN",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "B1",
+ "B2",
+ "ZN",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "A3",
+ "A4",
+ "Z",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "A3",
+ "A4",
+ "Z",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "ZN",
+ "VDD",
+ "VSS"
+ ], [
+ "ZN",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "A3",
+ "Z",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "A3",
+ "Z",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "A3",
+ "A4",
+ "ZN",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "A3",
+ "A4",
+ "ZN",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "Z",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "Z",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "I",
+ "Z",
+ "VDD",
+ "VSS"
+ ], [
+ "I",
+ "Z",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "Z",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "Z",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "A3",
+ "ZN",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "A3",
+ "ZN",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "A3",
+ "A4",
+ "ZN",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "A3",
+ "A4",
+ "ZN",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "I",
+ "Z",
+ "VDD",
+ "VSS"
+ ], [
+ "I",
+ "Z",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "ZN",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "ZN",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "B",
+ "ZN",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "B",
+ "ZN",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "A3",
+ "ZN",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "A3",
+ "ZN",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "I",
+ "Z",
+ "VDD",
+ "VSS"
+ ], [
+ "I",
+ "Z",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "A3",
+ "A4",
+ "ZN",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "A3",
+ "A4",
+ "ZN",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "A3",
+ "Z",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "A3",
+ "Z",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "B",
+ "C",
+ "ZN",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "B",
+ "C",
+ "ZN",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "A1",
+ "A2",
+ "A3",
+ "A4",
+ "ZN",
+ "VDD",
+ "VSS"
+ ], [
+ "A1",
+ "A2",
+ "A3",
+ "A4",
+ "ZN",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "I",
+ "Z",
+ "VDD",
+ "VSS"
+ ], [
+ "I",
+ "Z",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "pins": [
+ [
+ "I0",
+ "I1",
+ "S",
+ "Z",
+ "VDD",
+ "VSS"
+ ], [
+ "I0",
+ "I1",
+ "S",
+ "Z",
+ "VDD",
+ "VSS"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "plant_example",
+ "plant_example"
+ ],
+ "devices": [
+ [
+ ["gf180mcu_fd_sc_mcu7t5v0__fillcap_64", 1],
+ ["gf180mcu_fd_sc_mcu7t5v0__fillcap_4", 1],
+ ["gf180mcu_fd_sc_mcu7t5v0__fillcap_16", 1],
+ ["gf180mcu_fd_sc_mcu7t5v0__fillcap_8", 1],
+ ["gf180mcu_fd_sc_mcu7t5v0__fillcap_32", 1],
+ ["gf180mcu_fd_sc_mcu7t5v0__antenna", 39],
+ ["gf180mcu_fd_sc_mcu7t5v0__buf_1", 4],
+ ["gf180mcu_fd_sc_mcu7t5v0__aoi21_1", 6],
+ ["gf180mcu_fd_sc_mcu7t5v0__dffq_1", 6],
+ ["gf180mcu_fd_sc_mcu7t5v0__clkinv_1", 8],
+ ["gf180mcu_fd_sc_mcu7t5v0__clkbuf_3", 3],
+ ["gf180mcu_fd_sc_mcu7t5v0__nand3_2", 1],
+ ["gf180mcu_fd_sc_mcu7t5v0__nand2_1", 12],
+ ["gf180mcu_fd_sc_mcu7t5v0__aoi22_1", 2],
+ ["gf180mcu_fd_sc_mcu7t5v0__and4_1", 4],
+ ["gf180mcu_fd_sc_mcu7t5v0__tiel", 73],
+ ["gf180mcu_fd_sc_mcu7t5v0__and3_1", 2],
+ ["gf180mcu_fd_sc_mcu7t5v0__nor4_4", 1],
+ ["gf180mcu_fd_sc_mcu7t5v0__and2_1", 3],
+ ["gf180mcu_fd_sc_mcu7t5v0__dlyb_1", 5],
+ ["gf180mcu_fd_sc_mcu7t5v0__or2_1", 2],
+ ["gf180mcu_fd_sc_mcu7t5v0__nand3_1", 2],
+ ["gf180mcu_fd_sc_mcu7t5v0__nand4_1", 1],
+ ["gf180mcu_fd_sc_mcu7t5v0__clkbuf_1", 5],
+ ["gf180mcu_fd_sc_mcu7t5v0__nor2_1", 6],
+ ["gf180mcu_fd_sc_mcu7t5v0__oai21_1", 5],
+ ["gf180mcu_fd_sc_mcu7t5v0__nor3_1", 1],
+ ["gf180mcu_fd_sc_mcu7t5v0__clkbuf_2", 1],
+ ["gf180mcu_fd_sc_mcu7t5v0__nor4_2", 1],
+ ["gf180mcu_fd_sc_mcu7t5v0__or3_1", 1],
+ ["gf180mcu_fd_sc_mcu7t5v0__oai211_1", 1],
+ ["gf180mcu_fd_sc_mcu7t5v0__nor4_1", 1],
+ ["gf180mcu_fd_sc_mcu7t5v0__clkbuf_16", 3],
+ ["gf180mcu_fd_sc_mcu7t5v0__mux2_2", 1 ]
+ ], [
+ ["gf180mcu_fd_sc_mcu7t5v0__fillcap_64", 1 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__fillcap_4", 1 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__fillcap_16", 1 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__fillcap_8", 1 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__fillcap_32", 1 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__antenna", 39 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__buf_1", 4 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__aoi21_1", 6 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__dffq_1", 6 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__clkinv_1", 8 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__clkbuf_3", 3 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__nand3_2", 1 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__nand2_1", 12 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__aoi22_1", 2 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__and4_1", 4 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__tiel", 73 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__and3_1", 2 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__nor4_4", 1 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__and2_1", 3 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__dlyb_1", 5 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__or2_1", 2 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__nand3_1", 2 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__nand4_1", 1 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__clkbuf_1", 5 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__nor2_1", 6 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__oai21_1", 5 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__nor3_1", 1 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__clkbuf_2", 1 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__nor4_2", 1 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__or3_1", 1 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__oai211_1", 1 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__nor4_1", 1 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__clkbuf_16", 3 ],
+ ["gf180mcu_fd_sc_mcu7t5v0__mux2_2", 1 ]
+ ]
+ ],
+ "nets": [
+ 173,
+ 173
+ ],
+ "badnets": [
+ ],
+ "badelements": [
+ ],
+ "pins": [
+ [
+ "io_oeb[1]",
+ "io_out[0]",
+ "io_oeb[0]",
+ "io_oeb[8]",
+ "io_oeb[7]",
+ "io_oeb[18]",
+ "io_oeb[6]",
+ "io_oeb[17]",
+ "io_oeb[28]",
+ "io_out[1]",
+ "io_oeb[5]",
+ "io_oeb[16]",
+ "io_oeb[27]",
+ "io_out[11]",
+ "io_oeb[4]",
+ "io_oeb[15]",
+ "io_oeb[26]",
+ "io_oeb[37]",
+ "io_out[10]",
+ "io_out[21]",
+ "io_oeb[14]",
+ "io_oeb[25]",
+ "io_oeb[36]",
+ "io_oeb[3]",
+ "io_out[20]",
+ "io_out[31]",
+ "io_out[9]",
+ "io_oeb[13]",
+ "io_oeb[24]",
+ "io_oeb[35]",
+ "io_oeb[2]",
+ "io_out[19]",
+ "io_out[30]",
+ "io_out[8]",
+ "io_oeb[23]",
+ "io_oeb[34]",
+ "io_oeb[12]",
+ "io_out[29]",
+ "io_out[7]",
+ "io_out[18]",
+ "io_oeb[22]",
+ "io_oeb[33]",
+ "io_oeb[11]",
+ "io_out[28]",
+ "io_out[6]",
+ "io_out[17]",
+ "io_oeb[32]",
+ "io_oeb[10]",
+ "io_oeb[21]",
+ "io_out[5]",
+ "io_out[16]",
+ "io_out[27]",
+ "io_oeb[9]",
+ "io_oeb[20]",
+ "io_oeb[31]",
+ "io_out[37]",
+ "io_out[4]",
+ "io_out[15]",
+ "io_out[26]",
+ "io_oeb[19]",
+ "io_oeb[30]",
+ "io_out[14]",
+ "io_out[25]",
+ "io_out[36]",
+ "io_out[3]",
+ "io_oeb[29]",
+ "io_out[13]",
+ "io_out[24]",
+ "io_out[35]",
+ "io_out[2]",
+ "io_out[23]",
+ "io_out[34]",
+ "io_out[12]",
+ "io_out[22]",
+ "io_out[33]",
+ "io_out[32]",
+ "wb_clk_i",
+ "io_in[0]",
+ "wb_rst_i",
+ "io_in[3]",
+ "wbs_sel_i[0]",
+ "io_in[1]",
+ "io_in[2]",
+ "wbs_we_i",
+ "wbs_sel_i[1]",
+ "wbs_sel_i[2]",
+ "vdd",
+ "vss",
+ "io_in[10]",
+ "io_in[11]",
+ "io_in[12]",
+ "io_in[13]",
+ "io_in[14]",
+ "io_in[15]",
+ "io_in[16]",
+ "io_in[17]",
+ "io_in[18]",
+ "io_in[19]",
+ "io_in[20]",
+ "io_in[21]",
+ "io_in[22]",
+ "io_in[23]",
+ "io_in[24]",
+ "io_in[25]",
+ "io_in[26]",
+ "io_in[27]",
+ "io_in[28]",
+ "io_in[29]",
+ "io_in[30]",
+ "io_in[31]",
+ "io_in[32]",
+ "io_in[33]",
+ "io_in[34]",
+ "io_in[35]",
+ "io_in[36]",
+ "io_in[37]",
+ "io_in[4]",
+ "io_in[5]",
+ "io_in[6]",
+ "io_in[7]",
+ "io_in[8]",
+ "io_in[9]",
+ "wbs_sel_i[3]"
+ ], [
+ "io_oeb[1]",
+ "io_out[0]",
+ "io_oeb[0]",
+ "io_oeb[8]",
+ "io_oeb[7]",
+ "io_oeb[18]",
+ "io_oeb[6]",
+ "io_oeb[17]",
+ "io_oeb[28]",
+ "io_out[1]",
+ "io_oeb[5]",
+ "io_oeb[16]",
+ "io_oeb[27]",
+ "io_out[11]",
+ "io_oeb[4]",
+ "io_oeb[15]",
+ "io_oeb[26]",
+ "io_oeb[37]",
+ "io_out[10]",
+ "io_out[21]",
+ "io_oeb[14]",
+ "io_oeb[25]",
+ "io_oeb[36]",
+ "io_oeb[3]",
+ "io_out[20]",
+ "io_out[31]",
+ "io_out[9]",
+ "io_oeb[13]",
+ "io_oeb[24]",
+ "io_oeb[35]",
+ "io_oeb[2]",
+ "io_out[19]",
+ "io_out[30]",
+ "io_out[8]",
+ "io_oeb[23]",
+ "io_oeb[34]",
+ "io_oeb[12]",
+ "io_out[29]",
+ "io_out[7]",
+ "io_out[18]",
+ "io_oeb[22]",
+ "io_oeb[33]",
+ "io_oeb[11]",
+ "io_out[28]",
+ "io_out[6]",
+ "io_out[17]",
+ "io_oeb[32]",
+ "io_oeb[10]",
+ "io_oeb[21]",
+ "io_out[5]",
+ "io_out[16]",
+ "io_out[27]",
+ "io_oeb[9]",
+ "io_oeb[20]",
+ "io_oeb[31]",
+ "io_out[37]",
+ "io_out[4]",
+ "io_out[15]",
+ "io_out[26]",
+ "io_oeb[19]",
+ "io_oeb[30]",
+ "io_out[14]",
+ "io_out[25]",
+ "io_out[36]",
+ "io_out[3]",
+ "io_oeb[29]",
+ "io_out[13]",
+ "io_out[24]",
+ "io_out[35]",
+ "io_out[2]",
+ "io_out[23]",
+ "io_out[34]",
+ "io_out[12]",
+ "io_out[22]",
+ "io_out[33]",
+ "io_out[32]",
+ "wb_clk_i",
+ "io_in[0]",
+ "wb_rst_i",
+ "io_in[3]",
+ "wbs_sel_i[0]",
+ "io_in[1]",
+ "io_in[2]",
+ "wbs_we_i",
+ "wbs_sel_i[1]",
+ "wbs_sel_i[2]",
+ "vdd",
+ "vss",
+ "io_in[10]",
+ "io_in[11]",
+ "io_in[12]",
+ "io_in[13]",
+ "io_in[14]",
+ "io_in[15]",
+ "io_in[16]",
+ "io_in[17]",
+ "io_in[18]",
+ "io_in[19]",
+ "io_in[20]",
+ "io_in[21]",
+ "io_in[22]",
+ "io_in[23]",
+ "io_in[24]",
+ "io_in[25]",
+ "io_in[26]",
+ "io_in[27]",
+ "io_in[28]",
+ "io_in[29]",
+ "io_in[30]",
+ "io_in[31]",
+ "io_in[32]",
+ "io_in[33]",
+ "io_in[34]",
+ "io_in[35]",
+ "io_in[36]",
+ "io_in[37]",
+ "io_in[4]",
+ "io_in[5]",
+ "io_in[6]",
+ "io_in[7]",
+ "io_in[8]",
+ "io_in[9]",
+ "wbs_sel_i[3]"
+ ]
+ ]
+ }
+]
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/signoff/27-plant_example.lef.lvs.log b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/27-plant_example.lef.lvs.log
new file mode 100644
index 0000000..78f870c
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/27-plant_example.lef.lvs.log
@@ -0,0 +1,957 @@
+
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__fillcap_64 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__fillca |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__fillca
+-------------------------------------------|-------------------------------------------
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__fillcap_64 and gf180mcu_fd_sc_mcu7t5v0__fillcap_64 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__fillcap_4 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__fillca |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__fillca
+-------------------------------------------|-------------------------------------------
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__fillcap_4 and gf180mcu_fd_sc_mcu7t5v0__fillcap_4 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__fillcap_16 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__fillca |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__fillca
+-------------------------------------------|-------------------------------------------
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__fillcap_16 and gf180mcu_fd_sc_mcu7t5v0__fillcap_16 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__fillcap_8 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__fillca |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__fillca
+-------------------------------------------|-------------------------------------------
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__fillcap_8 and gf180mcu_fd_sc_mcu7t5v0__fillcap_8 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__fillcap_32 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__fillca |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__fillca
+-------------------------------------------|-------------------------------------------
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__fillcap_32 and gf180mcu_fd_sc_mcu7t5v0__fillcap_32 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__antenna (0) disconnected node: I
+Cell gf180mcu_fd_sc_mcu7t5v0__antenna (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__antenna (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__antenna is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__antenn |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__antenn
+-------------------------------------------|-------------------------------------------
+I |I
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__antenna and gf180mcu_fd_sc_mcu7t5v0__antenna are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__buf_1 (0) disconnected node: I
+Cell gf180mcu_fd_sc_mcu7t5v0__buf_1 (0) disconnected node: Z
+Cell gf180mcu_fd_sc_mcu7t5v0__buf_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__buf_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__buf_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__buf_1 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__buf_1
+-------------------------------------------|-------------------------------------------
+I |I
+Z |Z
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__buf_1 and gf180mcu_fd_sc_mcu7t5v0__buf_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1 (0) disconnected node: B
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__aoi21_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__aoi21_ |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__aoi21_
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+B |B
+ZN |ZN
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__aoi21_1 and gf180mcu_fd_sc_mcu7t5v0__aoi21_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__dffq_1 (0) disconnected node: D
+Cell gf180mcu_fd_sc_mcu7t5v0__dffq_1 (0) disconnected node: CLK
+Cell gf180mcu_fd_sc_mcu7t5v0__dffq_1 (0) disconnected node: Q
+Cell gf180mcu_fd_sc_mcu7t5v0__dffq_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__dffq_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__dffq_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__dffq_1 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__dffq_1
+-------------------------------------------|-------------------------------------------
+D |D
+CLK |CLK
+Q |Q
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__dffq_1 and gf180mcu_fd_sc_mcu7t5v0__dffq_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1 (0) disconnected node: I
+Cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__clkinv_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__clkinv |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__clkinv
+-------------------------------------------|-------------------------------------------
+I |I
+ZN |ZN
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__clkinv_1 and gf180mcu_fd_sc_mcu7t5v0__clkinv_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 (0) disconnected node: I
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 (0) disconnected node: Z
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__clkbuf |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__clkbuf
+-------------------------------------------|-------------------------------------------
+I |I
+Z |Z
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 and gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_2 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_2 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_2 (0) disconnected node: A3
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_2 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_2 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_2 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__nand3_2 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__nand3_ |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__nand3_
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+A3 |A3
+ZN |ZN
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__nand3_2 and gf180mcu_fd_sc_mcu7t5v0__nand3_2 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__nand2_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__nand2_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__nand2_1 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__nand2_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__nand2_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__nand2_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__nand2_ |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__nand2_
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+ZN |ZN
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__nand2_1 and gf180mcu_fd_sc_mcu7t5v0__nand2_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1 (0) disconnected node: B1
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1 (0) disconnected node: B2
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__aoi22_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__aoi22_ |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__aoi22_
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+B1 |B1
+B2 |B2
+ZN |ZN
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__aoi22_1 and gf180mcu_fd_sc_mcu7t5v0__aoi22_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__and4_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__and4_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__and4_1 (0) disconnected node: A3
+Cell gf180mcu_fd_sc_mcu7t5v0__and4_1 (0) disconnected node: A4
+Cell gf180mcu_fd_sc_mcu7t5v0__and4_1 (0) disconnected node: Z
+Cell gf180mcu_fd_sc_mcu7t5v0__and4_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__and4_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__and4_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__and4_1 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__and4_1
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+A3 |A3
+A4 |A4
+Z |Z
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__and4_1 and gf180mcu_fd_sc_mcu7t5v0__and4_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__tiel (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__tiel (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__tiel (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__tiel is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__tiel |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__tiel
+-------------------------------------------|-------------------------------------------
+ZN |ZN
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__tiel and gf180mcu_fd_sc_mcu7t5v0__tiel are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__and3_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__and3_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__and3_1 (0) disconnected node: A3
+Cell gf180mcu_fd_sc_mcu7t5v0__and3_1 (0) disconnected node: Z
+Cell gf180mcu_fd_sc_mcu7t5v0__and3_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__and3_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__and3_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__and3_1 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__and3_1
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+A3 |A3
+Z |Z
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__and3_1 and gf180mcu_fd_sc_mcu7t5v0__and3_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_4 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_4 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_4 (0) disconnected node: A3
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_4 (0) disconnected node: A4
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_4 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_4 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_4 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__nor4_4 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__nor4_4 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__nor4_4
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+A3 |A3
+A4 |A4
+ZN |ZN
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__nor4_4 and gf180mcu_fd_sc_mcu7t5v0__nor4_4 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__and2_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__and2_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__and2_1 (0) disconnected node: Z
+Cell gf180mcu_fd_sc_mcu7t5v0__and2_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__and2_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__and2_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__and2_1 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__and2_1
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+Z |Z
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__and2_1 and gf180mcu_fd_sc_mcu7t5v0__and2_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__dlyb_1 (0) disconnected node: I
+Cell gf180mcu_fd_sc_mcu7t5v0__dlyb_1 (0) disconnected node: Z
+Cell gf180mcu_fd_sc_mcu7t5v0__dlyb_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__dlyb_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__dlyb_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__dlyb_1 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__dlyb_1
+-------------------------------------------|-------------------------------------------
+I |I
+Z |Z
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__dlyb_1 and gf180mcu_fd_sc_mcu7t5v0__dlyb_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__or2_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__or2_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__or2_1 (0) disconnected node: Z
+Cell gf180mcu_fd_sc_mcu7t5v0__or2_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__or2_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__or2_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__or2_1 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__or2_1
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+Z |Z
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__or2_1 and gf180mcu_fd_sc_mcu7t5v0__or2_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_1 (0) disconnected node: A3
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_1 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__nand3_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__nand3_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__nand3_ |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__nand3_
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+A3 |A3
+ZN |ZN
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__nand3_1 and gf180mcu_fd_sc_mcu7t5v0__nand3_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__nand4_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__nand4_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__nand4_1 (0) disconnected node: A3
+Cell gf180mcu_fd_sc_mcu7t5v0__nand4_1 (0) disconnected node: A4
+Cell gf180mcu_fd_sc_mcu7t5v0__nand4_1 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__nand4_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__nand4_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__nand4_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__nand4_ |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__nand4_
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+A3 |A3
+A4 |A4
+ZN |ZN
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__nand4_1 and gf180mcu_fd_sc_mcu7t5v0__nand4_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 (0) disconnected node: I
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 (0) disconnected node: Z
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__clkbuf |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__clkbuf
+-------------------------------------------|-------------------------------------------
+I |I
+Z |Z
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 and gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__nor2_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__nor2_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__nor2_1 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__nor2_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__nor2_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__nor2_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__nor2_1 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__nor2_1
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+ZN |ZN
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__nor2_1 and gf180mcu_fd_sc_mcu7t5v0__nor2_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__oai21_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__oai21_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__oai21_1 (0) disconnected node: B
+Cell gf180mcu_fd_sc_mcu7t5v0__oai21_1 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__oai21_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__oai21_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__oai21_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__oai21_ |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__oai21_
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+B |B
+ZN |ZN
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__oai21_1 and gf180mcu_fd_sc_mcu7t5v0__oai21_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__nor3_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__nor3_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__nor3_1 (0) disconnected node: A3
+Cell gf180mcu_fd_sc_mcu7t5v0__nor3_1 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__nor3_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__nor3_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__nor3_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__nor3_1 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__nor3_1
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+A3 |A3
+ZN |ZN
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__nor3_1 and gf180mcu_fd_sc_mcu7t5v0__nor3_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 (0) disconnected node: I
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 (0) disconnected node: Z
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__clkbuf |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__clkbuf
+-------------------------------------------|-------------------------------------------
+I |I
+Z |Z
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 and gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_2 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_2 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_2 (0) disconnected node: A3
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_2 (0) disconnected node: A4
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_2 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_2 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_2 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__nor4_2 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__nor4_2 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__nor4_2
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+A3 |A3
+A4 |A4
+ZN |ZN
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__nor4_2 and gf180mcu_fd_sc_mcu7t5v0__nor4_2 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__or3_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__or3_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__or3_1 (0) disconnected node: A3
+Cell gf180mcu_fd_sc_mcu7t5v0__or3_1 (0) disconnected node: Z
+Cell gf180mcu_fd_sc_mcu7t5v0__or3_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__or3_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__or3_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__or3_1 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__or3_1
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+A3 |A3
+Z |Z
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__or3_1 and gf180mcu_fd_sc_mcu7t5v0__or3_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__oai211_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__oai211_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__oai211_1 (0) disconnected node: B
+Cell gf180mcu_fd_sc_mcu7t5v0__oai211_1 (0) disconnected node: C
+Cell gf180mcu_fd_sc_mcu7t5v0__oai211_1 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__oai211_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__oai211_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__oai211_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__oai211 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__oai211
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+B |B
+C |C
+ZN |ZN
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__oai211_1 and gf180mcu_fd_sc_mcu7t5v0__oai211_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_1 (0) disconnected node: A1
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_1 (0) disconnected node: A2
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_1 (0) disconnected node: A3
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_1 (0) disconnected node: A4
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_1 (0) disconnected node: ZN
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_1 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__nor4_1 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__nor4_1 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__nor4_1 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__nor4_1
+-------------------------------------------|-------------------------------------------
+A1 |A1
+A2 |A2
+A3 |A3
+A4 |A4
+ZN |ZN
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__nor4_1 and gf180mcu_fd_sc_mcu7t5v0__nor4_1 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 (0) disconnected node: I
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 (0) disconnected node: Z
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__clkbuf |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__clkbuf
+-------------------------------------------|-------------------------------------------
+I |I
+Z |Z
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 and gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 are equivalent.
+
+Cell gf180mcu_fd_sc_mcu7t5v0__mux2_2 (0) disconnected node: I0
+Cell gf180mcu_fd_sc_mcu7t5v0__mux2_2 (0) disconnected node: I1
+Cell gf180mcu_fd_sc_mcu7t5v0__mux2_2 (0) disconnected node: S
+Cell gf180mcu_fd_sc_mcu7t5v0__mux2_2 (0) disconnected node: Z
+Cell gf180mcu_fd_sc_mcu7t5v0__mux2_2 (0) disconnected node: VDD
+Cell gf180mcu_fd_sc_mcu7t5v0__mux2_2 (0) disconnected node: VSS
+Warning: Equate pins: cell gf180mcu_fd_sc_mcu7t5v0__mux2_2 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: gf180mcu_fd_sc_mcu7t5v0__mux2_2 |Circuit 2: gf180mcu_fd_sc_mcu7t5v0__mux2_2
+-------------------------------------------|-------------------------------------------
+I0 |I0
+I1 |I1
+S |S
+Z |Z
+VDD |VDD
+VSS |VSS
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes gf180mcu_fd_sc_mcu7t5v0__mux2_2 and gf180mcu_fd_sc_mcu7t5v0__mux2_2 are equivalent.
+
+Cell plant_example (0) disconnected node: io_in[10]
+Cell plant_example (0) disconnected node: io_in[11]
+Cell plant_example (0) disconnected node: io_in[12]
+Cell plant_example (0) disconnected node: io_in[13]
+Cell plant_example (0) disconnected node: io_in[14]
+Cell plant_example (0) disconnected node: io_in[15]
+Cell plant_example (0) disconnected node: io_in[16]
+Cell plant_example (0) disconnected node: io_in[17]
+Cell plant_example (0) disconnected node: io_in[18]
+Cell plant_example (0) disconnected node: io_in[19]
+Cell plant_example (0) disconnected node: io_in[20]
+Cell plant_example (0) disconnected node: io_in[21]
+Cell plant_example (0) disconnected node: io_in[22]
+Cell plant_example (0) disconnected node: io_in[23]
+Cell plant_example (0) disconnected node: io_in[24]
+Cell plant_example (0) disconnected node: io_in[25]
+Cell plant_example (0) disconnected node: io_in[26]
+Cell plant_example (0) disconnected node: io_in[27]
+Cell plant_example (0) disconnected node: io_in[28]
+Cell plant_example (0) disconnected node: io_in[29]
+Cell plant_example (0) disconnected node: io_in[30]
+Cell plant_example (0) disconnected node: io_in[31]
+Cell plant_example (0) disconnected node: io_in[32]
+Cell plant_example (0) disconnected node: io_in[33]
+Cell plant_example (0) disconnected node: io_in[34]
+Cell plant_example (0) disconnected node: io_in[35]
+Cell plant_example (0) disconnected node: io_in[36]
+Cell plant_example (0) disconnected node: io_in[37]
+Cell plant_example (0) disconnected node: io_in[4]
+Cell plant_example (0) disconnected node: io_in[5]
+Cell plant_example (0) disconnected node: io_in[6]
+Cell plant_example (0) disconnected node: io_in[7]
+Cell plant_example (0) disconnected node: io_in[8]
+Cell plant_example (0) disconnected node: io_in[9]
+Cell plant_example (0) disconnected node: wbs_sel_i[3]
+Cell plant_example (1) disconnected node: io_in[37]
+Cell plant_example (1) disconnected node: io_in[36]
+Cell plant_example (1) disconnected node: io_in[35]
+Cell plant_example (1) disconnected node: io_in[34]
+Cell plant_example (1) disconnected node: io_in[33]
+Cell plant_example (1) disconnected node: io_in[32]
+Cell plant_example (1) disconnected node: io_in[31]
+Cell plant_example (1) disconnected node: io_in[30]
+Cell plant_example (1) disconnected node: io_in[29]
+Cell plant_example (1) disconnected node: io_in[28]
+Cell plant_example (1) disconnected node: io_in[27]
+Cell plant_example (1) disconnected node: io_in[26]
+Cell plant_example (1) disconnected node: io_in[25]
+Cell plant_example (1) disconnected node: io_in[24]
+Cell plant_example (1) disconnected node: io_in[23]
+Cell plant_example (1) disconnected node: io_in[22]
+Cell plant_example (1) disconnected node: io_in[21]
+Cell plant_example (1) disconnected node: io_in[20]
+Cell plant_example (1) disconnected node: io_in[19]
+Cell plant_example (1) disconnected node: io_in[18]
+Cell plant_example (1) disconnected node: io_in[17]
+Cell plant_example (1) disconnected node: io_in[16]
+Cell plant_example (1) disconnected node: io_in[15]
+Cell plant_example (1) disconnected node: io_in[14]
+Cell plant_example (1) disconnected node: io_in[13]
+Cell plant_example (1) disconnected node: io_in[12]
+Cell plant_example (1) disconnected node: io_in[11]
+Cell plant_example (1) disconnected node: io_in[10]
+Cell plant_example (1) disconnected node: io_in[9]
+Cell plant_example (1) disconnected node: io_in[8]
+Cell plant_example (1) disconnected node: io_in[7]
+Cell plant_example (1) disconnected node: io_in[6]
+Cell plant_example (1) disconnected node: io_in[5]
+Cell plant_example (1) disconnected node: io_in[4]
+Cell plant_example (1) disconnected node: wbs_sel_i[3]
+Class plant_example (0): Merged 6742 parallel devices.
+Class plant_example (1): Merged 6742 parallel devices.
+Cell plant_example (0) disconnected node: io_in[10]
+Cell plant_example (0) disconnected node: io_in[11]
+Cell plant_example (0) disconnected node: io_in[12]
+Cell plant_example (0) disconnected node: io_in[13]
+Cell plant_example (0) disconnected node: io_in[14]
+Cell plant_example (0) disconnected node: io_in[15]
+Cell plant_example (0) disconnected node: io_in[16]
+Cell plant_example (0) disconnected node: io_in[17]
+Cell plant_example (0) disconnected node: io_in[18]
+Cell plant_example (0) disconnected node: io_in[19]
+Cell plant_example (0) disconnected node: io_in[20]
+Cell plant_example (0) disconnected node: io_in[21]
+Cell plant_example (0) disconnected node: io_in[22]
+Cell plant_example (0) disconnected node: io_in[23]
+Cell plant_example (0) disconnected node: io_in[24]
+Cell plant_example (0) disconnected node: io_in[25]
+Cell plant_example (0) disconnected node: io_in[26]
+Cell plant_example (0) disconnected node: io_in[27]
+Cell plant_example (0) disconnected node: io_in[28]
+Cell plant_example (0) disconnected node: io_in[29]
+Cell plant_example (0) disconnected node: io_in[30]
+Cell plant_example (0) disconnected node: io_in[31]
+Cell plant_example (0) disconnected node: io_in[32]
+Cell plant_example (0) disconnected node: io_in[33]
+Cell plant_example (0) disconnected node: io_in[34]
+Cell plant_example (0) disconnected node: io_in[35]
+Cell plant_example (0) disconnected node: io_in[36]
+Cell plant_example (0) disconnected node: io_in[37]
+Cell plant_example (0) disconnected node: io_in[4]
+Cell plant_example (0) disconnected node: io_in[5]
+Cell plant_example (0) disconnected node: io_in[6]
+Cell plant_example (0) disconnected node: io_in[7]
+Cell plant_example (0) disconnected node: io_in[8]
+Cell plant_example (0) disconnected node: io_in[9]
+Cell plant_example (0) disconnected node: wbs_sel_i[3]
+Cell plant_example (1) disconnected node: io_in[37]
+Cell plant_example (1) disconnected node: io_in[36]
+Cell plant_example (1) disconnected node: io_in[35]
+Cell plant_example (1) disconnected node: io_in[34]
+Cell plant_example (1) disconnected node: io_in[33]
+Cell plant_example (1) disconnected node: io_in[32]
+Cell plant_example (1) disconnected node: io_in[31]
+Cell plant_example (1) disconnected node: io_in[30]
+Cell plant_example (1) disconnected node: io_in[29]
+Cell plant_example (1) disconnected node: io_in[28]
+Cell plant_example (1) disconnected node: io_in[27]
+Cell plant_example (1) disconnected node: io_in[26]
+Cell plant_example (1) disconnected node: io_in[25]
+Cell plant_example (1) disconnected node: io_in[24]
+Cell plant_example (1) disconnected node: io_in[23]
+Cell plant_example (1) disconnected node: io_in[22]
+Cell plant_example (1) disconnected node: io_in[21]
+Cell plant_example (1) disconnected node: io_in[20]
+Cell plant_example (1) disconnected node: io_in[19]
+Cell plant_example (1) disconnected node: io_in[18]
+Cell plant_example (1) disconnected node: io_in[17]
+Cell plant_example (1) disconnected node: io_in[16]
+Cell plant_example (1) disconnected node: io_in[15]
+Cell plant_example (1) disconnected node: io_in[14]
+Cell plant_example (1) disconnected node: io_in[13]
+Cell plant_example (1) disconnected node: io_in[12]
+Cell plant_example (1) disconnected node: io_in[11]
+Cell plant_example (1) disconnected node: io_in[10]
+Cell plant_example (1) disconnected node: io_in[9]
+Cell plant_example (1) disconnected node: io_in[8]
+Cell plant_example (1) disconnected node: io_in[7]
+Cell plant_example (1) disconnected node: io_in[6]
+Cell plant_example (1) disconnected node: io_in[5]
+Cell plant_example (1) disconnected node: io_in[4]
+Cell plant_example (1) disconnected node: wbs_sel_i[3]
+Subcircuit summary:
+Circuit 1: plant_example |Circuit 2: plant_example
+-------------------------------------------|-------------------------------------------
+gf180mcu_fd_sc_mcu7t5v0__fillcap_64 (3039- |gf180mcu_fd_sc_mcu7t5v0__fillcap_64 (3039-
+gf180mcu_fd_sc_mcu7t5v0__fillcap_4 (3204-> |gf180mcu_fd_sc_mcu7t5v0__fillcap_4 (3204->
+gf180mcu_fd_sc_mcu7t5v0__fillcap_16 (196-> |gf180mcu_fd_sc_mcu7t5v0__fillcap_16 (196->
+gf180mcu_fd_sc_mcu7t5v0__fillcap_8 (74->1) |gf180mcu_fd_sc_mcu7t5v0__fillcap_8 (74->1)
+gf180mcu_fd_sc_mcu7t5v0__fillcap_32 (194-> |gf180mcu_fd_sc_mcu7t5v0__fillcap_32 (194->
+gf180mcu_fd_sc_mcu7t5v0__antenna (79->39) |gf180mcu_fd_sc_mcu7t5v0__antenna (79->39)
+gf180mcu_fd_sc_mcu7t5v0__buf_1 (4) |gf180mcu_fd_sc_mcu7t5v0__buf_1 (4)
+gf180mcu_fd_sc_mcu7t5v0__aoi21_1 (6) |gf180mcu_fd_sc_mcu7t5v0__aoi21_1 (6)
+gf180mcu_fd_sc_mcu7t5v0__dffq_1 (6) |gf180mcu_fd_sc_mcu7t5v0__dffq_1 (6)
+gf180mcu_fd_sc_mcu7t5v0__clkinv_1 (8) |gf180mcu_fd_sc_mcu7t5v0__clkinv_1 (8)
+gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 (3) |gf180mcu_fd_sc_mcu7t5v0__clkbuf_3 (3)
+gf180mcu_fd_sc_mcu7t5v0__nand3_2 (1) |gf180mcu_fd_sc_mcu7t5v0__nand3_2 (1)
+gf180mcu_fd_sc_mcu7t5v0__nand2_1 (12) |gf180mcu_fd_sc_mcu7t5v0__nand2_1 (12)
+gf180mcu_fd_sc_mcu7t5v0__aoi22_1 (2) |gf180mcu_fd_sc_mcu7t5v0__aoi22_1 (2)
+gf180mcu_fd_sc_mcu7t5v0__and4_1 (4) |gf180mcu_fd_sc_mcu7t5v0__and4_1 (4)
+gf180mcu_fd_sc_mcu7t5v0__tiel (73) |gf180mcu_fd_sc_mcu7t5v0__tiel (73)
+gf180mcu_fd_sc_mcu7t5v0__and3_1 (2) |gf180mcu_fd_sc_mcu7t5v0__and3_1 (2)
+gf180mcu_fd_sc_mcu7t5v0__nor4_4 (1) |gf180mcu_fd_sc_mcu7t5v0__nor4_4 (1)
+gf180mcu_fd_sc_mcu7t5v0__and2_1 (3) |gf180mcu_fd_sc_mcu7t5v0__and2_1 (3)
+gf180mcu_fd_sc_mcu7t5v0__dlyb_1 (5) |gf180mcu_fd_sc_mcu7t5v0__dlyb_1 (5)
+gf180mcu_fd_sc_mcu7t5v0__or2_1 (2) |gf180mcu_fd_sc_mcu7t5v0__or2_1 (2)
+gf180mcu_fd_sc_mcu7t5v0__nand3_1 (2) |gf180mcu_fd_sc_mcu7t5v0__nand3_1 (2)
+gf180mcu_fd_sc_mcu7t5v0__nand4_1 (1) |gf180mcu_fd_sc_mcu7t5v0__nand4_1 (1)
+gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 (5) |gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 (5)
+gf180mcu_fd_sc_mcu7t5v0__nor2_1 (6) |gf180mcu_fd_sc_mcu7t5v0__nor2_1 (6)
+gf180mcu_fd_sc_mcu7t5v0__oai21_1 (5) |gf180mcu_fd_sc_mcu7t5v0__oai21_1 (5)
+gf180mcu_fd_sc_mcu7t5v0__nor3_1 (1) |gf180mcu_fd_sc_mcu7t5v0__nor3_1 (1)
+gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 (1) |gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 (1)
+gf180mcu_fd_sc_mcu7t5v0__nor4_2 (1) |gf180mcu_fd_sc_mcu7t5v0__nor4_2 (1)
+gf180mcu_fd_sc_mcu7t5v0__or3_1 (1) |gf180mcu_fd_sc_mcu7t5v0__or3_1 (1)
+gf180mcu_fd_sc_mcu7t5v0__oai211_1 (1) |gf180mcu_fd_sc_mcu7t5v0__oai211_1 (1)
+gf180mcu_fd_sc_mcu7t5v0__nor4_1 (1) |gf180mcu_fd_sc_mcu7t5v0__nor4_1 (1)
+gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 (3) |gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 (3)
+gf180mcu_fd_sc_mcu7t5v0__mux2_2 (1) |gf180mcu_fd_sc_mcu7t5v0__mux2_2 (1)
+Number of devices: 205 |Number of devices: 205
+Number of nets: 173 |Number of nets: 173
+---------------------------------------------------------------------------------------
+Resolving symmetries by property value.
+Resolving symmetries by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: plant_example |Circuit 2: plant_example
+-------------------------------------------|-------------------------------------------
+io_oeb[1] |io_oeb[1]
+io_out[0] |io_out[0]
+io_oeb[0] |io_oeb[0]
+io_oeb[8] |io_oeb[8]
+io_oeb[7] |io_oeb[7]
+io_oeb[18] |io_oeb[18]
+io_oeb[6] |io_oeb[6]
+io_oeb[17] |io_oeb[17]
+io_oeb[28] |io_oeb[28]
+io_out[1] |io_out[1]
+io_oeb[5] |io_oeb[5]
+io_oeb[16] |io_oeb[16]
+io_oeb[27] |io_oeb[27]
+io_out[11] |io_out[11]
+io_oeb[4] |io_oeb[4]
+io_oeb[15] |io_oeb[15]
+io_oeb[26] |io_oeb[26]
+io_oeb[37] |io_oeb[37]
+io_out[10] |io_out[10]
+io_out[21] |io_out[21]
+io_oeb[14] |io_oeb[14]
+io_oeb[25] |io_oeb[25]
+io_oeb[36] |io_oeb[36]
+io_oeb[3] |io_oeb[3]
+io_out[20] |io_out[20]
+io_out[31] |io_out[31]
+io_out[9] |io_out[9]
+io_oeb[13] |io_oeb[13]
+io_oeb[24] |io_oeb[24]
+io_oeb[35] |io_oeb[35]
+io_oeb[2] |io_oeb[2]
+io_out[19] |io_out[19]
+io_out[30] |io_out[30]
+io_out[8] |io_out[8]
+io_oeb[23] |io_oeb[23]
+io_oeb[34] |io_oeb[34]
+io_oeb[12] |io_oeb[12]
+io_out[29] |io_out[29]
+io_out[7] |io_out[7]
+io_out[18] |io_out[18]
+io_oeb[22] |io_oeb[22]
+io_oeb[33] |io_oeb[33]
+io_oeb[11] |io_oeb[11]
+io_out[28] |io_out[28]
+io_out[6] |io_out[6]
+io_out[17] |io_out[17]
+io_oeb[32] |io_oeb[32]
+io_oeb[10] |io_oeb[10]
+io_oeb[21] |io_oeb[21]
+io_out[5] |io_out[5]
+io_out[16] |io_out[16]
+io_out[27] |io_out[27]
+io_oeb[9] |io_oeb[9]
+io_oeb[20] |io_oeb[20]
+io_oeb[31] |io_oeb[31]
+io_out[37] |io_out[37]
+io_out[4] |io_out[4]
+io_out[15] |io_out[15]
+io_out[26] |io_out[26]
+io_oeb[19] |io_oeb[19]
+io_oeb[30] |io_oeb[30]
+io_out[14] |io_out[14]
+io_out[25] |io_out[25]
+io_out[36] |io_out[36]
+io_out[3] |io_out[3]
+io_oeb[29] |io_oeb[29]
+io_out[13] |io_out[13]
+io_out[24] |io_out[24]
+io_out[35] |io_out[35]
+io_out[2] |io_out[2]
+io_out[23] |io_out[23]
+io_out[34] |io_out[34]
+io_out[12] |io_out[12]
+io_out[22] |io_out[22]
+io_out[33] |io_out[33]
+io_out[32] |io_out[32]
+wb_clk_i |wb_clk_i
+io_in[0] |io_in[0]
+wb_rst_i |wb_rst_i
+io_in[3] |io_in[3]
+wbs_sel_i[0] |wbs_sel_i[0]
+io_in[1] |io_in[1]
+io_in[2] |io_in[2]
+wbs_we_i |wbs_we_i
+wbs_sel_i[1] |wbs_sel_i[1]
+wbs_sel_i[2] |wbs_sel_i[2]
+vdd |vdd
+vss |vss
+io_in[10] |io_in[10]
+io_in[11] |io_in[11]
+io_in[12] |io_in[12]
+io_in[13] |io_in[13]
+io_in[14] |io_in[14]
+io_in[15] |io_in[15]
+io_in[16] |io_in[16]
+io_in[17] |io_in[17]
+io_in[18] |io_in[18]
+io_in[19] |io_in[19]
+io_in[20] |io_in[20]
+io_in[21] |io_in[21]
+io_in[22] |io_in[22]
+io_in[23] |io_in[23]
+io_in[24] |io_in[24]
+io_in[25] |io_in[25]
+io_in[26] |io_in[26]
+io_in[27] |io_in[27]
+io_in[28] |io_in[28]
+io_in[29] |io_in[29]
+io_in[30] |io_in[30]
+io_in[31] |io_in[31]
+io_in[32] |io_in[32]
+io_in[33] |io_in[33]
+io_in[34] |io_in[34]
+io_in[35] |io_in[35]
+io_in[36] |io_in[36]
+io_in[37] |io_in[37]
+io_in[4] |io_in[4]
+io_in[5] |io_in[5]
+io_in[6] |io_in[6]
+io_in[7] |io_in[7]
+io_in[8] |io_in[8]
+io_in[9] |io_in[9]
+wbs_sel_i[3] |wbs_sel_i[3]
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes plant_example and plant_example are equivalent.
+
+Final result: Circuits match uniquely.
+.
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/signoff/28-drc.log b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/28-drc.log
new file mode 100644
index 0000000..5a21c3c
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/28-drc.log
@@ -0,0 +1,68 @@
+
+Magic 8.3 revision 331 - Compiled on Sat Oct 22 18:40:56 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology gf180mcuC ...
+10 Magic internal units = 1 Lambda
+Input style import: scaleFactor=10, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+ obsactive mvobsactive filldiff fillpoly m1hole obsm1 fillm1 obsv1 m2hole obsm2 fillm2 obsv2 m3hole obsm3 fillm3 m4hole obsm4 fillm4 m5hole obsm5 fillm5 glass fillblock lvstext obscomment
+Scaled tech values by 10 / 1 to match internal grid scaling
+Loading gf180mcuC Device Generator Menu ...
+Using technology "gf180mcuC", version 1.0.359-0-g35c7265
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: plant_example
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_32".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_64".
+Reading "gf180mcu_fd_sc_mcu7t5v0__endcap".
+Reading "gf180mcu_fd_sc_mcu7t5v0__filltie".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_16".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__dffq_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16".
+Reading "gf180mcu_fd_sc_mcu7t5v0__antenna".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fill_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__fillcap_8".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__buf_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__dlyb_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor2_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand2_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkinv_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand3_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__or2_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__and3_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor4_4".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand3_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi21_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor4_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__aoi22_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai21_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__and4_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__and2_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__mux2_2".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nand4_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor4_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__oai211_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__or3_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__nor3_1".
+Reading "gf180mcu_fd_sc_mcu7t5v0__clkbuf_3".
+Reading "gf180mcu_fd_sc_mcu7t5v0__tiel".
+Reading "plant_example".
+ 5000 uses
+ 10000 uses
+[INFO]: Loading plant_example
+
+DRC style is now "drc(full)"
+Loading DRC CIF style.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff/drc.rpt)
+[INFO]: Saving mag view with DRC errors (/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/signoff/plant_example.drc.mag)
+[INFO]: Saved
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/signoff/29-antenna.log b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/29-antenna.log
new file mode 100644
index 0000000..1e838d2
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/signoff/29-antenna.log
@@ -0,0 +1,5 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO ANT-0002] Found 0 net violations.
+[INFO ANT-0001] Found 0 pin violations.
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/synthesis/1-synthesis.log b/openlane/user_proj_example/runs/user_proj_example/logs/synthesis/1-synthesis.log
new file mode 100644
index 0000000..b3c07d6
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/synthesis/1-synthesis.log
@@ -0,0 +1,968 @@
+
+ /----------------------------------------------------------------------------\
+ | |
+ | yosys -- Yosys Open SYnthesis Suite |
+ | |
+ | Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> |
+ | |
+ | Permission to use, copy, modify, and/or distribute this software for any |
+ | purpose with or without fee is hereby granted, provided that the above |
+ | copyright notice and this permission notice appear in all copies. |
+ | |
+ | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
+ | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
+ | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
+ | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
+ | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
+ | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
+ | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
+ | |
+ \----------------------------------------------------------------------------/
+
+ Yosys 0.22 (git sha1 f109fa3d4c5, gcc 8.3.1 -fPIC -Os)
+
+[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
+
+1. Executing Verilog-2005 frontend: /home/xb4syf/ASIC/gf180-demo/caravel/verilog/rtl/defines.v
+Parsing SystemVerilog input from `/home/xb4syf/ASIC/gf180-demo/caravel/verilog/rtl/defines.v' to AST representation.
+Successfully finished Verilog frontend.
+
+2. Executing Verilog-2005 frontend: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/../../verilog/rtl/plant_example.v
+Parsing SystemVerilog input from `/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/../../verilog/rtl/plant_example.v' to AST representation.
+Generating RTLIL representation for module `\plant_example'.
+Generating RTLIL representation for module `\fsm_plant_opt'.
+Successfully finished Verilog frontend.
+
+3. Generating Graphviz representation of design.
+Writing dot description to `/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/hierarchy.dot'.
+Dumping module plant_example to page 1.
+
+4. Executing HIERARCHY pass (managing design hierarchy).
+
+4.1. Analyzing design hierarchy..
+Top module: \plant_example
+Used module: \fsm_plant_opt
+
+4.2. Analyzing design hierarchy..
+Top module: \plant_example
+Used module: \fsm_plant_opt
+Removed 0 unused modules.
+Warning: Resizing cell port plant_example.fsm_plant_opt.ac from 38 bits to 2 bits.
+Warning: Resizing cell port plant_example.fsm_plant_opt.pump from 38 bits to 1 bits.
+Warning: Resizing cell port plant_example.fsm_plant_opt.water from 38 bits to 4 bits.
+Warning: Resizing cell port plant_example.fsm_plant_opt.temperature from 4 bits to 3 bits.
+WARNING: TRISTATE_BUFFER_MAP is defined but could not be found: /localtmp/asic/gf180/pdk//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tribuff_map.v
+
+5. Executing SYNTH pass.
+
+5.1. Executing HIERARCHY pass (managing design hierarchy).
+
+5.1.1. Analyzing design hierarchy..
+Top module: \plant_example
+Used module: \fsm_plant_opt
+
+5.1.2. Analyzing design hierarchy..
+Top module: \plant_example
+Used module: \fsm_plant_opt
+Removed 0 unused modules.
+
+5.2. Executing PROC pass (convert processes to netlists).
+
+5.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Cleaned up 0 empty switches.
+
+5.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
+Removed a total of 0 dead cases.
+
+5.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
+Removed 0 redundant assignments.
+Promoted 6 assignments to connections.
+
+5.2.4. Executing PROC_INIT pass (extract init attributes).
+
+5.2.5. Executing PROC_ARST pass (detect async resets in processes).
+
+5.2.6. Executing PROC_ROM pass (convert switches to ROMs).
+Converted 0 switches.
+
+5.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
+Creating decoders for process `\fsm_plant_opt.$proc$/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/../../verilog/rtl/plant_example.v:917$373'.
+
+5.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
+
+5.2.9. Executing PROC_DFF pass (convert process syncs to FFs).
+Creating register for signal `\fsm_plant_opt.\state_temperature_synth_0' using process `\fsm_plant_opt.$proc$/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/../../verilog/rtl/plant_example.v:917$373'.
+ created $dff cell `$procdff$374' with positive edge clock.
+Creating register for signal `\fsm_plant_opt.\state_temperature_synth_1' using process `\fsm_plant_opt.$proc$/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/../../verilog/rtl/plant_example.v:917$373'.
+ created $dff cell `$procdff$375' with positive edge clock.
+Creating register for signal `\fsm_plant_opt.\state_temperature_synth_2' using process `\fsm_plant_opt.$proc$/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/../../verilog/rtl/plant_example.v:917$373'.
+ created $dff cell `$procdff$376' with positive edge clock.
+Creating register for signal `\fsm_plant_opt.\state_water_synth_1' using process `\fsm_plant_opt.$proc$/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/../../verilog/rtl/plant_example.v:917$373'.
+ created $dff cell `$procdff$377' with positive edge clock.
+Creating register for signal `\fsm_plant_opt.\state_water_synth_2' using process `\fsm_plant_opt.$proc$/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/../../verilog/rtl/plant_example.v:917$373'.
+ created $dff cell `$procdff$378' with positive edge clock.
+Creating register for signal `\fsm_plant_opt.\state_water_synth_0' using process `\fsm_plant_opt.$proc$/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/../../verilog/rtl/plant_example.v:917$373'.
+ created $dff cell `$procdff$379' with positive edge clock.
+
+5.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
+
+5.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Removing empty process `fsm_plant_opt.$proc$/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/../../verilog/rtl/plant_example.v:917$373'.
+Cleaned up 0 empty switches.
+
+5.2.12. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fsm_plant_opt.
+<suppressed ~16 debug messages>
+Optimizing module plant_example.
+
+5.3. Executing FLATTEN pass (flatten design).
+Deleting now unused module fsm_plant_opt.
+<suppressed ~1 debug messages>
+
+5.4. Executing OPT_EXPR pass (perform const folding).
+Optimizing module plant_example.
+
+5.5. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \plant_example..
+Removed 3 unused cells and 381 unused wires.
+<suppressed ~7 debug messages>
+
+5.6. Executing CHECK pass (checking for obvious problems).
+Checking module plant_example...
+Found and reported 0 problems.
+
+5.7. Executing OPT pass (performing simple optimizations).
+
+5.7.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module plant_example.
+
+5.7.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\plant_example'.
+Removed a total of 0 cells.
+
+5.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \plant_example..
+ Creating internal representation of mux trees.
+ No muxes found in this module.
+Removed 0 multiplexer ports.
+
+5.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \plant_example.
+Performed a total of 0 changes.
+
+5.7.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\plant_example'.
+Removed a total of 0 cells.
+
+5.7.6. Executing OPT_DFF pass (perform DFF optimizations).
+
+5.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \plant_example..
+
+5.7.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module plant_example.
+
+5.7.9. Finished OPT passes. (There is nothing left to do.)
+
+5.8. Executing FSM pass (extract and optimize FSM).
+
+5.8.1. Executing FSM_DETECT pass (finding FSMs in design).
+
+5.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).
+
+5.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).
+
+5.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \plant_example..
+
+5.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).
+
+5.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
+
+5.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
+
+5.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
+
+5.9. Executing OPT pass (performing simple optimizations).
+
+5.9.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module plant_example.
+
+5.9.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\plant_example'.
+Removed a total of 0 cells.
+
+5.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \plant_example..
+ Creating internal representation of mux trees.
+ No muxes found in this module.
+Removed 0 multiplexer ports.
+
+5.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \plant_example.
+Performed a total of 0 changes.
+
+5.9.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\plant_example'.
+Removed a total of 0 cells.
+
+5.9.6. Executing OPT_DFF pass (perform DFF optimizations).
+
+5.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \plant_example..
+
+5.9.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module plant_example.
+
+5.9.9. Finished OPT passes. (There is nothing left to do.)
+
+5.10. Executing WREDUCE pass (reducing word size of cells).
+
+5.11. Executing PEEPOPT pass (run peephole optimizers).
+
+5.12. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \plant_example..
+
+5.13. Executing ALUMACC pass (create $alu and $macc cells).
+Extracting $alu and $macc cells in module plant_example:
+ created 0 $alu and 0 $macc cells.
+
+5.14. Executing SHARE pass (SAT-based resource sharing).
+
+5.15. Executing OPT pass (performing simple optimizations).
+
+5.15.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module plant_example.
+
+5.15.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\plant_example'.
+Removed a total of 0 cells.
+
+5.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \plant_example..
+ Creating internal representation of mux trees.
+ No muxes found in this module.
+Removed 0 multiplexer ports.
+
+5.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \plant_example.
+Performed a total of 0 changes.
+
+5.15.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\plant_example'.
+Removed a total of 0 cells.
+
+5.15.6. Executing OPT_DFF pass (perform DFF optimizations).
+
+5.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \plant_example..
+
+5.15.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module plant_example.
+
+5.15.9. Finished OPT passes. (There is nothing left to do.)
+
+5.16. Executing MEMORY pass.
+
+5.16.1. Executing OPT_MEM pass (optimize memories).
+Performed a total of 0 transformations.
+
+5.16.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
+Performed a total of 0 transformations.
+
+5.16.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
+
+5.16.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
+
+5.16.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
+
+5.16.6. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \plant_example..
+
+5.16.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
+
+5.16.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
+Performed a total of 0 transformations.
+
+5.16.9. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \plant_example..
+
+5.16.10. Executing MEMORY_COLLECT pass (generating $mem cells).
+
+5.17. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \plant_example..
+
+5.18. Executing OPT pass (performing simple optimizations).
+
+5.18.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module plant_example.
+
+5.18.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\plant_example'.
+Removed a total of 0 cells.
+
+5.18.3. Executing OPT_DFF pass (perform DFF optimizations).
+
+5.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \plant_example..
+
+5.18.5. Finished fast OPT passes.
+
+5.19. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
+
+5.20. Executing OPT pass (performing simple optimizations).
+
+5.20.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module plant_example.
+
+5.20.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\plant_example'.
+Removed a total of 0 cells.
+
+5.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \plant_example..
+ Creating internal representation of mux trees.
+ No muxes found in this module.
+Removed 0 multiplexer ports.
+
+5.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \plant_example.
+Performed a total of 0 changes.
+
+5.20.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\plant_example'.
+Removed a total of 0 cells.
+
+5.20.6. Executing OPT_SHARE pass.
+
+5.20.7. Executing OPT_DFF pass (perform DFF optimizations).
+
+5.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \plant_example..
+
+5.20.9. Executing OPT_EXPR pass (perform const folding).
+Optimizing module plant_example.
+
+5.20.10. Finished OPT passes. (There is nothing left to do.)
+
+5.21. Executing TECHMAP pass (map to technology primitives).
+
+5.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
+Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
+Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
+Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
+Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
+Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
+Generating RTLIL representation for module `\_90_simplemap_various'.
+Generating RTLIL representation for module `\_90_simplemap_registers'.
+Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
+Generating RTLIL representation for module `\_90_shift_shiftx'.
+Generating RTLIL representation for module `\_90_fa'.
+Generating RTLIL representation for module `\_90_lcu'.
+Generating RTLIL representation for module `\_90_alu'.
+Generating RTLIL representation for module `\_90_macc'.
+Generating RTLIL representation for module `\_90_alumacc'.
+Generating RTLIL representation for module `\$__div_mod_u'.
+Generating RTLIL representation for module `\$__div_mod_trunc'.
+Generating RTLIL representation for module `\_90_div'.
+Generating RTLIL representation for module `\_90_mod'.
+Generating RTLIL representation for module `\$__div_mod_floor'.
+Generating RTLIL representation for module `\_90_divfloor'.
+Generating RTLIL representation for module `\_90_modfloor'.
+Generating RTLIL representation for module `\_90_pow'.
+Generating RTLIL representation for module `\_90_pmux'.
+Generating RTLIL representation for module `\_90_demux'.
+Generating RTLIL representation for module `\_90_lut'.
+Successfully finished Verilog frontend.
+
+5.21.2. Continuing TECHMAP pass.
+Using extmapper simplemap for cells of type $or.
+Using extmapper simplemap for cells of type $and.
+Using extmapper simplemap for cells of type $not.
+Using extmapper simplemap for cells of type $dff.
+Using extmapper simplemap for cells of type $xor.
+No more expansions possible.
+<suppressed ~430 debug messages>
+
+5.22. Executing OPT pass (performing simple optimizations).
+
+5.22.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module plant_example.
+
+5.22.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\plant_example'.
+Removed a total of 0 cells.
+
+5.22.3. Executing OPT_DFF pass (perform DFF optimizations).
+
+5.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \plant_example..
+
+5.22.5. Finished fast OPT passes.
+
+5.23. Executing ABC pass (technology mapping using ABC).
+
+5.23.1. Extracting gate netlist of module `\plant_example' to `<abc-temp-dir>/input.blif'..
+Extracted 353 gates and 368 wires to a netlist network with 15 inputs and 9 outputs.
+
+5.23.1.1. Executing ABC.
+Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
+ABC: ABC command line: "source <abc-temp-dir>/abc.script".
+ABC:
+ABC: + read_blif <abc-temp-dir>/input.blif
+ABC: + read_library <abc-temp-dir>/stdcells.genlib
+ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
+ABC: + strash
+ABC: + dretime
+ABC: + map
+ABC: + write_blif <abc-temp-dir>/output.blif
+
+5.23.1.2. Re-integrating ABC results.
+ABC RESULTS: NOT cells: 7
+ABC RESULTS: AND cells: 6
+ABC RESULTS: NAND cells: 6
+ABC RESULTS: NOR cells: 19
+ABC RESULTS: MUX cells: 21
+ABC RESULTS: OR cells: 76
+ABC RESULTS: ORNOT cells: 19
+ABC RESULTS: ANDNOT cells: 56
+ABC RESULTS: XNOR cells: 1
+ABC RESULTS: internal signals: 344
+ABC RESULTS: input signals: 15
+ABC RESULTS: output signals: 9
+Removing temp directory.
+
+5.24. Executing OPT pass (performing simple optimizations).
+
+5.24.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module plant_example.
+<suppressed ~2 debug messages>
+
+5.24.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\plant_example'.
+Removed a total of 0 cells.
+
+5.24.3. Executing OPT_DFF pass (perform DFF optimizations).
+
+5.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \plant_example..
+Removed 1 unused cells and 379 unused wires.
+<suppressed ~356 debug messages>
+
+5.24.5. Finished fast OPT passes.
+
+5.25. Executing HIERARCHY pass (managing design hierarchy).
+
+5.25.1. Analyzing design hierarchy..
+Top module: \plant_example
+
+5.25.2. Analyzing design hierarchy..
+Top module: \plant_example
+Removed 0 unused modules.
+
+5.26. Printing statistics.
+
+=== plant_example ===
+
+ Number of wires: 249
+ Number of wire bits: 401
+ Number of public wires: 48
+ Number of public wire bits: 200
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 216
+ $_ANDNOT_ 56
+ $_AND_ 6
+ $_DFF_P_ 6
+ $_MUX_ 21
+ $_NAND_ 6
+ $_NOR_ 19
+ $_NOT_ 6
+ $_ORNOT_ 19
+ $_OR_ 76
+ $_XNOR_ 1
+
+5.27. Executing CHECK pass (checking for obvious problems).
+Checking module plant_example...
+Found and reported 0 problems.
+
+6. Generating Graphviz representation of design.
+Writing dot description to `/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/post_techmap.dot'.
+Dumping module plant_example to page 1.
+Warning: WIDTHLABEL \wbs_sel_i [0] 1
+Warning: WIDTHLABEL \wbs_sel_i [1] 1
+Warning: WIDTHLABEL \wbs_sel_i [2] 1
+Warning: WIDTHLABEL \io_in [3] 1
+Warning: WIDTHLABEL \io_in [2] 1
+Warning: WIDTHLABEL \io_in [1] 1
+Warning: WIDTHLABEL \wbs_sel_i [2] 1
+Warning: WIDTHLABEL \wbs_sel_i [1] 1
+Warning: WIDTHLABEL \wbs_sel_i [2] 1
+Warning: WIDTHLABEL \wbs_sel_i [1] 1
+Warning: WIDTHLABEL \io_in [1] 1
+Warning: WIDTHLABEL \io_in [0] 1
+Warning: WIDTHLABEL \io_in [2] 1
+
+7. Executing SHARE pass (SAT-based resource sharing).
+
+8. Executing OPT pass (performing simple optimizations).
+
+8.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module plant_example.
+
+8.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\plant_example'.
+Removed a total of 0 cells.
+
+8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \plant_example..
+ Creating internal representation of mux trees.
+ No muxes found in this module.
+Removed 0 multiplexer ports.
+
+8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \plant_example.
+Performed a total of 0 changes.
+
+8.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\plant_example'.
+Removed a total of 0 cells.
+
+8.6. Executing OPT_DFF pass (perform DFF optimizations).
+
+8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \plant_example..
+
+8.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module plant_example.
+
+8.9. Finished OPT passes. (There is nothing left to do.)
+
+9. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \plant_example..
+Removed 0 unused cells and 26 unused wires.
+<suppressed ~26 debug messages>
+
+10. Printing statistics.
+
+=== plant_example ===
+
+ Number of wires: 223
+ Number of wire bits: 337
+ Number of public wires: 22
+ Number of public wire bits: 136
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 216
+ $_ANDNOT_ 56
+ $_AND_ 6
+ $_DFF_P_ 6
+ $_MUX_ 21
+ $_NAND_ 6
+ $_NOR_ 19
+ $_NOT_ 6
+ $_ORNOT_ 19
+ $_OR_ 76
+ $_XNOR_ 1
+
+11. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
+ cell gf180mcu_fd_sc_mcu7t5v0__dffnq_1 (noninv, pins=3, area=65.86) is a direct match for cell type $_DFF_N_.
+ cell gf180mcu_fd_sc_mcu7t5v0__dffq_1 (noninv, pins=3, area=63.66) is a direct match for cell type $_DFF_P_.
+ cell gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1 (noninv, pins=4, area=74.64) is a direct match for cell type $_DFF_NN0_.
+ cell gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1 (noninv, pins=4, area=79.03) is a direct match for cell type $_DFF_NN1_.
+ cell gf180mcu_fd_sc_mcu7t5v0__dffrnq_1 (noninv, pins=4, area=74.64) is a direct match for cell type $_DFF_PN0_.
+ cell gf180mcu_fd_sc_mcu7t5v0__dffsnq_1 (noninv, pins=4, area=79.03) is a direct match for cell type $_DFF_PN1_.
+ cell gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1 (noninv, pins=5, area=94.39) is a direct match for cell type $_DFFSR_NNN_.
+ cell gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1 (noninv, pins=5, area=85.61) is a direct match for cell type $_DFFSR_PNN_.
+ final dff cell mappings:
+ \gf180mcu_fd_sc_mcu7t5v0__dffnq_1 _DFF_N_ (.CLKN( C), .D( D), .Q( Q));
+ \gf180mcu_fd_sc_mcu7t5v0__dffq_1 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
+ \gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1 _DFF_NN0_ (.CLKN( C), .D( D), .Q( Q), .RN( R));
+ \gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1 _DFF_NN1_ (.CLKN( C), .D( D), .Q( Q), .SETN( R));
+ unmapped dff cell: $_DFF_NP0_
+ unmapped dff cell: $_DFF_NP1_
+ \gf180mcu_fd_sc_mcu7t5v0__dffrnq_1 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RN( R));
+ \gf180mcu_fd_sc_mcu7t5v0__dffsnq_1 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SETN( R));
+ unmapped dff cell: $_DFF_PP0_
+ unmapped dff cell: $_DFF_PP1_
+ \gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1 _DFFSR_NNN_ (.CLKN( C), .D( D), .Q( Q), .RN( R), .SETN( S));
+ unmapped dff cell: $_DFFSR_NNP_
+ unmapped dff cell: $_DFFSR_NPN_
+ unmapped dff cell: $_DFFSR_NPP_
+ \gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1 _DFFSR_PNN_ (.CLK( C), .D( D), .Q( Q), .RN( R), .SETN( S));
+ unmapped dff cell: $_DFFSR_PNP_
+ unmapped dff cell: $_DFFSR_PPN_
+ unmapped dff cell: $_DFFSR_PPP_
+
+11.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
+Mapping DFF cells in module `\plant_example':
+ mapped 6 $_DFF_P_ cells to \gf180mcu_fd_sc_mcu7t5v0__dffq_1 cells.
+
+12. Printing statistics.
+
+=== plant_example ===
+
+ Number of wires: 223
+ Number of wire bits: 337
+ Number of public wires: 22
+ Number of public wire bits: 136
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 216
+ $_ANDNOT_ 56
+ $_AND_ 6
+ $_MUX_ 21
+ $_NAND_ 6
+ $_NOR_ 19
+ $_NOT_ 6
+ $_ORNOT_ 19
+ $_OR_ 76
+ $_XNOR_ 1
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 6
+
+[INFO]: USING STRATEGY AREA 0
+
+13. Executing ABC pass (technology mapping using ABC).
+
+13.1. Extracting gate netlist of module `\plant_example' to `/tmp/yosys-abc-9IHGfo/input.blif'..
+Extracted 210 gates and 225 wires to a netlist network with 15 inputs and 9 outputs.
+
+13.1.1. Executing ABC.
+Running ABC command: "/build/bin/yosys-abc" -s -f /tmp/yosys-abc-9IHGfo/abc.script 2>&1
+ABC: ABC command line: "source /tmp/yosys-abc-9IHGfo/abc.script".
+ABC:
+ABC: + read_blif /tmp/yosys-abc-9IHGfo/input.blif
+ABC: + read_lib -w /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/trimmed.lib
+ABC: Parsing finished successfully. Parsing time = 0.16 sec
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__antenna" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_1".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_2".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_3".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_4".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_8".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_12".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_16".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrnq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnsnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffnsnq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrnq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrsnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffrsnq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffsnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffsnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__dffsnq_4".
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__endcap" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_1" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_2" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_4" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_8" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_16" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_32" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fill_64" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fillcap_4" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fillcap_8" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fillcap_16" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fillcap_32" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__fillcap_64" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__filltie" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__hold".
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtn_1" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtn_2" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtn_4" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtp_1" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtp_2" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__icgtp_4" without logic function.
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_1".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_2".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_3".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_4".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_8".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_12".
+ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__invz_16".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrnq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrsnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrsnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latrsnq_4".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latsnq_1".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latsnq_2".
+ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latsnq_4".
+ABC: Library "gf180mcuC_merged" from "/home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/trimmed.lib" has 143 cells (72 skipped: 36 seq; 15 tri-state; 21 no func; 0 dont_use). Time = 0.30 sec
+ABC: Memory = 23.60 MB. Time = 0.30 sec
+ABC: Warning: Detected 6 multi-output gates (for example, "gf180mcu_fd_sc_mcu7t5v0__addf_1").
+ABC: + read_constr -v /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/synthesis.sdc
+ABC: Setting driving cell to be "gf180mcu_fd_sc_mcu7t5v0__inv_1".
+ABC: Setting output load to be 72.910004.
+ABC: + read_constr /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/synthesis/synthesis.sdc
+ABC: + fx
+ABC: + mfs
+ABC: + strash
+ABC: + refactor
+ABC: + balance
+ABC: + rewrite
+ABC: + refactor
+ABC: + balance
+ABC: + rewrite
+ABC: + rewrite -z
+ABC: + balance
+ABC: + refactor -z
+ABC: + rewrite -z
+ABC: + balance
+ABC: + retime -D -D 30000.0 -M 5
+ABC: + scleanup
+ABC: Error: The network is combinational.
+ABC: + fraig_store
+ABC: + balance
+ABC: + fraig_store
+ABC: + balance
+ABC: + rewrite
+ABC: + refactor
+ABC: + balance
+ABC: + rewrite
+ABC: + rewrite -z
+ABC: + balance
+ABC: + refactor -z
+ABC: + rewrite -z
+ABC: + balance
+ABC: + fraig_store
+ABC: + balance
+ABC: + rewrite
+ABC: + refactor
+ABC: + balance
+ABC: + rewrite
+ABC: + rewrite -z
+ABC: + balance
+ABC: + refactor -z
+ABC: + rewrite -z
+ABC: + balance
+ABC: + fraig_store
+ABC: + balance
+ABC: + rewrite
+ABC: + refactor
+ABC: + balance
+ABC: + rewrite
+ABC: + rewrite -z
+ABC: + balance
+ABC: + refactor -z
+ABC: + rewrite -z
+ABC: + balance
+ABC: + fraig_store
+ABC: + fraig_restore
+ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000
+ABC: + retime -D -D 30000.0
+ABC: + &get -n
+ABC: + &st
+ABC: + &dch
+ABC: + &nf
+ABC: + &put
+ABC: + buffer -N 4 -S 3000.0
+ABC: + upsize -D 30000.0
+ABC: Current delay (3896.03 ps) does not exceed the target delay (30000.00 ps). Upsizing is not performed.
+ABC: + dnsize -D 30000.0
+ABC: + stime -p
+ABC: WireLoad = "none" Gates = 67 ( 20.9 %) Cap = 16.1 ff ( 4.8 %) Area = 1047.11 ( 86.6 %) Delay = 3992.42 ps ( 13.4 %)
+ABC: Path 0 -- 1 : 0 4 pi A = 0.00 Df = 160.6 -60.2 ps S = 327.7 ps Cin = 0.0 ff Cout = 16.8 ff Cmax = 0.0 ff G = 0
+ABC: Path 1 -- 28 : 1 2 gf180mcu_fd_sc_mcu7t5v0__clkinv_1 A = 8.78 Df = 326.2 -79.6 ps S = 194.6 ps Cin = 4.2 ff Cout = 6.9 ff Cmax = 228.4 ff G = 163
+ABC: Path 2 -- 29 : 1 4 gf180mcu_fd_sc_mcu7t5v0__buf_1 A = 13.17 Df = 672.2 -103.0 ps S = 310.4 ps Cin = 2.9 ff Cout = 15.4 ff Cmax = 238.8 ff G = 537
+ABC: Path 3 -- 30 : 2 4 gf180mcu_fd_sc_mcu7t5v0__or2_1 A = 17.56 Df =1189.7 -243.3 ps S = 352.0 ps Cin = 2.9 ff Cout = 17.9 ff Cmax = 238.8 ff G = 628
+ABC: Path 4 -- 52 : 2 2 gf180mcu_fd_sc_mcu7t5v0__nor2_1 A = 13.17 Df =1495.0 -363.0 ps S = 430.7 ps Cin = 4.4 ff Cout = 9.6 ff Cmax = 125.1 ff G = 220
+ABC: Path 5 -- 87 : 2 1 gf180mcu_fd_sc_mcu7t5v0__nand2_1 A = 10.98 Df =1606.2 -321.4 ps S = 166.0 ps Cin = 4.7 ff Cout = 2.8 ff Cmax = 212.6 ff G = 59
+ABC: Path 6 -- 88 : 2 1 gf180mcu_fd_sc_mcu7t5v0__and2_1 A = 17.56 Df =1868.5 -80.7 ps S = 127.8 ps Cin = 2.8 ff Cout = 2.9 ff Cmax = 237.8 ff G = 102
+ABC: Path 7 -- 89 : 1 2 gf180mcu_fd_sc_mcu7t5v0__buf_1 A = 13.17 Df =2677.1 -120.4 ps S =1329.1 ps Cin = 2.9 ff Cout = 77.2 ff Cmax = 238.8 ff G = 2685
+ABC: Path 8 -- 90 : 2 1 gf180mcu_fd_sc_mcu7t5v0__nor2_1 A = 13.17 Df =3992.4 -373.6 ps S =2308.4 ps Cin = 4.4 ff Cout = 72.9 ff Cmax = 125.1 ff G = 1671
+ABC: Start-point = pi0 (\wbs_we_i). End-point = po6 (\fsm_plant_opt.tmp3553).
+ABC: + print_stats -m
+ABC: netlist : i/o = 15/ 9 lat = 0 nd = 67 edge = 161 area =1047.13 delay = 8.00 lev = 8
+ABC: + write_blif /tmp/yosys-abc-9IHGfo/output.blif
+
+13.1.2. Re-integrating ABC results.
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__or2_1 cells: 2
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__nand4_1 cells: 1
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__and3_1 cells: 2
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__mux2_2 cells: 1
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__nand3_1 cells: 3
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__nor4_1 cells: 3
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__oai211_1 cells: 1
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__or3_1 cells: 1
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__nor3_1 cells: 1
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__aoi22_1 cells: 2
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__clkinv_1 cells: 6
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__oai21_1 cells: 5
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__and4_1 cells: 4
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__inv_1 cells: 2
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__nand2_1 cells: 12
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__and2_1 cells: 3
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__buf_1 cells: 6
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__nor2_1 cells: 6
+ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__aoi21_1 cells: 6
+ABC RESULTS: internal signals: 201
+ABC RESULTS: input signals: 15
+ABC RESULTS: output signals: 9
+Removing temp directory.
+
+14. Executing SETUNDEF pass (replace undef values with defined constants).
+
+15. Executing HILOMAP pass (mapping to constant drivers).
+
+16. Executing SPLITNETS pass (splitting up multi-bit signals).
+
+17. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \plant_example..
+Removed 0 unused cells and 301 unused wires.
+<suppressed ~4 debug messages>
+
+18. Executing INSBUF pass (insert buffer cells for connected wires).
+
+19. Executing CHECK pass (checking for obvious problems).
+Checking module plant_example...
+Warning: Wire plant_example.\io_out [37] is used but has no driver.
+Warning: Wire plant_example.\io_out [36] is used but has no driver.
+Warning: Wire plant_example.\io_out [35] is used but has no driver.
+Warning: Wire plant_example.\io_out [34] is used but has no driver.
+Warning: Wire plant_example.\io_out [33] is used but has no driver.
+Warning: Wire plant_example.\io_out [32] is used but has no driver.
+Warning: Wire plant_example.\io_out [31] is used but has no driver.
+Warning: Wire plant_example.\io_out [30] is used but has no driver.
+Warning: Wire plant_example.\io_out [29] is used but has no driver.
+Warning: Wire plant_example.\io_out [28] is used but has no driver.
+Warning: Wire plant_example.\io_out [27] is used but has no driver.
+Warning: Wire plant_example.\io_out [26] is used but has no driver.
+Warning: Wire plant_example.\io_out [25] is used but has no driver.
+Warning: Wire plant_example.\io_out [24] is used but has no driver.
+Warning: Wire plant_example.\io_out [23] is used but has no driver.
+Warning: Wire plant_example.\io_out [22] is used but has no driver.
+Warning: Wire plant_example.\io_out [21] is used but has no driver.
+Warning: Wire plant_example.\io_out [20] is used but has no driver.
+Warning: Wire plant_example.\io_out [19] is used but has no driver.
+Warning: Wire plant_example.\io_out [18] is used but has no driver.
+Warning: Wire plant_example.\io_out [17] is used but has no driver.
+Warning: Wire plant_example.\io_out [16] is used but has no driver.
+Warning: Wire plant_example.\io_out [15] is used but has no driver.
+Warning: Wire plant_example.\io_out [14] is used but has no driver.
+Warning: Wire plant_example.\io_out [13] is used but has no driver.
+Warning: Wire plant_example.\io_out [12] is used but has no driver.
+Warning: Wire plant_example.\io_out [11] is used but has no driver.
+Warning: Wire plant_example.\io_out [10] is used but has no driver.
+Warning: Wire plant_example.\io_out [9] is used but has no driver.
+Warning: Wire plant_example.\io_out [8] is used but has no driver.
+Warning: Wire plant_example.\io_out [7] is used but has no driver.
+Warning: Wire plant_example.\io_out [6] is used but has no driver.
+Warning: Wire plant_example.\io_out [5] is used but has no driver.
+Warning: Wire plant_example.\io_out [4] is used but has no driver.
+Warning: Wire plant_example.\io_out [3] is used but has no driver.
+Warning: Wire plant_example.\io_out [2] is used but has no driver.
+Warning: Wire plant_example.\io_out [1] is used but has no driver.
+Warning: Wire plant_example.\io_out [0] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [37] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [36] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [35] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [34] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [33] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [32] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [31] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [30] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [29] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [28] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [27] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [26] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [25] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [24] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [23] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [22] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [21] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [20] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [19] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [18] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [17] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [16] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [15] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [14] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [13] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [12] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [11] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [10] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [9] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [8] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [7] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [6] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [5] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [4] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [3] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [2] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [1] is used but has no driver.
+Warning: Wire plant_example.\io_oeb [0] is used but has no driver.
+Found and reported 76 problems.
+
+20. Printing statistics.
+
+=== plant_example ===
+
+ Number of wires: 77
+ Number of wire bits: 191
+ Number of public wires: 19
+ Number of public wire bits: 133
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 146
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 3
+ gf180mcu_fd_sc_mcu7t5v0__and3_1 2
+ gf180mcu_fd_sc_mcu7t5v0__and4_1 4
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 6
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 2
+ gf180mcu_fd_sc_mcu7t5v0__buf_1 6
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 6
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 6
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 2
+ gf180mcu_fd_sc_mcu7t5v0__mux2_2 1
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 12
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 3
+ gf180mcu_fd_sc_mcu7t5v0__nand4_1 1
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 6
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 1
+ gf180mcu_fd_sc_mcu7t5v0__nor4_1 3
+ gf180mcu_fd_sc_mcu7t5v0__oai211_1 1
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 5
+ gf180mcu_fd_sc_mcu7t5v0__or2_1 2
+ gf180mcu_fd_sc_mcu7t5v0__or3_1 1
+ gf180mcu_fd_sc_mcu7t5v0__tiel 73
+
+ Chip area for module '\plant_example': 2070.073600
+
+21. Executing Verilog backend.
+
+21.1. Executing BMUXMAP pass.
+
+21.2. Executing DEMUXMAP pass.
+Dumping module `\plant_example'.
+
+Warnings: 87 unique messages, 93 total
+End of script. Logfile hash: 8d4c9dc63d, CPU: user 1.48s system 0.07s, MEM: 58.64 MB peak
+Yosys 0.22 (git sha1 f109fa3d4c5, gcc 8.3.1 -fPIC -Os)
+Time spent: 34% 2x abc (0 sec), 22% 4x stat (0 sec), ...
diff --git a/openlane/user_proj_example/runs/user_proj_example/logs/synthesis/2-sta.log b/openlane/user_proj_example/runs/user_proj_example/logs/synthesis/2-sta.log
new file mode 100644
index 0000000..3ae8ede
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/logs/synthesis/2-sta.log
@@ -0,0 +1,602 @@
+OpenROAD 7c85c140308f01b73f57ea1117f3e43f39abd437
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+[INFO ODB-0222] Reading LEF file: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/merged.nom.lef
+[INFO ODB-0223] Created 13 technology layers
+[INFO ODB-0224] Created 60 technology vias
+[INFO ODB-0225] Created 229 library cells
+[INFO ODB-0226] Finished LEF file: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/tmp/merged.nom.lef
+Reading netlist...
+[INFO]: Setting output delay to: 6.0
+[INFO]: Setting input delay to: 6.0
+[INFO]: Setting load to: 0.07291
+[INFO]: Setting clock uncertainty to: 0.25
+[INFO]: Setting clock transition to: 0.15
+[INFO]: Setting timing derate to: 0.5 %
+min_report
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.19 0.68 0.68 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_water_synth_2 (net)
+ 0.19 0.00 0.68 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.46 0.33 1.01 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 4 0.02 _002_ (net)
+ 0.46 0.00 1.01 ^ _124_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.14 0.09 1.11 v _124_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp3555 (net)
+ 0.14 0.00 1.11 v _130_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.11 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.09 0.34 library hold time
+ 0.34 data required time
+-----------------------------------------------------------------------------
+ 0.34 data required time
+ -1.11 data arrival time
+-----------------------------------------------------------------------------
+ 0.77 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.19 0.68 0.68 v _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.19 0.00 0.68 v _094_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 0.22 0.17 0.85 ^ _094_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi22_1)
+ 1 0.00 _033_ (net)
+ 0.22 0.00 0.85 ^ _102_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.16 0.12 0.97 v _102_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _041_ (net)
+ 0.16 0.00 0.97 v _106_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.16 0.13 1.10 ^ _106_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _045_ (net)
+ 0.16 0.00 1.10 ^ _112_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.11 0.09 1.19 v _112_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2410 (net)
+ 0.11 0.00 1.19 v _125_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.19 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.09 0.34 library hold time
+ 0.34 data required time
+-----------------------------------------------------------------------------
+ 0.34 data required time
+ -1.19 data arrival time
+-----------------------------------------------------------------------------
+ 0.85 slack (MET)
+
+
+Startpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.24 0.76 0.76 ^ _126_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_temperature_synth_2 (net)
+ 0.24 0.00 0.76 ^ _070_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.29 0.23 0.99 v _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.29 0.00 0.99 v _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand4_1)
+ 0.19 0.22 1.21 ^ _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand4_1)
+ 1 0.00 _017_ (net)
+ 0.19 0.00 1.21 ^ _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.16 0.28 1.48 ^ _076_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _018_ (net)
+ 0.16 0.00 1.48 ^ _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.10 0.09 1.57 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.10 0.00 1.57 v _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.57 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.10 0.35 library hold time
+ 0.35 data required time
+-----------------------------------------------------------------------------
+ 0.35 data required time
+ -1.57 data arrival time
+-----------------------------------------------------------------------------
+ 1.23 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _128_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.19 0.68 0.68 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_water_synth_2 (net)
+ 0.19 0.00 0.68 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.46 0.33 1.01 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 4 0.02 _002_ (net)
+ 0.46 0.00 1.01 ^ _109_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.19 0.19 1.21 v _109_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 2 0.01 _048_ (net)
+ 0.19 0.00 1.21 v _121_/A1 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.10 0.24 1.45 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.10 0.00 1.45 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.13 0.24 1.69 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.13 0.00 1.69 v _128_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.69 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _128_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.09 0.34 library hold time
+ 0.34 data required time
+-----------------------------------------------------------------------------
+ 0.34 data required time
+ -1.69 data arrival time
+-----------------------------------------------------------------------------
+ 1.35 slack (MET)
+
+
+Startpoint: _130_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _130_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.19 0.68 0.68 v _130_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_water_synth_2 (net)
+ 0.19 0.00 0.68 v _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.46 0.33 1.01 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 4 0.02 _002_ (net)
+ 0.46 0.00 1.01 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 0.31 0.23 1.25 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
+ 3 0.01 _008_ (net)
+ 0.31 0.00 1.25 v _116_/A2 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.11 0.33 1.58 v _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.11 0.00 1.58 v _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.09 0.21 1.80 v _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.09 0.00 1.80 v _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.80 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.10 0.35 library hold time
+ 0.35 data required time
+-----------------------------------------------------------------------------
+ 0.35 data required time
+ -1.80 data arrival time
+-----------------------------------------------------------------------------
+ 1.45 slack (MET)
+
+
+min_report_end
+max_report
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.33 0.17 6.17 ^ wbs_we_i (in)
+ 4 0.02 wbs_we_i (net)
+ 0.33 0.00 6.17 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.19 0.17 6.34 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.19 0.00 6.34 v _072_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 0.76 0.42 6.76 ^ _072_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 2 0.01 _014_ (net)
+ 0.76 0.00 6.76 ^ _073_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.33 0.40 7.16 ^ _073_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 _015_ (net)
+ 0.33 0.00 7.16 ^ _097_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.27 0.56 7.72 ^ _097_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _036_ (net)
+ 0.27 0.00 7.72 ^ _114_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.24 0.21 7.93 v _114_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 _052_ (net)
+ 0.24 0.00 7.93 v _115_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.21 8.15 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.15 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.17 0.49 8.64 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.17 0.00 8.64 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.10 0.21 8.85 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.10 0.00 8.85 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.85 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.20 29.55 library setup time
+ 29.55 data required time
+-----------------------------------------------------------------------------
+ 29.55 data required time
+ -8.85 data arrival time
+-----------------------------------------------------------------------------
+ 20.70 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _129_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.33 0.17 6.17 ^ wbs_we_i (in)
+ 4 0.02 wbs_we_i (net)
+ 0.33 0.00 6.17 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.19 0.17 6.34 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.19 0.00 6.34 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.21 0.36 6.71 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 _004_ (net)
+ 0.21 0.00 6.71 v _078_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 1.02 0.57 7.28 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 3 0.01 _020_ (net)
+ 1.02 0.00 7.28 ^ _079_/A3 (gf180mcu_fd_sc_mcu7t5v0__and3_1)
+ 0.19 0.44 7.71 ^ _079_/Z (gf180mcu_fd_sc_mcu7t5v0__and3_1)
+ 1 0.00 _021_ (net)
+ 0.19 0.00 7.71 ^ _084_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.19 0.13 7.84 v _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _026_ (net)
+ 0.19 0.00 7.84 v _089_/I1 (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 0.13 0.39 8.23 v _089_/Z (gf180mcu_fd_sc_mcu7t5v0__mux2_2)
+ 1 0.00 _030_ (net)
+ 0.13 0.00 8.23 v _090_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.27 0.19 8.42 ^ _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 fsm_plant_opt.tmp2409 (net)
+ 0.27 0.00 8.42 ^ _129_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.42 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _129_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.23 29.52 library setup time
+ 29.52 data required time
+-----------------------------------------------------------------------------
+ 29.52 data required time
+ -8.42 data arrival time
+-----------------------------------------------------------------------------
+ 21.11 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.27 0.86 0.86 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.27 0.00 0.86 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.31 0.26 1.11 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.31 0.00 1.11 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.60 0.44 1.55 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.60 0.00 1.55 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.19 1.74 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 1.74 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1.40 0.90 2.63 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.07 io_oeb[0] (net)
+ 1.40 0.00 2.63 ^ io_oeb[0] (out)
+ 2.63 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.63 data arrival time
+-----------------------------------------------------------------------------
+ 21.12 slack (MET)
+
+
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _127_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.33 0.17 6.17 ^ wbs_we_i (in)
+ 4 0.02 wbs_we_i (net)
+ 0.33 0.00 6.17 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.19 0.17 6.34 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.19 0.00 6.34 v _062_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.21 0.36 6.71 v _062_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 _004_ (net)
+ 0.21 0.00 6.71 v _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 0.29 0.54 7.25 v _063_/Z (gf180mcu_fd_sc_mcu7t5v0__or2_1)
+ 4 0.02 _005_ (net)
+ 0.29 0.00 7.25 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.43 0.32 7.57 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _027_ (net)
+ 0.43 0.00 7.57 ^ _120_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.17 0.12 7.69 v _120_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 1 0.00 _056_ (net)
+ 0.17 0.00 7.69 v _121_/A2 (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 0.10 0.28 7.96 v _121_/Z (gf180mcu_fd_sc_mcu7t5v0__and2_1)
+ 1 0.00 _057_ (net)
+ 0.10 0.00 7.96 v _122_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.13 0.27 8.23 v _122_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2 0.01 fsm_plant_opt.tmp3554 (net)
+ 0.13 0.00 8.23 v _123_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.20 0.16 8.39 ^ _123_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 fsm_plant_opt.tmp3553 (net)
+ 0.20 0.00 8.39 ^ _127_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.39 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _127_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.22 29.53 library setup time
+ 29.53 data required time
+-----------------------------------------------------------------------------
+ 29.53 data required time
+ -8.39 data arrival time
+-----------------------------------------------------------------------------
+ 21.14 slack (MET)
+
+
+Startpoint: _125_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_oeb[1] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _125_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.27 0.86 0.86 ^ _125_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.01 fsm_plant_opt.state_temperature_synth_1 (net)
+ 0.27 0.00 0.86 ^ _069_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.31 0.26 1.11 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 4 0.02 _011_ (net)
+ 0.31 0.00 1.11 v _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.60 0.44 1.55 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4 0.02 _012_ (net)
+ 0.60 0.00 1.55 ^ _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 0.27 0.19 1.74 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
+ 2 0.01 _028_ (net)
+ 0.27 0.00 1.74 v _087_/I (gf180mcu_fd_sc_mcu7t5v0__inv_1)
+ 1.33 0.87 2.61 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__inv_1)
+ 2 0.08 io_oeb[1] (net)
+ 1.33 0.00 2.61 ^ io_oeb[1] (out)
+ 2.61 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ -6.00 23.75 output external delay
+ 23.75 data required time
+-----------------------------------------------------------------------------
+ 23.75 data required time
+ -2.61 data arrival time
+-----------------------------------------------------------------------------
+ 21.14 slack (MET)
+
+
+max_report_end
+check_report
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: wbs_we_i (input port clocked by wb_clk_i)
+Endpoint: _126_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 6.00 6.00 ^ input external delay
+ 0.33 0.17 6.17 ^ wbs_we_i (in)
+ 4 0.02 wbs_we_i (net)
+ 0.33 0.00 6.17 ^ _061_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 0.19 0.17 6.34 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_1)
+ 2 0.01 _003_ (net)
+ 0.19 0.00 6.34 v _072_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 0.76 0.42 6.76 ^ _072_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor4_1)
+ 2 0.01 _014_ (net)
+ 0.76 0.00 6.76 ^ _073_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.33 0.40 7.16 ^ _073_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.02 _015_ (net)
+ 0.33 0.00 7.16 ^ _097_/A3 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.27 0.56 7.72 ^ _097_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 2 0.01 _036_ (net)
+ 0.27 0.00 7.72 ^ _114_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.24 0.21 7.93 v _114_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 _052_ (net)
+ 0.24 0.00 7.93 v _115_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.27 0.21 8.15 ^ _115_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _053_ (net)
+ 0.27 0.00 8.15 ^ _116_/A4 (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 0.17 0.49 8.64 ^ _116_/Z (gf180mcu_fd_sc_mcu7t5v0__and4_1)
+ 1 0.00 _054_ (net)
+ 0.17 0.00 8.64 ^ _117_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.10 0.21 8.85 ^ _117_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1 0.00 fsm_plant_opt.tmp2411 (net)
+ 0.10 0.00 8.85 ^ _126_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 8.85 data arrival time
+
+ 0.15 30.00 30.00 clock wb_clk_i (rise edge)
+ 0.00 30.00 clock network delay (ideal)
+ -0.25 29.75 clock uncertainty
+ 0.00 29.75 clock reconvergence pessimism
+ 29.75 ^ _126_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.20 29.55 library setup time
+ 29.55 data required time
+-----------------------------------------------------------------------------
+ 29.55 data required time
+ -8.85 data arrival time
+-----------------------------------------------------------------------------
+ 20.70 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
+check_report_end
+check_slew
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
+check_slew_end
+tns_report
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
+tns_report_end
+wns_report
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
+wns_report_end
+worst_slack
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 20.70
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 0.77
+worst_slack_end
+clock_skew
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_125_/CLK ^
+ 0.05
+_125_/CLK ^
+ 0.05 0.00 0.00
+
+clock_skew_end
+power_report
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 1.09e-04 4.05e-06 1.22e-09 1.13e-04 69.1%
+Combinational 2.28e-05 2.75e-05 1.09e-08 5.04e-05 30.9%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 1.31e-04 3.16e-05 1.21e-08 1.63e-04 100.0%
+ 80.6% 19.4% 0.0%
+power_report_end
+area_report
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 2070 u^2 100% utilization.
+area_report_end
+[WARNING] Did not save OpenROAD database!
+Writing SDF to /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/synthesis/plant_example.sdf...
diff --git a/openlane/user_proj_example/runs/user_proj_example/openlane.log b/openlane/user_proj_example/runs/user_proj_example/openlane.log
index d00491f..143385c 100644
--- a/openlane/user_proj_example/runs/user_proj_example/openlane.log
+++ b/openlane/user_proj_example/runs/user_proj_example/openlane.log
@@ -1 +1,50 @@
-1
+[INFO]: Run Directory: /home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22
+[INFO]: Preparing LEF files for the nom corner...
+[INFO]: Running Synthesis (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/synthesis/1-synthesis.log)...
+[INFO]: Running Single-Corner Static Timing Analysis (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/synthesis/2-sta.log)...
+[INFO]: Running Initial Floorplanning (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/floorplan/3-initial_fp.log)...
+[INFO]: Floorplanned with width 886.48 and height 568.4.
+[INFO]: Running IO Placement (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/floorplan/4-place_io.log)...
+[INFO]: Running Tap/Decap Insertion (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/floorplan/5-tap.log)...
+[INFO]: Power planning with power {vdd} and ground {vss}...
+[INFO]: Generating PDN (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/floorplan/6-pdn.log)...
+[INFO]: Running Global Placement (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/placement/7-global.log)...
+[INFO]: Running Placement Resizer Design Optimizations (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/placement/8-resizer.log)...
+[INFO]: Running Detailed Placement (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/placement/9-detailed.log)...
+[INFO]: Running Clock Tree Synthesis (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/cts/10-cts.log)...
+[INFO]: Running Placement Resizer Timing Optimizations (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/cts/11-resizer.log)...
+[INFO]: Running Global Routing Resizer Timing Optimizations (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/12-resizer.log)...
+[INFO]: Running Diode Insertion (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/13-diodes.log)...
+[INFO]: Running Detailed Placement (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/14-diode_legalization.log)...
+[INFO]: Running Fill Insertion (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/15-fill.log)...
+[INFO]: Running Global Routing (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/16-global.log)...
+[INFO]: Writing Verilog (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/16-global_write_netlist.log)...
+[INFO]: Running Detailed Routing (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/18-detailed.log)...
+[INFO]: No DRC violations after detailed routing.
+[INFO]: Checking Wire Lengths (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/routing/19-wire_lengths.log)...
+[INFO]: Running SPEF Extraction at the nom process corner (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/20-parasitics_extraction.nom.log)...
+[INFO]: Running Multi-Corner Static Timing Analysis at the nom process corner (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/21-rcx_mcsta.nom.log)...
+[INFO]: Running Single-Corner Static Timing Analysis at the nom process corner (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/22-rcx_sta.log)...
+[INFO]: Running Magic to generate various views...
+[INFO]: Streaming out GDSII with Magic (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/23-gdsii.log)...
+[INFO]: Generating MAGLEF views...
+[INFO]: Running Magic Spice Export from LEF (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/24-spice.log)...
+[INFO]: Writing Powered Verilog (logs: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/25-write_powered_def.log, ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/25-write_powered_verilog.log)...
+[INFO]: Writing Verilog (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/25-write_powered_verilog.log)...
+[INFO]: Running LVS (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/27-lvs.lef.log)...
+[INFO]: Running Magic DRC (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/28-drc.log)...
+[INFO]: Converting Magic DRC database to various tool-readable formats...
+[INFO]: No DRC violations after GDS streaming out.
+[INFO]: Running OpenROAD Antenna Rule Checker (log: ../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/logs/signoff/29-antenna.log)...
+[WARNING]: This PDK does not support the Circuit Validity Checker, skipping...
+[INFO]: Saving current set of views in '../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/results/final'...
+[INFO]: Saving current set of views in '../home/xb4syf/ASIC/gf180-demo'...
+[INFO]: Saving runtime environment...
+[INFO]: Generating final set of reports...
+[INFO]: Created manufacturability report at '../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/manufacturability.rpt'.
+[INFO]: Created metrics report at '../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/metrics.csv'.
+[WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff/22-rcx_sta.slew.rpt'.
+[INFO]: There are no hold violations in the design at the typical corner.
+[INFO]: There are no setup violations in the design at the typical corner.
+[SUCCESS]: Flow complete.
+[INFO]: Note that the following warnings have been generated:
diff --git a/openlane/user_proj_example/runs/user_proj_example/runtime.yaml b/openlane/user_proj_example/runs/user_proj_example/runtime.yaml
new file mode 100644
index 0000000..952e1f5
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/runtime.yaml
@@ -0,0 +1,97 @@
+- status: 0 - openlane design prep
+ runtime_s: 2.7
+ runtime_ts: 0h0m2s702ms
+- status: 1 - synthesis - yosys
+ runtime_s: 3.26
+ runtime_ts: 0h0m3s261ms
+- status: 2 - sta - openroad
+ runtime_s: 0.91
+ runtime_ts: 0h0m0s912ms
+- status: 3 - floorplan initialization - openroad
+ runtime_s: 2.08
+ runtime_ts: 0h0m2s81ms
+- status: 4 - io_place - openlane
+ runtime_s: 0.46
+ runtime_ts: 0h0m0s464ms
+- status: 5 - tap/decap insertion - openroad
+ runtime_s: 1.06
+ runtime_ts: 0h0m1s58ms
+- status: 6 - pdn generation - openroad
+ runtime_s: 1.19
+ runtime_ts: 0h0m1s193ms
+- status: 7 - global placement - openroad
+ runtime_s: 3.38
+ runtime_ts: 0h0m3s383ms
+- status: 8 - resizer design optimizations - openroad
+ runtime_s: 1.4
+ runtime_ts: 0h0m1s401ms
+- status: 9 - detailed placement - openroad
+ runtime_s: 1.13
+ runtime_ts: 0h0m1s132ms
+- status: 10 - cts - openroad
+ runtime_s: 38.79
+ runtime_ts: 0h0m38s787ms
+- status: 11 - resizer timing optimizations - openroad
+ runtime_s: 1.33
+ runtime_ts: 0h0m1s326ms
+- status: 12 - resizer timing optimizations - openroad
+ runtime_s: 1.44
+ runtime_ts: 0h0m1s437ms
+- status: 14 - detailed placement - openroad
+ runtime_s: 1.14
+ runtime_ts: 0h0m1s135ms
+- status: 14 - diode insertion - openlane
+ runtime_s: 1.26
+ runtime_ts: 0h0m1s262ms
+- status: 15 - fill insertion - openroad
+ runtime_s: 1.34
+ runtime_ts: 0h0m1s338ms
+- status: 17 - write verilog - openroad
+ runtime_s: 0.99
+ runtime_ts: 0h0m0s991ms
+- status: 17 - global routing - openroad
+ runtime_s: 1.12
+ runtime_ts: 0h0m1s125ms
+- status: 18 - detailed_routing - openroad
+ runtime_s: 14.84
+ runtime_ts: 0h0m14s843ms
+- status: 19 - wire lengths - openlane
+ runtime_s: 0.48
+ runtime_ts: 0h0m0s478ms
+- status: 20 - parasitics extraction - openroad
+ runtime_s: 1.05
+ runtime_ts: 0h0m1s46ms
+- status: 21 - sta - openroad
+ runtime_s: 3.38
+ runtime_ts: 0h0m3s382ms
+- status: 22 - sta - openroad
+ runtime_s: 1.35
+ runtime_ts: 0h0m1s347ms
+- status: 23 - gdsii - magic
+ runtime_s: 3.38
+ runtime_ts: 0h0m3s375ms
+- status: 24 - spice extraction - magic
+ runtime_s: 6.91
+ runtime_ts: 0h0m6s910ms
+- status: 26 - write verilog - openroad
+ runtime_s: 1.06
+ runtime_ts: 0h0m1s56ms
+- status: 26 - write powered verilog - openlane
+ runtime_s: 1.21
+ runtime_ts: 0h0m1s209ms
+- status: 27 - lvs - netgen
+ runtime_s: 0.48
+ runtime_ts: 0h0m0s476ms
+- status: 28 - drc - magic
+ runtime_s: 50.34
+ runtime_ts: 0h0m50s335ms
+- status: 29 - antenna check - openroad
+ runtime_s: 1.04
+ runtime_ts: 0h0m1s36ms
+---
+- status: routed
+ runtime_s: 84.0
+ runtime_ts: 0h1m24s0ms
+- status: flow completed
+ runtime_s: 155.0
+ runtime_ts: 0h2m35s0ms
diff --git a/openlane/user_proj_example/runs/user_proj_example/warnings.log b/openlane/user_proj_example/runs/user_proj_example/warnings.log
new file mode 100644
index 0000000..55a83ee
--- /dev/null
+++ b/openlane/user_proj_example/runs/user_proj_example/warnings.log
@@ -0,0 +1,2 @@
+[WARNING]: This PDK does not support the Circuit Validity Checker, skipping...
+[WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../home/xb4syf/ASIC/gf180-demo/openlane/user_proj_example/runs/22_12_05_10_22/reports/signoff/22-rcx_sta.slew.rpt'.
