af4315240f00b9fec3ce21e9a62edba08f6e77af - third_party/shuttle/gf180mcu/mpw-000/slot-038

commit	af4315240f00b9fec3ce21e9a62edba08f6e77af	[log] [tgz]
author	luisadolfo180 <119854393+luisadolfo180@users.noreply.github.com>	Mon Dec 05 04:29:01 2022 -0600
committer	GitHub <noreply@github.com>	Mon Dec 05 04:29:01 2022 -0600
tree	0c7f5c2ec8f03d7a98c38b64b158b0abd949594f

Add files via upload

LICENSE[Added - diff]
Makefile[Added - diff]
README.md[Added - diff]
def/OQPSK_RCOSINE_ALL.def[Added - diff]
def/user_proj_example.def[Added - diff]
def/user_project_wrapper.def[Added - diff]
docs/Makefile[Added - diff]
docs/environment.yml[Added - diff]
docs/requirements.txt[Added - diff]
docs/source/_static/counter_32.png[Added - diff]
docs/source/_static/empty.png[Added - diff]
docs/source/_static/layout.png[Added - diff]
docs/source/_static/option1.png[Added - diff]
docs/source/_static/option2.png[Added - diff]
docs/source/_static/option3.png[Added - diff]
docs/source/_static/pitch.png[Added - diff]
docs/source/_static/wrapper.png[Added - diff]
docs/source/conf.py[Added - diff]
docs/source/index.rst[Added - diff]
gds/OQPSK_RCOSINE_ALL.gds[Added - diff]
gds/user_proj_example.gds[Added - diff]
gds/user_project_wrapper.gds[Added - diff]
lef/OQPSK_RCOSINE_ALL.lef[Added - diff]
lef/user_proj_example.lef[Added - diff]
lef/user_project_wrapper.lef[Added - diff]
lib/OQPSK_RCOSINE_ALL.lib[Added - diff]
lib/user_proj_example.lib[Added - diff]
lib/user_project_wrapper.lib[Added - diff]
mag/OQPSK_RCOSINE_ALL.mag[Added - diff]
mag/user_proj_example.mag[Added - diff]
mag/user_project_wrapper.mag[Added - diff]
maglef/OQPSK_RCOSINE_ALL.mag[Added - diff]
maglef/user_proj_example.mag[Added - diff]
maglef/user_project_wrapper.mag[Added - diff]
openlane/Makefile[Added - diff]
openlane/modulador_a/config.tcl[Added - diff]
openlane/user_proj_example/config.tcl[Added - diff]
openlane/user_proj_example/pin_order.cfg[Added - diff]
openlane/user_project_wrapper/config.tcl[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def[Added - diff]
openlane/user_project_wrapper/macro.cfg[Added - diff]
openlane/user_project_wrapper/pin_order.cfg[Added - diff]
sdc/OQPSK_RCOSINE_ALL.sdc[Added - diff]
sdc/user_proj_example.sdc[Added - diff]
sdc/user_project_wrapper.sdc[Added - diff]
sdf/OQPSK_RCOSINE_ALL.sdf[Added - diff]
sdf/multicorner/nom/user_project_wrapper.ff.sdf[Added - diff]
sdf/multicorner/nom/user_project_wrapper.ss.sdf[Added - diff]
sdf/multicorner/nom/user_project_wrapper.tt.sdf[Added - diff]
sdf/user_proj_example.sdf[Added - diff]
sdf/user_project_wrapper.sdf[Added - diff]
signoff/modulador_a/OPENLANE_VERSION[Added - diff]
signoff/modulador_a/PDK_SOURCES[Added - diff]
signoff/modulador_a/metrics.csv[Added - diff]
signoff/user_proj_example/OPENLANE_VERSION[Added - diff]
signoff/user_proj_example/PDK_SOURCES[Added - diff]
signoff/user_proj_example/metrics.csv[Added - diff]
signoff/user_project_wrapper/OPENLANE_VERSION[Added - diff]
signoff/user_project_wrapper/PDK_SOURCES[Added - diff]
signoff/user_project_wrapper/metrics.csv[Added - diff]
spef/OQPSK_RCOSINE_ALL.spef[Added - diff]
spef/multicorner/user_project_wrapper.nom.spef[Added - diff]
spef/user_proj_example.spef[Added - diff]
spef/user_project_wrapper.spef[Added - diff]
spi/lvs/OQPSK_RCOSINE_ALL.spice[Added - diff]
spi/lvs/user_proj_example.spice[Added - diff]
spi/lvs/user_project_wrapper.spice[Added - diff]
verilog/dv/README.md[Added - diff]
verilog/gl/OQPSK_RCOSINE_ALL.nl.v[Added - diff]
verilog/gl/OQPSK_RCOSINE_ALL.v[Added - diff]
verilog/gl/user_proj_example.v[Added - diff]
verilog/gl/user_project_wrapper.nl.v[Added - diff]
verilog/gl/user_project_wrapper.v[Added - diff]
verilog/includes/includes.gl+sdf.caravel_user_project[Added - diff]
verilog/includes/includes.gl.caravel_user_project[Added - diff]
verilog/includes/includes.rtl.caravel_user_project[Added - diff]
verilog/rtl/OQPSK_RCOSINE_ALL.v[Added - diff]
verilog/rtl/defines.v[Added - diff]
verilog/rtl/uprj_netlists.v[Added - diff]
verilog/rtl/user_defines.v[Added - diff]
verilog/rtl/user_proj_example.v[Added - diff]
verilog/rtl/user_project_wrapper.v[Added - diff]

85 files changed

tree: 0c7f5c2ec8f03d7a98c38b64b158b0abd949594f

README.md

Test of gf180 with an asynchronous modulator, which is part of a PhD project at Cinvestav in Guadalajara, Mexico.