tapeout/outputs/drc/caravel_18006e0d_esd.lyrdb

<?xml version="1.0" encoding="utf-8"?>
<report-database>
 <description>DRC Run Report at</description>
 <original-file/>
 <generator>drc: script='/mnt/shuttles/shuttle/gfmpw-0/u9822_susanao/modulador/tapeout/outputs/drc/esd.drc'</generator>
 <top-cell>caravel_18006e0d</top-cell>
 <tags>
 </tags>
 <categories>
  <category>
   <name>ESD.1</name>
   <description>ESD.1 : Minimum width of an ESD implant area. : 0.6µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.2</name>
   <description>ESD.2 : Minimum space between two ESD implant areas. (Merge if the space is less than 0.6um). : 0.6µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.3a</name>
   <description>ESD.3a : Minimum space to NCOMP. : 0.6µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.3b</name>
   <description>ESD.3b : Min/max space to a butted PCOMP.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.4a</name>
   <description>ESD.4a : Extension beyond NCOMP. : 0.24µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.4b</name>
   <description>ESD.4b : Minimum overlap of an ESD implant edge to a COMP. : 0.45µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.5a</name>
   <description>ESD.5a : Minimum ESD area (um2). : 0.49µm²</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.5b</name>
   <description>ESD.5b : Minimum field area enclosed by ESD implant (um2). : 0.49µm²</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.6</name>
   <description>ESD.6 : Extension perpendicular to Poly2 gate. : 0.45µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.7</name>
   <description>ESD.7 : No ESD implant inside PCOMP.</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.8</name>
   <description>ESD.8 : Minimum space to Nplus/Pplus. : 0.3µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.pl</name>
   <description>ESD.pl : Minimum gate length of 5V/6V gate NMOS. : 0.8µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.9</name>
   <description>ESD.9 : ESD implant layer must be overlapped by Dualgate layer (as ESD implant option is only for 5V/6V devices).</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>ESD.10</name>
   <description>ESD.10 : LVS_IO shall be drawn covering I/O MOS active area by minimum overlap.</description>
   <categories>
   </categories>
  </category>
 </categories>
 <cells>
  <cell>
   <name>caravel_18006e0d</name>
   <variant/>
   <references>
   </references>
  </cell>
 </cells>
 <items>
 </items>
</report-database>