tapeout/outputs/drc/caravel_18005f3a_dnwell.lyrdb

<?xml version="1.0" encoding="utf-8"?>
<report-database>
 <description>DRC Run Report at</description>
 <original-file/>
 <generator>drc: script='/mnt/shuttles/shuttle/gfmpw-0/u9820_lpgarci/divider/tapeout/outputs/drc/dnwell.drc'</generator>
 <top-cell>caravel_18005f3a</top-cell>
 <tags>
 </tags>
 <categories>
  <category>
   <name>DN.1</name>
   <description>DN.1 : Min. DNWELL Width : 1.7µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DN.2b_</name>
   <description>DN.2b_ : Min. DNWELL Space (Different potential) : 5.42µm</description>
   <categories>
   </categories>
  </category>
  <category>
   <name>DN.3</name>
   <description>DN.3 : Each DNWELL shall be directly surrounded by PCOMP guard ring tied to the P-substrate potential.</description>
   <categories>
   </categories>
  </category>
 </categories>
 <cells>
  <cell>
   <name>caravel_18005f3a</name>
   <variant/>
   <references>
   </references>
  </cell>
 </cells>
 <items>
 </items>
</report-database>