)]}'
{
  "commit": "e66c94fb7b6a8caccbebf38b08ec9eea54999e5c",
  "tree": "57a0494152514a43392d9404ad351651fd17f654",
  "parents": [
    "29dce52b37b67142942e6419185952e83ad45b12"
  ],
  "author": {
    "name": "rolf widenfelt",
    "email": "rolfvw@gmail.com",
    "time": "Sun Dec 04 23:28:17 2022 -0800"
  },
  "committer": {
    "name": "rolf widenfelt",
    "email": "rolfvw@gmail.com",
    "time": "Sun Dec 04 23:28:17 2022 -0800"
  },
  "message": "add a 16x4 regfile to the project\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d15b271f95ca198f0c7aa23ffd3d29e5d1e4527f",
      "old_mode": 33188,
      "old_path": "info.yaml",
      "new_id": "9f4bf39b6b22d44a91e550c8b1bd5a5f8412ec8f",
      "new_mode": 33188,
      "new_path": "info.yaml"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "1a545f2ecc95f5f6c844acd771a4c89b93b1ed70",
      "new_mode": 33188,
      "new_path": "verilog/rtl/regfile16x4.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "d3be45183f40c1d0f4045af957151be3971c13ee",
      "new_mode": 33188,
      "new_path": "verilog/rtl/regfile_top.v"
    }
  ]
}