)]}'
{
  "commit": "56f26233bf249d532a2f58f49515260516e06098",
  "tree": "133eabdf8106e67778d0c918d364500e437c790f",
  "parents": [
    "aa1eabecd43b8c9982bbb7ce1b8cad35c57488da"
  ],
  "author": {
    "name": "rolf widenfelt",
    "email": "rolfvw@gmail.com",
    "time": "Sat Dec 03 23:53:17 2022 -0800"
  },
  "committer": {
    "name": "rolf widenfelt",
    "email": "rolfvw@gmail.com",
    "time": "Sat Dec 03 23:53:17 2022 -0800"
  },
  "message": "add my verilog files (1st draft)\n",
  "tree_diff": [
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      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "65715ba0c3b50ba3466da38f06a483e815edb5e6",
      "new_mode": 33188,
      "new_path": "verilog/rtl/top.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "a97e006d6a329d879555f545ebedabc497f92ac0",
      "new_mode": 33188,
      "new_path": "verilog/rtl/xnor1.v"
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}