commit 29dce52b37b67142942e6419185952e83ad45b12
author rolf widenfelt <rolfvw@gmail.com> Sun Dec 04 00:32:02 2022 -0800
committer rolf widenfelt <rolfvw@gmail.com> Sun Dec 04 00:32:02 2022 -0800
tree 1da5df44709637c5d7ac91814aa480439fe286d9
parent ad47a17012fbf6438066cae8001647cecddaaf4d

typo

verilog/rtl/top.v

diff --git a/verilog/rtl/top.v b/verilog/rtl/top.v
index 4c533ab..aaecffc 100644
--- a/verilog/rtl/top.v
+++ b/verilog/rtl/top.v
@@ -13,7 +13,7 @@
   wire clk = io_in[7];      // notused
   wire reset = io_in[6];    // notused
   wire xnor_a = io_in[5];
-  wire nxor_b = io_in[4];
+  wire xnor_b = io_in[4];
   wire [3:0] notused_in = io_in[3:0];
 
   assign io_out[7] = xnor_y;