Sign in
foss-eda-tools
/
third_party
/
shuttle
/
gf180mcu
/
mpw-000
/
slot-032
/
cd3bb635faa9ef6940c9a278ae0aa459b19be3d3
commit
cd3bb635faa9ef6940c9a278ae0aa459b19be3d3
[
log
]
[
tgz
]
author
AbdulMoizSheikh1 <119680153+AbdulMoizSheikh1@users.noreply.github.com>
Mon Dec 05 16:12:39 2022 +0500
committer
GitHub <noreply@github.com>
Mon Dec 05 16:12:39 2022 +0500
tree
5fc0853b0ac705185252b4dc714a82470c8bf535
parent
d75b7c110f1c910316924e242bac71da489ec943
[
diff
]
Delete Verilog_Code directory
Verilog_Code/REadme.md
[Deleted -
diff
]
Verilog_Code/clock_mux.v
[Deleted -
diff
]
Verilog_Code/sha256.v
[Deleted -
diff
]
Verilog_Code/sha256_core.v
[Deleted -
diff
]
Verilog_Code/sha256_k_constants.v
[Deleted -
diff
]
Verilog_Code/sha256_w_mem.v
[Deleted -
diff
]
Verilog_Code/tb_clock_mux.v
[Deleted -
diff
]
Verilog_Code/tb_sha256.v
[Deleted -
diff
]
Verilog_Code/tb_sha256.v.bak
[Deleted -
diff
]
Verilog_Code/tb_sha256_core.v
[Deleted -
diff
]
Verilog_Code/tb_sha256_w_mem.v
[Deleted -
diff
]
Verilog_Code/tb_top.v
[Deleted -
diff
]
Verilog_Code/top_tukka_proj.v
[Deleted -
diff
]
13 files changed
tree: 5fc0853b0ac705185252b4dc714a82470c8bf535
def/
deps/
docs/
gds/
lef/
lib/
mag/
maglef/
sdc/
sdf/
signoff/
spef/
spi/
venv/
verilog/
caravel
LICENSE
Makefile
Readme
README.md
README.md
This is test This is actuall This is type ofactuall