io
diff --git a/configure.py b/configure.py
index 9bf5775..af0b1be 100755
--- a/configure.py
+++ b/configure.py
@@ -128,7 +128,6 @@
def get_io_ranges(yaml):
input_range = (GPIO_VALID_RANGE[0], GPIO_VALID_RANGE[0]+len(yaml['documentation']['inputs']))
output_range = (input_range[1], input_range[1]+len(yaml['documentation']['outputs']))
-# output_range = (GPIO_VALID_RANGE[0], GPIO_VALID_RANGE[0]+len(yaml['documentation']['outputs']))
gpio_end = output_range[1]
if gpio_end > GPIO_VALID_RANGE[1]:
raise Exception('ETOOMANY IOs')
diff --git a/verilog/rtl/pyramiden_core.v b/verilog/rtl/pyramiden_core.v
index 6d0790a..052249d 100644
--- a/verilog/rtl/pyramiden_core.v
+++ b/verilog/rtl/pyramiden_core.v
@@ -285,8 +285,10 @@
assign dmem_dout = des_dout[36:21];
assign des_din[13:0] = imem_addr;
+ ssign des_din[15:14] = 2'd0;
assign des_din[31:16] = dmem_addr;
assign des_din[47:32] = dmem_din;
+ assign des_din[63:48] = 16'd0;
///////////////////////////////////////////////////////////////////////////
diff --git a/verilog/rtl/tiny_user_project.v b/verilog/rtl/tiny_user_project.v
index 8689351..e53d242 100644
--- a/verilog/rtl/tiny_user_project.v
+++ b/verilog/rtl/tiny_user_project.v
@@ -42,10 +42,10 @@
// pass input and output pins defined in user_defines.v
pyramiden_core mod (
io_in[18:0],
- io_out[18:0]
+ io_out[37:19]
);
// all output enabled
-assign io_oeb[18:0] = 19'd0;
+assign io_oeb[37:19] = 'd0;
endmodule // tiny_user_project
diff --git a/verilog/rtl/tiny_user_project.v.jinja2 b/verilog/rtl/tiny_user_project.v.jinja2
index ab6098e..cc4708b 100644
--- a/verilog/rtl/tiny_user_project.v.jinja2
+++ b/verilog/rtl/tiny_user_project.v.jinja2
@@ -41,11 +41,11 @@
// pass input and output pins defined in user_defines.v
{{ module_name }} mod (
- io_in[18:0],
- io_out[18:0]
+ io_in[{{ io_in_range[1] - 1 }}:{{ io_in_range[0] }}],
+ io_out[{{ io_out_range[1] - 1 }}:{{ io_out_range[0] }}]
);
// all output enabled
-assign io_oeb[18:0] = 19'd0;
+assign io_oeb[{{ io_out_range[1] - 1 }}:{{ io_out_range[0] }}] = 'd0;
endmodule // tiny_user_project
diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v
index b5188d2..0ee1921 100644
--- a/verilog/rtl/user_defines.v
+++ b/verilog/rtl/user_defines.v
@@ -87,4 +87,4 @@
`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_USER_STD_OUTPUT
`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_USER_STD_OUTPUT
-`endif // __USER_DEFINES_H
\ No newline at end of file
+`endif // __USER_DEFINES_H
