diff --git a/verilog/rtl/des.v b/verilog/rtl/des.v
index 8aa8892..6ef1ad8 100644
--- a/verilog/rtl/des.v
+++ b/verilog/rtl/des.v
@@ -21,11 +21,11 @@
 	input in_clk,
 	input rst,
 
-   input [15:0] des_sin,
+   input [12:0] des_sin,
    output reg [15:0] des_sout,
 
    input [63:0] des_din,
-   output reg [63:0] des_dout,
+   output reg [51:0] des_dout,
 
 	output reg des_clk_out
 );
@@ -55,10 +55,10 @@
    always @ (posedge in_clk)
    begin
       case (des_counter)
-         3'b000: des_dout[15:0] <= des_sin;
-         3'b001: des_dout[31:16] <= des_sin;
-         3'b010: des_dout[47:32] <= des_sin;
-         3'b011: des_dout[63:48] <= des_sin;
+         3'b000: des_dout[12:0] <= des_sin;
+         3'b001: des_dout[25:13] <= des_sin;
+         3'b010: des_dout[38:26] <= des_sin;
+         3'b011: des_dout[51:39] <= des_sin;
          3'b100: begin end
          3'b101: begin end
          3'b110: begin end
diff --git a/verilog/rtl/pyramiden_core.v b/verilog/rtl/pyramiden_core.v
index fdc0d17..6d0790a 100644
--- a/verilog/rtl/pyramiden_core.v
+++ b/verilog/rtl/pyramiden_core.v
@@ -21,8 +21,8 @@
 
 //	input in_clk,
 
-	input [19:0] io_in,
-	output [17:0] io_out
+	input [18:0] io_in,
+	output [18:0] io_out
 
 //	output [BITS-3:0] debug_pc,
 //	output [IBITS-1:0] debug_instr,
@@ -42,9 +42,9 @@
 	////////////////////////////////
 
 	parameter BITS = 16;
-	parameter IBITS = 18;
-	parameter RBITS = 3;
-	parameter NREG = 8;
+	parameter IBITS = 21;
+	parameter RBITS = 4;
+	parameter NREG = 16;
 
 
 	///////////////////////////////////////////////////////////////////////////
@@ -220,10 +220,10 @@
    /////////////////////////
 
    wire des_clk_out;
-   wire [15:0] des_sin;
+   wire [12:0] des_sin;
    wire [15:0] des_sout;
    wire [63:0] des_din;
-   wire [63:0] des_dout;
+   wire [51:0] des_dout;
 
    //////////////////////////
    ////////// core //////////
@@ -253,13 +253,16 @@
 
 	assign in_clk 				= io_in[0]; // ZZZ
 	assign rst 				= io_in[1];
-	assign run 				= (~ rst); //io_in[2];
-//	assign ??? 				= io_in[3];
-	assign des_sin			= io_in[19:4];
+	assign run 				= io_in[2];
+	assign imem_rdy 		= io_in[3];
+	assign dmem_bsy 		= io_in[4];
+	assign dmem_rdy 		= io_in[5];
+	assign des_sin			= io_in[18:6];
 
 	assign io_out[0]		= halt;
-//	assign io_out[1]		= ???
-	assign io_out[17:2]	= des_sout;
+	assign io_out[1] 		= dmem_we;
+	assign io_out[2] 		= dmem_en;
+	assign io_out[18:3]	= des_sout;
 
 
    ///////////////////////////////////////////////////////////////////////////
@@ -278,19 +281,12 @@
 
 	assign clk = des_clk_out;
 
-   assign imem_dout	= des_dout[17:0];
-   assign dmem_dout	= des_dout[33:18];
-	assign imem_rdy	= 1; //des_dout[34];
-	assign dmem_bsy	= 0; //des_dout[35];
-	assign dmem_rdy	= 1; //des_dout[36];
+   assign imem_dout	= des_dout[20:0];
+   assign dmem_dout	= des_dout[36:21];
 
-   assign des_din[6:0]		= imem_addr[6:0];
-   assign des_din[13:7]		= dmem_addr[6:0];
-   assign des_din[29:14]	= dmem_din;
-   assign des_din[30]		= dmem_we;
-   assign des_din[31]		= dmem_en;
-   assign des_din[38:32]	= imem_addr[13:7];
-   assign des_din[47:39]	= dmem_addr[15:7];
+   assign des_din[13:0]		= imem_addr;
+   assign des_din[31:16]	= dmem_addr;
+   assign des_din[47:32]	= dmem_din;
 
 
 	///////////////////////////////////////////////////////////////////////////
@@ -393,7 +389,7 @@
 		if (imem_rdy)
 			nxt_instr = imem_dout[IBITS-1:0];
 		else
-			nxt_instr = 18'h3ffff;
+			nxt_instr = 21'h1fffff;
 	end
 
 	always @ (posedge clk)
@@ -443,7 +439,7 @@
 			if (valid_out1)
 				instr_2 <= instr;
 			else
-				instr_2 <= 18'h3ffff;
+				instr_2 <= 21'h1fffff;
 		end
 		else begin
 			pc_2 <= pc_2;
@@ -474,11 +470,11 @@
 
 
 	assign opcode = instr_2[2:0];
-	assign rd = instr_2[5:3];
-	assign funct3 = instr_2[8:6];
-	assign rs1 = instr_2[11:9];
-	assign rs2 = instr_2[14:12];
-	assign funct7 = instr_2[17:15];
+	assign rd = instr_2[6:3];
+	assign funct3 = instr_2[9:7];
+	assign rs1 = instr_2[13:10];
+	assign rs2 = instr_2[17:14];
+	assign funct7 = instr_2[20:18];
 
 	assign rv_op_imm 		= (opcode == 3'b001);
 	assign rv_op	 		= (opcode == 3'b011);
@@ -518,30 +514,23 @@
 
 	assign ri = rv_itype | rv_stype;
 
-	assign s[15] = instr_2[17];
-	assign s[14] = instr_2[17];
-	assign s[13] = instr_2[17];
-	assign s[12] = instr_2[17];
-	assign s[11] = instr_2[17];
-	assign s[10] = instr_2[17];
-	assign s[9] = instr_2[17];
-	assign s[8] = instr_2[17];
-	assign s[7] = instr_2[17];
-	assign s[6] = instr_2[17];
-
-	assign opcode = instr_2[2:0];
-	assign rd = instr_2[5:3];
-	assign funct3 = instr_2[8:6];
-	assign rs1 = instr_2[11:9];
-	assign rs2 = instr_2[14:12];
-	assign funct7 = instr_2[17:15];
+	assign s[15] = instr_2[20];
+	assign s[14] = instr_2[20];
+	assign s[13] = instr_2[20];
+	assign s[12] = instr_2[20];
+	assign s[11] = instr_2[20];
+	assign s[10] = instr_2[20];
+	assign s[9] = instr_2[20];
+	assign s[8] = instr_2[20];
+	assign s[7] = instr_2[20];
+	assign s[6] = instr_2[20];
 
    always @ (*)
    begin
       if (rv_itype)
-         imm6 = { instr_2[17:12] };
+         imm6 = { instr_2[19:14] };
       else
-         imm6 = { instr_2[17:15], instr_2[5:3] };
+         imm6 = { instr_2[20:18], instr_2[5:3] };
    end
 
 	always @ (*)
@@ -549,7 +538,7 @@
 		if (rv_itype|rv_stype|rv_btype)
 			imm = { s[15:6], imm6 };
 		else
-			imm = { s[15:12], instr_2[17:6] };
+			imm = { s[15:12], instr_2[18:7] };
 	end
 
 
diff --git a/verilog/rtl/registers.v b/verilog/rtl/registers.v
index f9e1df4..dd0a669 100644
--- a/verilog/rtl/registers.v
+++ b/verilog/rtl/registers.v
@@ -33,8 +33,8 @@
 );
 
 	parameter BITS = 16;
-	parameter RBITS = 3;
-	parameter NREG = 8;
+	parameter RBITS = 4;
+	parameter NREG = 16;
 
 	reg [BITS-1:0] r1;
 	reg [BITS-1:0] r2;
@@ -43,43 +43,91 @@
 	reg [BITS-1:0] r5;
 	reg [BITS-1:0] r6;
 	reg [BITS-1:0] r7;
+	reg [BITS-1:0] r8;
+	reg [BITS-1:0] r9;
+	reg [BITS-1:0] r10;
+	reg [BITS-1:0] r11;
+	reg [BITS-1:0] r12;
+	reg [BITS-1:0] r13;
+	reg [BITS-1:0] r14;
+	reg [BITS-1:0] r15;
 
 	always @ (posedge clk)
 	begin
-		if (run & we & (rd==3'b001)) 
+		if (run & we & (rd==4'b0001)) 
     	  r1 <= rd_din;
 		else 
 			r1 <= r1;
 
-		if (run & we & (rd==3'b010)) 
+		if (run & we & (rd==4'b0010)) 
     	  r2 <= rd_din;
 		else 
 			r2 <= r2;
 
-		if (run & we & (rd==3'b011)) 
+		if (run & we & (rd==4'b0011)) 
     	  r3 <= rd_din;
 		else 
 			r3 <= r3;
 
-		if (run & we & (rd==3'b100)) 
+		if (run & we & (rd==4'b0100)) 
     	  r4 <= rd_din;
 		else 
 			r4 <= r4;
 
-		if (run & we & (rd==3'b101)) 
+		if (run & we & (rd==4'b0101)) 
     	  r5 <= rd_din;
 		else 
 			r5 <= r5;
 
-		if (run & we & (rd==3'b110)) 
+		if (run & we & (rd==4'b0110)) 
     	  r6 <= rd_din;
 		else 
 			r6 <= r6;
 
-		if (run & we & (rd==3'b111)) 
+		if (run & we & (rd==4'b0111)) 
     	  r7 <= rd_din;
 		else 
 			r7 <= r7;
+
+		if (run & we & (rd==4'b1000)) 
+    	  r8 <= rd_din;
+		else 
+			r8 <= r8;
+
+		if (run & we & (rd==4'b1001)) 
+    	  r9 <= rd_din;
+		else 
+			r9 <= r9;
+
+		if (run & we & (rd==4'b1010)) 
+    	  r10 <= rd_din;
+		else 
+			r10 <= r10;
+
+		if (run & we & (rd==4'b1011)) 
+    	  r11 <= rd_din;
+		else 
+			r11 <= r11;
+
+		if (run & we & (rd==4'b1100)) 
+    	  r12 <= rd_din;
+		else 
+			r12 <= r12;
+
+		if (run & we & (rd==4'b1101)) 
+    	  r13 <= rd_din;
+		else 
+			r13 <= r13;
+
+		if (run & we & (rd==4'b1110)) 
+    	  r14 <= rd_din;
+		else 
+			r14 <= r14;
+
+		if (run & we & (rd==4'b1111)) 
+    	  r15 <= rd_din;
+		else 
+			r15 <= r15;
 	end
 
 
@@ -89,25 +137,41 @@
 	begin
 
 		case (rs1)
-			3'b000: rs1_dout = 'd0;
-			3'b001: rs1_dout = r1;
-			3'b010: rs1_dout = r2;
-			3'b011: rs1_dout = r3;
-			3'b100: rs1_dout = r4;
-			3'b101: rs1_dout = r5;
-			3'b110: rs1_dout = r6;
-			3'b111: rs1_dout = r7;
+			4'b0000: rs1_dout = 'd0;
+			4'b0001: rs1_dout = r1;
+			4'b0010: rs1_dout = r2;
+			4'b0011: rs1_dout = r3;
+			4'b0100: rs1_dout = r4;
+			4'b0101: rs1_dout = r5;
+			4'b0110: rs1_dout = r6;
+			4'b0111: rs1_dout = r7;
+			4'b1000: rs1_dout = r8;
+			4'b1001: rs1_dout = r9;
+			4'b1010: rs1_dout = r10;
+			4'b1011: rs1_dout = r11;
+			4'b1100: rs1_dout = r12;
+			4'b1101: rs1_dout = r13;
+			4'b1110: rs1_dout = r14;
+			4'b1111: rs1_dout = r15;
 		endcase
 
 		case (rs2)
-			3'b000: rs2_dout = 'd0;
-			3'b001: rs2_dout = r1;
-			3'b010: rs2_dout = r2;
-			3'b011: rs2_dout = r3;
-			3'b100: rs2_dout = r4;
-			3'b101: rs2_dout = r5;
-			3'b110: rs2_dout = r6;
-			3'b111: rs2_dout = r7;
+			4'b0000: rs2_dout = 'd0;
+			4'b0001: rs2_dout = r1;
+			4'b0010: rs2_dout = r2;
+			4'b0011: rs2_dout = r3;
+			4'b0100: rs2_dout = r4;
+			4'b0101: rs2_dout = r5;
+			4'b0110: rs2_dout = r6;
+			4'b0111: rs2_dout = r7;
+			4'b1000: rs2_dout = r8;
+			4'b1001: rs2_dout = r9;
+			4'b1010: rs2_dout = r10;
+			4'b1011: rs2_dout = r11;
+			4'b1100: rs2_dout = r12;
+			4'b1101: rs2_dout = r13;
+			4'b1110: rs2_dout = r14;
+			4'b1111: rs2_dout = r15;
 		endcase
 
 	end
@@ -116,14 +180,22 @@
 	always @ (*)
 	begin
 		case(debug_reg_sel)
-			3'b000: debug_reg_dout = 'd0;
-			3'b001: debug_reg_dout = r1;
-			3'b010: debug_reg_dout = r2;
-			3'b011: debug_reg_dout = r3;
-			3'b100: debug_reg_dout = r4;
-			3'b101: debug_reg_dout = r5;
-			3'b110: debug_reg_dout = r6;
-			3'b111: debug_reg_dout = r7;
+			4'b0000: debug_reg_dout = 'd0;
+			4'b0001: debug_reg_dout = r1;
+			4'b0010: debug_reg_dout = r2;
+			4'b0011: debug_reg_dout = r3;
+			4'b0100: debug_reg_dout = r4;
+			4'b0101: debug_reg_dout = r5;
+			4'b0110: debug_reg_dout = r6;
+			4'b0111: debug_reg_dout = r7;
+			4'b1000: debug_reg_dout = r8;
+			4'b1001: debug_reg_dout = r9;
+			4'b1010: debug_reg_dout = r10;
+			4'b1011: debug_reg_dout = r11;
+			4'b1100: debug_reg_dout = r12;
+			4'b1101: debug_reg_dout = r13;
+			4'b1110: debug_reg_dout = r14;
+			4'b1111: debug_reg_dout = r15;
 		endcase
 	end
 */