| commit | 739fa1dd63b388b66d1e9687f8caacb39bb68b69 | [log] [tgz] |
|---|---|---|
| author | embelon <78412338+embelon@users.noreply.github.com> | Sun Dec 04 22:14:09 2022 +0100 |
| committer | embelon <78412338+embelon@users.noreply.github.com> | Sun Dec 04 22:14:09 2022 +0100 |
| tree | b83748ec92b1191f1d37f0ab7dcf93819472bee0 | |
| parent | 99a51c2d4b4c0bc3a80be8104ca795c54967ead8 [diff] |
Initial version for submision.
Wishbone HyperRAM controller RTL: https://github.com/embelon/wb_hyperram PCB: https://github.com/embelon/hyperram_asic_pcb